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irq_asm.S @ 258ad71

Last change on this file since 258ad71 was 258ad71, checked in by Sebastian Huber <sebastian.huber@…>, on 09/25/15 at 12:34:24

SMP: Fix and optimize thread dispatching

According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.

Property mode set to 100644

File size: 30.0 KB

Line
1	/* cpu_asm.s
2	*
3	* This file contains the basic algorithms for all assembly code used
4	* in an specific CPU port of RTEMS. These algorithms must be implemented
5	* in assembly language.
6	*
7	* COPYRIGHT (c) 1989-2011.
8	* On-Line Applications Research Corporation (OAR).
9	*
10	* Copyright (c) 2014-2015 embedded brains GmbH
11	*
12	* The license and distribution terms for this file may be
13	* found in the file LICENSE in this distribution or at
14	* http://www.rtems.org/license/LICENSE.
15	*
16	* Ported to ERC32 implementation of the SPARC by On-Line Applications
17	* Research Corporation (OAR) under contract to the European Space
18	* Agency (ESA).
19	*
20	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
21	* European Space Agency.
22	*/
23
24	#include <rtems/asm.h>
25	#include <rtems/score/percpu.h>
26	#include <bspopts.h>
27
28	#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
29	#define FP_FRAME_OFFSET_FO_F1 (CPU_MINIMUM_STACK_FRAME_SIZE + 0)
30	#define FP_FRAME_OFFSET_F2_F3 (FP_FRAME_OFFSET_FO_F1 + 8)
31	#define FP_FRAME_OFFSET_F4_F5 (FP_FRAME_OFFSET_F2_F3 + 8)
32	#define FP_FRAME_OFFSET_F6_F7 (FP_FRAME_OFFSET_F4_F5 + 8)
33	#define FP_FRAME_OFFSET_F8_F9 (FP_FRAME_OFFSET_F6_F7 + 8)
34	#define FP_FRAME_OFFSET_F1O_F11 (FP_FRAME_OFFSET_F8_F9 + 8)
35	#define FP_FRAME_OFFSET_F12_F13 (FP_FRAME_OFFSET_F1O_F11 + 8)
36	#define FP_FRAME_OFFSET_F14_F15 (FP_FRAME_OFFSET_F12_F13 + 8)
37	#define FP_FRAME_OFFSET_F16_F17 (FP_FRAME_OFFSET_F14_F15 + 8)
38	#define FP_FRAME_OFFSET_F18_F19 (FP_FRAME_OFFSET_F16_F17 + 8)
39	#define FP_FRAME_OFFSET_F2O_F21 (FP_FRAME_OFFSET_F18_F19 + 8)
40	#define FP_FRAME_OFFSET_F22_F23 (FP_FRAME_OFFSET_F2O_F21 + 8)
41	#define FP_FRAME_OFFSET_F24_F25 (FP_FRAME_OFFSET_F22_F23 + 8)
42	#define FP_FRAME_OFFSET_F26_F27 (FP_FRAME_OFFSET_F24_F25 + 8)
43	#define FP_FRAME_OFFSET_F28_F29 (FP_FRAME_OFFSET_F26_F27 + 8)
44	#define FP_FRAME_OFFSET_F3O_F31 (FP_FRAME_OFFSET_F28_F29 + 8)
45	#define FP_FRAME_OFFSET_FSR (FP_FRAME_OFFSET_F3O_F31 + 8)
46	#define FP_FRAME_SIZE (FP_FRAME_OFFSET_FSR + 8)
47	#endif
48
49	/*
50	* void _CPU_Context_switch(
51	* Context_Control *run,
52	* Context_Control *heir
53	* )
54	*
55	* This routine performs a normal non-FP context switch.
56	*/
57
58	.align 4
59	PUBLIC(_CPU_Context_switch)
60	SYM(_CPU_Context_switch):
61	st %g5, [%o0 + G5_OFFSET] ! save the global registers
62	st %g7, [%o0 + G7_OFFSET]
63
64	std %l0, [%o0 + L0_OFFSET] ! save the local registers
65	std %l2, [%o0 + L2_OFFSET]
66	std %l4, [%o0 + L4_OFFSET]
67	std %l6, [%o0 + L6_OFFSET]
68
69	std %i0, [%o0 + I0_OFFSET] ! save the input registers
70	std %i2, [%o0 + I2_OFFSET]
71	std %i4, [%o0 + I4_OFFSET]
72	std %i6, [%o0 + I6_FP_OFFSET]
73
74	std %o6, [%o0 + O6_SP_OFFSET] ! save the output registers
75
76	! load the ISR stack nesting prevention flag
77	ld [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %o4
78	! save it a bit later so we do not waste a couple of cycles
79
80	rd %psr, %o2
81	st %o2, [%o0 + PSR_OFFSET] ! save status register
82
83	! Now actually save ISR stack nesting prevention flag
84	st %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
85
86	/*
87	* This is entered from _CPU_Context_restore with:
88	* o1 = context to restore
89	* o2 = psr
90	*/
91
92	PUBLIC(_CPU_Context_restore_heir)
93	SYM(_CPU_Context_restore_heir):
94	/*
95	* Flush all windows with valid contents except the current one.
96	* In examining the set register windows, one may logically divide
97	* the windows into sets (some of which may be empty) based on their
98	* current status:
99	*
100	* + current (i.e. in use),
101	* + used (i.e. a restore would not trap)
102	* + invalid (i.e. 1 in corresponding bit in WIM)
103	* + unused
104	*
105	* Either the used or unused set of windows may be empty.
106	*
107	* NOTE: We assume only one bit is set in the WIM at a time.
108	*
109	* Given a CWP of 5 and a WIM of 0x1, the registers are divided
110	* into sets as follows:
111	*
112	* + 0 - invalid
113	* + 1-4 - unused
114	* + 5 - current
115	* + 6-7 - used
116	*
117	* In this case, we only would save the used windows -- 6 and 7.
118	*
119	* Traps are disabled for the same logical period as in a
120	* flush all windows trap handler.
121	*
122	* Register Usage while saving the windows:
123	* g1 = current PSR
124	* g2 = current wim
125	* g3 = CWP
126	* g4 = wim scratch
127	* g5 = scratch
128	*/
129
130	ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr
131
132	and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
133	! g1 = psr w/o cwp
134	andn %g1, SPARC_PSR_ET_MASK \| SPARC_PSR_CWP_MASK, %g1
135	or %g1, %g3, %g1 ! g1 = heirs psr
136	mov %g1, %psr ! restore status register and
137	! ** DISABLE TRAPS **
138	mov %wim, %g2 ! g2 = wim
139	mov 1, %g4
140	sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
141
142	save_frame_loop:
143	sll %g4, 1, %g5 ! rotate the "wim" left 1
144	srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
145	or %g4, %g5, %g4 ! g4 = wim if we do one restore
146
147	/*
148	* If a restore would not underflow, then continue.
149	*/
150
151	andcc %g4, %g2, %g0 ! Any windows to flush?
152	bnz done_flushing ! No, then continue
153	nop
154
155	restore ! back one window
156
157	/*
158	* Now save the window just as if we overflowed to it.
159	*/
160
161	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
162	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
163	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
164	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
165
166	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
167	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
168	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
169	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
170
171	ba save_frame_loop
172	nop
173
174	done_flushing:
175
176	add %g3, 1, %g3 ! calculate desired WIM
177	and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
178	mov 1, %g4
179	sll %g4, %g3, %g4 ! g4 = new WIM
180	mov %g4, %wim
181
182	or %g1, SPARC_PSR_ET_MASK, %g1
183	mov %g1, %psr ! ** ENABLE TRAPS **
184	! and restore CWP
185	nop
186	nop
187	nop
188
189	#if defined(RTEMS_SMP)
190	! The executing context no longer executes on this processor
191	st %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
192
193	! Try to update the is executing indicator of the heir context
194	mov 1, %g1
195
196	try_update_is_executing:
197
198	swap [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
199	cmp %g1, 0
200	bne check_is_executing
201
202	! The next load is in a delay slot, which is all right
203	#endif
204
205	ld [%o1 + G5_OFFSET], %g5 ! restore the global registers
206	ld [%o1 + G7_OFFSET], %g7
207
208	! Load thread specific ISR dispatch prevention flag
209	ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
210	! Store it to memory later to use the cycles
211
212	ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
213	ldd [%o1 + L2_OFFSET], %l2
214	ldd [%o1 + L4_OFFSET], %l4
215	ldd [%o1 + L6_OFFSET], %l6
216
217	! Now restore thread specific ISR dispatch prevention flag
218	st %o2, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
219
220	ldd [%o1 + I0_OFFSET], %i0 ! restore the input registers
221	ldd [%o1 + I2_OFFSET], %i2
222	ldd [%o1 + I4_OFFSET], %i4
223	ldd [%o1 + I6_FP_OFFSET], %i6
224
225	ldd [%o1 + O6_SP_OFFSET], %o6 ! restore the output registers
226
227	jmp %o7 + 8 ! return
228	nop ! delay slot
229
230	#if defined(RTEMS_SMP)
231	check_is_executing:
232
233	! Check the is executing indicator of the heir context
234	ld [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
235	cmp %g1, 0
236	beq try_update_is_executing
237	mov 1, %g1
238
239	! We may have a new heir
240
241	! Read the executing and heir
242	ld [%g6 + PER_CPU_OFFSET_EXECUTING], %g1
243	ld [%g6 + PER_CPU_OFFSET_HEIR], %g2
244
245	! Update the executing only if necessary to avoid cache line
246	! monopolization.
247	cmp %g1, %g2
248	beq try_update_is_executing
249	mov 1, %g1
250
251	! Calculate the heir context pointer
252	sub %o1, %g1, %g1
253	add %g1, %g2, %o1
254
255	! Update the executing
256	st %g2, [%g6 + PER_CPU_OFFSET_EXECUTING]
257
258	ba try_update_is_executing
259	mov 1, %g1
260	#endif
261
262	/*
263	* void _CPU_Context_restore(
264	* Context_Control *new_context
265	* )
266	*
267	* This routine is generally used only to perform restart self.
268	*
269	* NOTE: It is unnecessary to reload some registers.
270	*/
271	.align 4
272	PUBLIC(_CPU_Context_restore)
273	SYM(_CPU_Context_restore):
274	save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
275	rd %psr, %o2
276	#if defined(RTEMS_SMP)
277	! On SPARC the restore path needs also a valid executing context on SMP
278	! to update the is executing indicator.
279	mov %i0, %o0
280	#endif
281	ba SYM(_CPU_Context_restore_heir)
282	mov %i0, %o1 ! in the delay slot
283
284	/*
285	* void _ISR_Handler()
286	*
287	* This routine provides the RTEMS interrupt management.
288	*
289	* We enter this handler from the 4 instructions in the trap table with
290	* the following registers assumed to be set as shown:
291	*
292	* l0 = PSR
293	* l1 = PC
294	* l2 = nPC
295	* l3 = trap type
296	*
297	* NOTE: By an executive defined convention, trap type is between 0 and 255 if
298	* it is an asynchonous trap and 256 and 511 if it is synchronous.
299	*/
300
301	.align 4
302	PUBLIC(_ISR_Handler)
303	SYM(_ISR_Handler):
304	/*
305	* Fix the return address for synchronous traps.
306	*/
307
308	andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
309	! Is this a synchronous trap?
310	be,a win_ovflow ! No, then skip the adjustment
311	nop ! DELAY
312	mov %l1, %l6 ! save trapped pc for debug info
313	mov %l2, %l1 ! do not return to the instruction
314	add %l2, 4, %l2 ! indicated
315
316	win_ovflow:
317	/*
318	* Save the globals this block uses.
319	*
320	* These registers are not restored from the locals. Their contents
321	* are saved directly from the locals into the ISF below.
322	*/
323
324	mov %g4, %l4 ! save the globals this block uses
325	mov %g5, %l5
326
327	/*
328	* When at a "window overflow" trap, (wim == (1 << cwp)).
329	* If we get here like that, then process a window overflow.
330	*/
331
332	rd %wim, %g4
333	srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
334	! are LS 5 bits ; how convenient :)
335	cmp %g5, 1 ! Is this an invalid window?
336	bne dont_do_the_window ! No, then skip all this stuff
337	! we are using the delay slot
338
339	/*
340	* The following is same as a 1 position right rotate of WIM
341	*/
342
343	srl %g4, 1, %g5 ! g5 = WIM >> 1
344	sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
345	! g4 = WIM << (Number Windows - 1)
346	or %g4, %g5, %g4 ! g4 = (WIM >> 1) \|
347	! (WIM << (Number Windows - 1))
348
349	/*
350	* At this point:
351	*
352	* g4 = the new WIM
353	* g5 is free
354	*/
355
356	/*
357	* Since we are tinkering with the register windows, we need to
358	* make sure that all the required information is in global registers.
359	*/
360
361	save ! Save into the window
362	wr %g4, 0, %wim ! WIM = new WIM
363	nop ! delay slots
364	nop
365	nop
366
367	/*
368	* Now save the window just as if we overflowed to it.
369	*/
370
371	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
372	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
373	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
374	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
375
376	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
377	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
378	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
379	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
380
381	restore
382	nop
383
384	dont_do_the_window:
385	/*
386	* Global registers %g4 and %g5 are saved directly from %l4 and
387	* %l5 directly into the ISF below.
388	*/
389
390	/*
391	* Save the state of the interrupted task -- especially the global
392	* registers -- in the Interrupt Stack Frame. Note that the ISF
393	* includes a regular minimum stack frame which will be used if
394	* needed by register window overflow and underflow handlers.
395	*
396	* REGISTERS SAME AS AT _ISR_Handler
397	*/
398
399	sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
400	! make space for ISF
401
402	std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
403	st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
404	st %g1, [%sp + ISF_G1_OFFSET] ! save g1
405	std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
406	std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
407	st %g7, [%sp + ISF_G7_OFFSET] ! save g7
408
409	std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
410	std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
411	std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
412	std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
413
414	rd %y, %g1
415	st %g1, [%sp + ISF_Y_OFFSET] ! save y
416	st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
417
418	mov %sp, %o1 ! 2nd arg to ISR Handler
419
420	/*
421	* Increment ISR nest level and Thread dispatch disable level.
422	*
423	* Register usage for this section:
424	*
425	* l6 = _Thread_Dispatch_disable_level value
426	* l7 = _ISR_Nest_level value
427	*
428	* NOTE: It is assumed that l6 - l7 will be preserved until the ISR
429	* nest and thread dispatch disable levels are unnested.
430	*/
431
432	ld [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
433	ld [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
434
435	add %l7, 1, %l7
436	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
437
438	add %l6, 1, %l6
439	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
440
441	#if SPARC_HAS_FPU == 1
442	/*
443	* We cannot use an intermediate value for operations with the PSR[EF]
444	* bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
445	*/
446	sethi %hi(SPARC_PSR_EF_MASK), %l5
447	#endif
448
449	/*
450	* If ISR nest level was zero (now 1), then switch stack.
451	*/
452
453	mov %sp, %fp
454	subcc %l7, 1, %l7 ! outermost interrupt handler?
455	bnz dont_switch_stacks ! No, then do not switch stacks
456
457	#if defined( RTEMS_PROFILING )
458	sethi %hi(SYM(_SPARC_Counter)), %o5
459	ld [%o5 + %lo(SYM(_SPARC_Counter))], %l4
460	ld [%l4], %o5
461	#else
462	nop
463	#endif
464
465	ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
466
467	#if SPARC_HAS_FPU == 1
468	/*
469	* Test if the interrupted thread uses the floating point unit
470	* (PSR[EF] == 1). In case it uses the floating point unit, then store
471	* the floating point status register. This has the side-effect that
472	* all pending floating point operations complete before the store
473	* completes. The PSR[EF] bit is restored after the call to the
474	* interrupt handler. Thus post-switch actions (e.g. signal handlers)
475	* and context switch extensions may still corrupt the floating point
476	* context.
477	*/
478	andcc %l0, %l5, %g0
479	bne,a dont_switch_stacks
480	st %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
481	#endif
482
483	dont_switch_stacks:
484	/*
485	* Make sure we have a place on the stack for the window overflow
486	* trap handler to write into. At this point it is safe to
487	* enable traps again.
488	*/
489
490	sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
491
492	/*
493	* Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
494	* set the PIL in the %psr to mask off interrupts with lower priority.
495	* The original %psr in %l0 is not modified since it will be restored
496	* when the interrupt handler returns.
497	*/
498
499	mov %l0, %g5
500	and %l3, 0x0ff, %g4
501	subcc %g4, 0x11, %g0
502	bl dont_fix_pil
503	subcc %g4, 0x1f, %g0
504	bg dont_fix_pil
505	sll %g4, 8, %g4
506	and %g4, SPARC_PSR_PIL_MASK, %g4
507	andn %l0, SPARC_PSR_PIL_MASK, %g5
508	ba pil_fixed
509	or %g4, %g5, %g5
510	dont_fix_pil:
511	or %g5, SPARC_PSR_PIL_MASK, %g5
512	pil_fixed:
513
514	#if SPARC_HAS_FPU == 1
515	/*
516	* Clear the PSR[EF] bit of the interrupted context to ensure that
517	* interrupt service routines cannot corrupt the floating point context.
518	*/
519	andn %g5, %l5, %g5
520	#endif
521
522	wr %g5, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
523
524	/*
525	* Vector to user's handler.
526	*
527	* NOTE: TBR may no longer have vector number in it since
528	* we just enabled traps. It is definitely in l3.
529	*/
530
531	sethi %hi(SYM(_ISR_Vector_table)), %g4
532	or %g4, %lo(SYM(_ISR_Vector_table)), %g4
533	and %l3, 0xFF, %g5 ! remove synchronous trap indicator
534	sll %g5, 2, %g5 ! g5 = offset into table
535	ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
536
537
538	! o1 = 2nd arg = address of the ISF
539	! WAS LOADED WHEN ISF WAS SAVED!!!
540	mov %l3, %o0 ! o0 = 1st arg = vector number
541	call %g4, 0
542	#if defined( RTEMS_PROFILING )
543	mov %o5, %l3 ! save interrupt entry instant
544	cmp %l7, 0
545	bne profiling_not_outer_most_exit
546	nop
547	ta SPARC_SWTRAP_IRQDIS ! Call interrupt disable trap handler
548	ld [%l4], %o2 ! o2 = 3rd arg = interrupt exit instant
549	mov %l3, %o1 ! o1 = 2nd arg = interrupt entry instant
550	call SYM(_Profiling_Outer_most_interrupt_entry_and_exit), 0
551	mov %g6, %o0 ! o0 = 1st arg = per-CPU control
552	profiling_not_outer_most_exit:
553	#else
554	nop ! delay slot
555	#endif
556
557	/*
558	* Redisable traps so we can finish up the interrupt processing.
559	* This is a VERY conservative place to do this.
560	*
561	* NOTE: %l0 has the PSR which was in place when we took the trap.
562	*/
563
564	mov %l0, %psr ! ** DISABLE TRAPS **
565	nop; nop; nop
566
567	/*
568	* Decrement ISR nest level and Thread dispatch disable level.
569	*
570	* Register usage for this section:
571	*
572	* l6 = _Thread_Dispatch_disable_level value
573	* l7 = _ISR_Nest_level value
574	*/
575
576	st %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
577
578	sub %l6, 1, %l6
579	st %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
580
581	/*
582	* If dispatching is disabled (includes nested interrupt case),
583	* then do a "simple" exit.
584	*/
585
586	orcc %l6, %g0, %g0 ! Is dispatching disabled?
587	bnz simple_return ! Yes, then do a "simple" exit
588	nop
589
590	! Are we dispatching from a previous ISR in the interrupted thread?
591	ld [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %l7
592	orcc %l7, %g0, %g0 ! Is this thread already doing an ISR?
593	bnz simple_return ! Yes, then do a "simple" exit
594	nop
595
596
597	/*
598	* If a context switch is necessary, then do fudge stack to
599	* return to the interrupt dispatcher.
600	*/
601
602	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %l6
603
604	orcc %l6, %g0, %g0 ! Is thread switch necessary?
605	bz simple_return ! no, then do a simple return
606	nop
607
608	/*
609	* Invoke interrupt dispatcher.
610	*/
611
612	! Set ISR dispatch nesting prevention flag
613	mov 1,%l6
614	st %l6, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
615
616	/*
617	* The following subtract should get us back on the interrupted
618	* tasks stack and add enough room to invoke the dispatcher.
619	* When we enable traps, we are mostly back in the context
620	* of the task and subsequent interrupts can operate normally.
621	*/
622
623	sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
624
625	or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1
626	mov %l7, %psr ! ** ENABLE TRAPS **
627	nop
628	nop
629	nop
630	isr_dispatch:
631
632	#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
633	/* Test if we interrupted a floating point thread (PSR[EF] == 1) */
634	andcc %l0, %l5, %g0
635	be non_fp_thread_dispatch
636	nop
637
638	/*
639	* Yes, this is a floating point thread, then save the floating point
640	* context to a new stack frame. Then do the thread dispatch.
641	* Post-switch actions (e.g. signal handlers) and context switch
642	* extensions may safely use the floating point unit.
643	*/
644	sub %sp, FP_FRAME_SIZE, %sp
645	std %f0, [%sp + FP_FRAME_OFFSET_FO_F1]
646	std %f2, [%sp + FP_FRAME_OFFSET_F2_F3]
647	std %f4, [%sp + FP_FRAME_OFFSET_F4_F5]
648	std %f6, [%sp + FP_FRAME_OFFSET_F6_F7]
649	std %f8, [%sp + FP_FRAME_OFFSET_F8_F9]
650	std %f10, [%sp + FP_FRAME_OFFSET_F1O_F11]
651	std %f12, [%sp + FP_FRAME_OFFSET_F12_F13]
652	std %f14, [%sp + FP_FRAME_OFFSET_F14_F15]
653	std %f16, [%sp + FP_FRAME_OFFSET_F16_F17]
654	std %f18, [%sp + FP_FRAME_OFFSET_F18_F19]
655	std %f20, [%sp + FP_FRAME_OFFSET_F2O_F21]
656	std %f22, [%sp + FP_FRAME_OFFSET_F22_F23]
657	std %f24, [%sp + FP_FRAME_OFFSET_F24_F25]
658	std %f26, [%sp + FP_FRAME_OFFSET_F26_F27]
659	std %f28, [%sp + FP_FRAME_OFFSET_F28_F29]
660	std %f30, [%sp + FP_FRAME_OFFSET_F3O_F31]
661	call SYM(_Thread_Dispatch), 0
662	st %fsr, [%sp + FP_FRAME_OFFSET_FSR]
663
664	/*
665	* Restore the floating point context from stack frame and release the
666	* stack frame.
667	*/
668	ldd [%sp + FP_FRAME_OFFSET_FO_F1], %f0
669	ldd [%sp + FP_FRAME_OFFSET_F2_F3], %f2
670	ldd [%sp + FP_FRAME_OFFSET_F4_F5], %f4
671	ldd [%sp + FP_FRAME_OFFSET_F6_F7], %f6
672	ldd [%sp + FP_FRAME_OFFSET_F8_F9], %f8
673	ldd [%sp + FP_FRAME_OFFSET_F1O_F11], %f10
674	ldd [%sp + FP_FRAME_OFFSET_F12_F13], %f12
675	ldd [%sp + FP_FRAME_OFFSET_F14_F15], %f14
676	ldd [%sp + FP_FRAME_OFFSET_F16_F17], %f16
677	ldd [%sp + FP_FRAME_OFFSET_F18_F19], %f18
678	ldd [%sp + FP_FRAME_OFFSET_F2O_F21], %f20
679	ldd [%sp + FP_FRAME_OFFSET_F22_F23], %f22
680	ldd [%sp + FP_FRAME_OFFSET_F24_F25], %f24
681	ldd [%sp + FP_FRAME_OFFSET_F26_F27], %f26
682	ldd [%sp + FP_FRAME_OFFSET_F28_F29], %f28
683	ldd [%sp + FP_FRAME_OFFSET_F3O_F31], %f30
684	ld [%sp + FP_FRAME_OFFSET_FSR], %fsr
685	ba thread_dispatch_done
686	add %sp, FP_FRAME_SIZE, %sp
687
688	non_fp_thread_dispatch:
689	#endif
690
691	call SYM(_Thread_Dispatch), 0
692	nop
693
694	#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
695	thread_dispatch_done:
696	#endif
697
698	/*
699	* We invoked _Thread_Dispatch in a state similar to the interrupted
700	* task. In order to safely be able to tinker with the register
701	* windows and get the task back to its pre-interrupt state,
702	* we need to disable interrupts disabled so we can safely tinker
703	* with the register windowing. In particular, the CWP in the PSR
704	* is fragile during this period. (See PR578.)
705	*/
706	ta SPARC_SWTRAP_IRQDIS ! syscall (disable interrupts)
707
708	/*
709	* While we had ISR dispatching disabled in this thread,
710	* did we miss anything. If so, then we need to do another
711	* _Thread_Dispatch before leaving this ISR Dispatch context.
712	*/
713	ldub [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
714
715	orcc %l7, %g0, %g0 ! Is thread switch necesary?
716	bne,a isr_dispatch ! Yes, then invoke the dispatcher.
717	! g1 = Old PSR PIL returned from IRQDis
718	ta SPARC_SWTRAP_IRQEN ! syscall (enable interrupts to same level)
719
720	! No, then clear out and return
721
722	! Zero out ISR stack nesting prevention flag
723	st %g0, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
724
725	/*
726	* The CWP in place at this point may be different from
727	* that which was in effect at the beginning of the ISR if we
728	* have been context switched between the beginning of this invocation
729	* of _ISR_Handler and this point. Thus the CWP and WIM should
730	* not be changed back to their values at ISR entry time. Any
731	* changes to the PSR must preserve the CWP.
732	*/
733
734	simple_return:
735	ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
736	wr %l5, 0, %y
737
738	ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
739	ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
740	rd %psr, %l3
741	and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
742	andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
743	or %l3, %l0, %l0 ! install it later...
744	andn %l0, SPARC_PSR_ET_MASK, %l0
745
746	/*
747	* Restore tasks global and out registers
748	*/
749
750	mov %fp, %g1
751
752	! g1 is restored later
753	ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
754	ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
755	ld [%fp + ISF_G7_OFFSET], %g7 ! restore g7
756
757	ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
758	ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
759	ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
760	ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
761
762	/*
763	* Registers:
764	*
765	* ALL global registers EXCEPT G1 and the input registers have
766	* already been restored and thuse off limits.
767	*
768	* The following is the contents of the local registers:
769	*
770	* l0 = original psr
771	* l1 = return address (i.e. PC)
772	* l2 = nPC
773	* l3 = CWP
774	*/
775
776	/*
777	* if (CWP + 1) is an invalid window then we need to reload it.
778	*
779	* WARNING: Traps should now be disabled
780	*/
781
782	mov %l0, %psr ! ** DISABLE TRAPS **
783	nop
784	nop
785	nop
786	rd %wim, %l4
787	add %l0, 1, %l6 ! l6 = cwp + 1
788	and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
789	srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
790	! and CWP are conveniently LS 5 bits
791	cmp %l5, 1 ! Is tasks window invalid?
792	bne good_task_window
793
794	/*
795	* The following code is the same as a 1 position left rotate of WIM.
796	*/
797
798	sll %l4, 1, %l5 ! l5 = WIM << 1
799	srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
800	! l4 = WIM >> (Number Windows - 1)
801	or %l4, %l5, %l4 ! l4 = (WIM << 1) \|
802	! (WIM >> (Number Windows - 1))
803
804	/*
805	* Now restore the window just as if we underflowed to it.
806	*/
807
808	wr %l4, 0, %wim ! WIM = new WIM
809	nop ! must delay after writing WIM
810	nop
811	nop
812	restore ! now into the tasks window
813
814	ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
815	ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
816	ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
817	ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
818	ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
819	ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
820	ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
821	ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
822	! reload of sp clobbers ISF
823	save ! Back to ISR dispatch window
824
825	good_task_window:
826
827	mov %l0, %psr ! ** DISABLE TRAPS **
828	nop; nop; nop
829	! and restore condition codes.
830	ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
831	jmp %l1 ! transfer control and
832	rett %l2 ! go back to tasks window
833
834	/* end of file */

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