[5d69cd3] | 1 | /* cpu_asm.s |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in an specific CPU port of RTEMS. These algorithms must be implemented |
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| 5 | * in assembly language. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1989-2011. |
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| 8 | * On-Line Applications Research Corporation (OAR). |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | * |
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| 14 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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| 15 | * Research Corporation (OAR) under contract to the European Space |
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| 16 | * Agency (ESA). |
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| 17 | * |
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| 18 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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| 19 | * European Space Agency. |
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| 20 | * |
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| 21 | * $Id$ |
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| 22 | */ |
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| 23 | |
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| 24 | #include <rtems/asm.h> |
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| 25 | #include <rtems/system.h> |
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| 26 | #include <bspopts.h> |
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| 27 | |
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| 28 | /* |
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| 29 | * void _ISR_Handler() |
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| 30 | * |
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| 31 | * This routine provides the RTEMS interrupt management. |
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| 32 | * |
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| 33 | * We enter this handler from the 4 instructions in the trap table with |
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| 34 | * the following registers assumed to be set as shown: |
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| 35 | * |
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| 36 | * l0 = PSR |
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| 37 | * l1 = PC |
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| 38 | * l2 = nPC |
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| 39 | * l3 = trap type |
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| 40 | * |
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| 41 | * NOTE: By an executive defined convention, trap type is between 0 and 255 if |
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| 42 | * it is an asynchonous trap and 256 and 511 if it is synchronous. |
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| 43 | */ |
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| 44 | |
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| 45 | .align 4 |
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| 46 | PUBLIC(_ISR_Handler) |
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| 47 | SYM(_ISR_Handler): |
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| 48 | /* |
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| 49 | * Fix the return address for synchronous traps. |
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| 50 | */ |
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| 51 | |
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| 52 | andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0 |
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| 53 | ! Is this a synchronous trap? |
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| 54 | be,a win_ovflow ! No, then skip the adjustment |
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| 55 | nop ! DELAY |
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| 56 | mov %l1, %l6 ! save trapped pc for debug info |
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| 57 | mov %l2, %l1 ! do not return to the instruction |
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| 58 | add %l2, 4, %l2 ! indicated |
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| 59 | |
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| 60 | win_ovflow: |
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| 61 | /* |
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| 62 | * Save the globals this block uses. |
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| 63 | * |
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| 64 | * These registers are not restored from the locals. Their contents |
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| 65 | * are saved directly from the locals into the ISF below. |
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| 66 | */ |
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| 67 | |
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| 68 | mov %g4, %l4 ! save the globals this block uses |
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| 69 | mov %g5, %l5 |
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| 70 | |
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| 71 | /* |
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| 72 | * When at a "window overflow" trap, (wim == (1 << cwp)). |
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| 73 | * If we get here like that, then process a window overflow. |
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| 74 | */ |
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| 75 | |
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| 76 | rd %wim, %g4 |
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| 77 | srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP |
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| 78 | ! are LS 5 bits ; how convenient :) |
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| 79 | cmp %g5, 1 ! Is this an invalid window? |
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| 80 | bne dont_do_the_window ! No, then skip all this stuff |
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| 81 | ! we are using the delay slot |
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| 82 | |
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| 83 | /* |
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| 84 | * The following is same as a 1 position right rotate of WIM |
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| 85 | */ |
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| 86 | |
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| 87 | srl %g4, 1, %g5 ! g5 = WIM >> 1 |
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| 88 | sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4 |
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| 89 | ! g4 = WIM << (Number Windows - 1) |
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| 90 | or %g4, %g5, %g4 ! g4 = (WIM >> 1) | |
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| 91 | ! (WIM << (Number Windows - 1)) |
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| 92 | |
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| 93 | /* |
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| 94 | * At this point: |
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| 95 | * |
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| 96 | * g4 = the new WIM |
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| 97 | * g5 is free |
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| 98 | */ |
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| 99 | |
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| 100 | /* |
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| 101 | * Since we are tinkering with the register windows, we need to |
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| 102 | * make sure that all the required information is in global registers. |
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| 103 | */ |
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| 104 | |
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| 105 | save ! Save into the window |
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| 106 | wr %g4, 0, %wim ! WIM = new WIM |
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| 107 | nop ! delay slots |
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| 108 | nop |
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| 109 | nop |
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| 110 | |
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| 111 | /* |
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| 112 | * Now save the window just as if we overflowed to it. |
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| 113 | */ |
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| 114 | |
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| 115 | std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET] |
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| 116 | std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET] |
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| 117 | std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET] |
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| 118 | std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET] |
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| 119 | |
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| 120 | std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET] |
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| 121 | std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET] |
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| 122 | std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET] |
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| 123 | std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET] |
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| 124 | |
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| 125 | restore |
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| 126 | nop |
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| 127 | |
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| 128 | dont_do_the_window: |
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| 129 | /* |
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| 130 | * Global registers %g4 and %g5 are saved directly from %l4 and |
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| 131 | * %l5 directly into the ISF below. |
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| 132 | */ |
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| 133 | |
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| 134 | save_isf: |
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| 135 | |
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| 136 | /* |
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| 137 | * Save the state of the interrupted task -- especially the global |
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| 138 | * registers -- in the Interrupt Stack Frame. Note that the ISF |
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| 139 | * includes a regular minimum stack frame which will be used if |
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| 140 | * needed by register window overflow and underflow handlers. |
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| 141 | * |
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| 142 | * REGISTERS SAME AS AT _ISR_Handler |
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| 143 | */ |
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| 144 | |
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| 145 | sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp |
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| 146 | ! make space for ISF |
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| 147 | |
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| 148 | std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC |
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| 149 | st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC |
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| 150 | st %g1, [%sp + ISF_G1_OFFSET] ! save g1 |
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| 151 | std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3 |
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| 152 | std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above |
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| 153 | std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7 |
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| 154 | |
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| 155 | std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1 |
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| 156 | std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3 |
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| 157 | std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5 |
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| 158 | std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7 |
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| 159 | |
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| 160 | rd %y, %g1 |
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| 161 | st %g1, [%sp + ISF_Y_OFFSET] ! save y |
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| 162 | st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc |
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| 163 | |
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| 164 | mov %sp, %o1 ! 2nd arg to ISR Handler |
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| 165 | |
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| 166 | /* |
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| 167 | * Check if we have an external interrupt (trap 0x11 - 0x1f). If so, |
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| 168 | * set the PIL in the %psr to mask off interrupts with lower priority. |
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| 169 | * The original %psr in %l0 is not modified since it will be restored |
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| 170 | * when the interrupt handler returns. |
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| 171 | */ |
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| 172 | |
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| 173 | mov %l0, %g5 |
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| 174 | and %l3, 0x0ff, %g4 |
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| 175 | |
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| 176 | /* This is a fix for ERC32 with FPU rev.B or rev.C */ |
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| 177 | |
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| 178 | #if defined(FPU_REVB) |
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| 179 | |
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| 180 | |
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| 181 | subcc %g4, 0x08, %g0 |
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| 182 | be fpu_revb |
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| 183 | subcc %g4, 0x11, %g0 |
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| 184 | bl dont_fix_pil |
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| 185 | subcc %g4, 0x1f, %g0 |
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| 186 | bg dont_fix_pil |
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| 187 | sll %g4, 8, %g4 |
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| 188 | and %g4, SPARC_PSR_PIL_MASK, %g4 |
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| 189 | andn %l0, SPARC_PSR_PIL_MASK, %g5 |
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| 190 | or %g4, %g5, %g5 |
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| 191 | srl %l0, 12, %g4 |
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| 192 | andcc %g4, 1, %g0 |
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| 193 | be dont_fix_pil |
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| 194 | nop |
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| 195 | ba,a enable_irq |
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| 196 | |
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| 197 | |
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| 198 | fpu_revb: |
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| 199 | srl %l0, 12, %g4 ! check if EF is set in %psr |
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| 200 | andcc %g4, 1, %g0 |
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| 201 | be dont_fix_pil ! if FPU disabled than continue as normal |
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| 202 | and %l3, 0xff, %g4 |
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| 203 | subcc %g4, 0x08, %g0 |
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| 204 | bne enable_irq ! if not a FPU exception then do two fmovs |
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| 205 | set __sparc_fq, %g4 |
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| 206 | st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs |
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| 207 | ld [%g4], %g4 ! than this is bug 3.14 |
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| 208 | srl %g4, 13, %g4 |
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| 209 | andcc %g4, 1, %g0 |
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| 210 | be dont_fix_pil |
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| 211 | set __sparc_fq, %g4 |
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| 212 | std %fq, [%g4] |
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| 213 | ld [%g4+4], %g4 |
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| 214 | set 0x81a00020, %g5 |
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| 215 | subcc %g4, %g5, %g0 |
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| 216 | bne,a dont_fix_pil2 |
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| 217 | wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** |
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| 218 | ba,a simple_return |
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| 219 | |
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| 220 | enable_irq: |
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| 221 | or %g5, SPARC_PSR_PIL_MASK, %g4 |
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| 222 | wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** |
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| 223 | nop; nop; nop |
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| 224 | fmovs %f0, %f0 |
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| 225 | ba dont_fix_pil |
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| 226 | fmovs %f0, %f0 |
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| 227 | |
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| 228 | .data |
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| 229 | .global __sparc_fq |
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| 230 | .align 8 |
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| 231 | __sparc_fq: |
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| 232 | .word 0,0 |
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| 233 | |
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| 234 | .text |
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| 235 | /* end of ERC32 FPU rev.B/C fix */ |
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| 236 | |
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| 237 | #else |
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| 238 | |
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| 239 | subcc %g4, 0x11, %g0 |
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| 240 | bl dont_fix_pil |
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| 241 | subcc %g4, 0x1f, %g0 |
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| 242 | bg dont_fix_pil |
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| 243 | sll %g4, 8, %g4 |
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| 244 | and %g4, SPARC_PSR_PIL_MASK, %g4 |
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| 245 | andn %l0, SPARC_PSR_PIL_MASK, %g5 |
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| 246 | ba pil_fixed |
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| 247 | or %g4, %g5, %g5 |
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| 248 | #endif |
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| 249 | |
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| 250 | dont_fix_pil: |
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| 251 | or %g5, SPARC_PSR_PIL_MASK, %g5 |
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| 252 | pil_fixed: |
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| 253 | wr %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS **** |
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| 254 | dont_fix_pil2: |
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| 255 | |
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[0bd3f7e] | 256 | PUBLIC(_ISR_PER_CPU) |
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| 257 | SYM(_ISR_PER_CPU): |
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| 258 | |
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| 259 | #if defined(RTEMS_SMP) |
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| 260 | sethi %hi(_Per_CPU_Information_p), %l5 |
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| 261 | add %l5, %lo(_Per_CPU_Information_p), %l5 |
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| 262 | #if BSP_LEON3_SMP |
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| 263 | /* LEON3 SMP support */ |
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| 264 | rd %asr17, %l7 |
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| 265 | srl %l7, 28, %l7 /* CPU number is upper 4 bits so shift */ |
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| 266 | sll %l7, 2, %l7 /* l7 = offset */ |
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| 267 | add %l5, %l7, %l5 |
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| 268 | #endif |
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| 269 | ld [%l5], %l5 /* l5 = pointer to per CPU */ |
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| 270 | |
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| 271 | /* |
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| 272 | * On multi-core system, we need to use SMP safe versions |
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| 273 | * of ISR and Thread Dispatch critical sections. |
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| 274 | * |
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| 275 | * _ISR_SMP_Enter returns the interrupt nest level. If we are |
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| 276 | * outermost interrupt, then we need to switch stacks. |
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| 277 | */ |
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| 278 | call SYM(_ISR_SMP_Enter), 0 |
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[47a61aa1] | 279 | mov %sp, %fp ! delay slot |
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[0bd3f7e] | 280 | cmp %o0, 0 |
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| 281 | #else |
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| 282 | /* |
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| 283 | * On single core system, we can directly use variables. |
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| 284 | * |
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| 285 | * Increment ISR nest level and Thread dispatch disable level. |
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| 286 | * |
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| 287 | * Register usage for this section: |
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| 288 | * |
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| 289 | * l4 = _Thread_Dispatch_disable_level pointer |
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| 290 | * l5 = _ISR_Nest_level pointer |
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| 291 | * l6 = _Thread_Dispatch_disable_level value |
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| 292 | * l7 = _ISR_Nest_level value |
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| 293 | * |
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| 294 | * NOTE: It is assumed that l4 - l7 will be preserved until the ISR |
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| 295 | * nest and thread dispatch disable levels are unnested. |
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| 296 | */ |
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| 297 | sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 |
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| 298 | ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6 |
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| 299 | |
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| 300 | sethi %hi(_Per_CPU_Information), %l5 |
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| 301 | add %l5, %lo(_Per_CPU_Information), %l5 |
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| 302 | |
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| 303 | ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7 |
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| 304 | |
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| 305 | add %l6, 1, %l6 |
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| 306 | st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] |
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| 307 | |
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| 308 | add %l7, 1, %l7 |
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| 309 | st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL] |
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| 310 | |
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| 311 | /* |
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| 312 | * If ISR nest level was zero (now 1), then switch stack. |
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| 313 | */ |
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| 314 | mov %sp, %fp |
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| 315 | subcc %l7, 1, %l7 ! outermost interrupt handler? |
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| 316 | #endif |
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| 317 | |
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| 318 | /* |
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| 319 | * Do we need to switch to the interrupt stack? |
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| 320 | */ |
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[47a61aa1] | 321 | beq,a dont_switch_stacks ! No, then do not switch stacks |
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| 322 | ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp |
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[0bd3f7e] | 323 | |
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| 324 | dont_switch_stacks: |
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| 325 | /* |
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| 326 | * Make sure we have a place on the stack for the window overflow |
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| 327 | * trap handler to write into. At this point it is safe to |
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| 328 | * enable traps again. |
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| 329 | */ |
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| 330 | |
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| 331 | sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 332 | |
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[5d69cd3] | 333 | /* |
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| 334 | * Vector to user's handler. |
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| 335 | * |
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| 336 | * NOTE: TBR may no longer have vector number in it since |
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| 337 | * we just enabled traps. It is definitely in l3. |
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| 338 | */ |
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| 339 | |
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| 340 | sethi %hi(SYM(_ISR_Vector_table)), %g4 |
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| 341 | ld [%g4+%lo(SYM(_ISR_Vector_table))], %g4 |
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| 342 | and %l3, 0xFF, %g5 ! remove synchronous trap indicator |
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| 343 | sll %g5, 2, %g5 ! g5 = offset into table |
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| 344 | ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] |
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| 345 | |
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| 346 | |
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| 347 | ! o1 = 2nd arg = address of the ISF |
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| 348 | ! WAS LOADED WHEN ISF WAS SAVED!!! |
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| 349 | mov %l3, %o0 ! o0 = 1st arg = vector number |
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| 350 | call %g4, 0 |
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| 351 | nop ! delay slot |
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| 352 | |
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[0bd3f7e] | 353 | #if defined(RTEMS_SMP) |
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| 354 | call SYM(_ISR_SMP_Exit), 0 |
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| 355 | nop ! delay slot |
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| 356 | cmp %o0, 0 |
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| 357 | bz simple_return |
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[47a61aa1] | 358 | nop |
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[0bd3f7e] | 359 | #else |
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| 360 | !sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 |
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| 361 | !ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7 |
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| 362 | !ld [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6 |
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| 363 | #endif |
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| 364 | |
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[5d69cd3] | 365 | /* |
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| 366 | * Redisable traps so we can finish up the interrupt processing. |
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| 367 | * This is a VERY conservative place to do this. |
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| 368 | * |
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| 369 | * NOTE: %l0 has the PSR which was in place when we took the trap. |
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| 370 | */ |
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| 371 | |
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| 372 | mov %l0, %psr ! **** DISABLE TRAPS **** |
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| 373 | nop; nop; nop |
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| 374 | |
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[0bd3f7e] | 375 | #if !defined(RTEMS_SMP) |
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[5d69cd3] | 376 | /* |
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| 377 | * Decrement ISR nest level and Thread dispatch disable level. |
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| 378 | * |
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| 379 | * Register usage for this section: |
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| 380 | * |
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| 381 | * l4 = _Thread_Dispatch_disable_level pointer |
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| 382 | * l5 = _ISR_Nest_level pointer |
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| 383 | * l6 = _Thread_Dispatch_disable_level value |
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| 384 | * l7 = _ISR_Nest_level value |
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| 385 | */ |
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| 386 | |
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| 387 | sub %l6, 1, %l6 |
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| 388 | st %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))] |
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| 389 | |
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| 390 | st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL] |
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| 391 | |
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| 392 | /* |
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| 393 | * If dispatching is disabled (includes nested interrupt case), |
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| 394 | * then do a "simple" exit. |
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| 395 | */ |
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| 396 | |
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| 397 | orcc %l6, %g0, %g0 ! Is dispatching disabled? |
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| 398 | bnz simple_return ! Yes, then do a "simple" exit |
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| 399 | ! NOTE: Use the delay slot |
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| 400 | sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %l6 |
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| 401 | |
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| 402 | ! Are we dispatching from a previous ISR in the interrupted thread? |
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| 403 | ld [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7 |
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| 404 | orcc %l7, %g0, %g0 ! Is this thread already doing an ISR? |
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| 405 | bnz simple_return ! Yes, then do a "simple" exit |
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[47a61aa1] | 406 | nop |
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[5d69cd3] | 407 | |
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| 408 | /* |
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| 409 | * If a context switch is necessary, then do fudge stack to |
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| 410 | * return to the interrupt dispatcher. |
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| 411 | */ |
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| 412 | |
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| 413 | ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5 |
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| 414 | orcc %l5, %g0, %g0 ! Is thread switch necessary? |
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| 415 | bz simple_return ! No, then return |
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[47a61aa1] | 416 | nop |
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[0bd3f7e] | 417 | #endif |
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[5d69cd3] | 418 | /* |
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| 419 | * Invoke interrupt dispatcher. |
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| 420 | */ |
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| 421 | |
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| 422 | PUBLIC(_ISR_Dispatch) |
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| 423 | SYM(_ISR_Dispatch): |
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| 424 | ! Set ISR dispatch nesting prevention flag |
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| 425 | mov 1,%l6 |
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| 426 | sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5 |
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| 427 | st %l6,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))] |
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| 428 | |
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| 429 | /* |
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| 430 | * The following subtract should get us back on the interrupted |
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| 431 | * tasks stack and add enough room to invoke the dispatcher. |
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| 432 | * When we enable traps, we are mostly back in the context |
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| 433 | * of the task and subsequent interrupts can operate normally. |
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| 434 | */ |
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| 435 | |
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| 436 | sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp |
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| 437 | |
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| 438 | or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1 |
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| 439 | mov %l7, %psr ! **** ENABLE TRAPS **** |
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| 440 | nop |
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| 441 | nop |
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| 442 | nop |
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| 443 | isr_dispatch: |
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| 444 | call SYM(_Thread_Dispatch), 0 |
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| 445 | nop |
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| 446 | |
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| 447 | /* |
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| 448 | * We invoked _Thread_Dispatch in a state similar to the interrupted |
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| 449 | * task. In order to safely be able to tinker with the register |
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| 450 | * windows and get the task back to its pre-interrupt state, |
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| 451 | * we need to disable interrupts disabled so we can safely tinker |
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| 452 | * with the register windowing. In particular, the CWP in the PSR |
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| 453 | * is fragile during this period. (See PR578.) |
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| 454 | */ |
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| 455 | mov 2,%g1 ! syscall (disable interrupts) |
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| 456 | ta 0 ! syscall (disable interrupts) |
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| 457 | |
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| 458 | /* |
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| 459 | * While we had ISR dispatching disabled in this thread, |
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| 460 | * did we miss anything. If so, then we need to do another |
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| 461 | * _Thread_Dispatch before leaving this ISR Dispatch context. |
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| 462 | */ |
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| 463 | |
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| 464 | #if defined(RTEMS_SMP) |
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| 465 | sethi %hi(_Per_CPU_Information_p), %l5 |
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| 466 | ld [%l5 + %lo(_Per_CPU_Information_p)], %l5 |
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| 467 | #if BSP_LEON3_SMP |
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| 468 | /* LEON3 SMP support */ |
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| 469 | rd %asr17, %l7 |
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| 470 | srl %l7, 28, %l7 /* CPU number is upper 4 bits so shift */ |
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| 471 | sll %l7, 2, %l7 /* l7 = offset */ |
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| 472 | add %l5, %l7, %l5 |
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| 473 | #else |
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| 474 | nop |
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| 475 | nop |
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| 476 | #endif |
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| 477 | ld [%l5], %l5 /* l5 = pointer to per CPU */ |
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| 478 | #else |
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| 479 | sethi %hi(_Per_CPU_Information), %l5 |
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| 480 | add %l5, %lo(_Per_CPU_Information), %l5 |
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| 481 | #endif |
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| 482 | ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5 |
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| 483 | orcc %l5, %g0, %g0 ! Is thread switch necessary? |
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| 484 | bz allow_nest_again |
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| 485 | nop |
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| 486 | |
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| 487 | ! Yes, then invoke the dispatcher |
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| 488 | dispatchAgain: |
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| 489 | mov 3,%g1 ! syscall (enable interrupts) |
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| 490 | ta 0 ! syscall (enable interrupts) |
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| 491 | ba isr_dispatch |
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| 492 | nop |
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| 493 | |
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| 494 | allow_nest_again: |
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| 495 | |
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| 496 | ! Zero out ISR stack nesting prevention flag |
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| 497 | sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5 |
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| 498 | st %g0,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))] |
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| 499 | |
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| 500 | /* |
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| 501 | * The CWP in place at this point may be different from |
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| 502 | * that which was in effect at the beginning of the ISR if we |
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| 503 | * have been context switched between the beginning of this invocation |
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| 504 | * of _ISR_Handler and this point. Thus the CWP and WIM should |
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| 505 | * not be changed back to their values at ISR entry time. Any |
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| 506 | * changes to the PSR must preserve the CWP. |
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| 507 | */ |
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| 508 | |
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| 509 | simple_return: |
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| 510 | ld [%fp + ISF_Y_OFFSET], %l5 ! restore y |
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| 511 | wr %l5, 0, %y |
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| 512 | |
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| 513 | ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC |
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| 514 | ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC |
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| 515 | rd %psr, %l3 |
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| 516 | and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP |
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| 517 | andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task |
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| 518 | or %l3, %l0, %l0 ! install it later... |
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| 519 | andn %l0, SPARC_PSR_ET_MASK, %l0 |
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| 520 | |
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| 521 | /* |
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| 522 | * Restore tasks global and out registers |
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| 523 | */ |
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| 524 | |
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| 525 | mov %fp, %g1 |
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| 526 | |
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| 527 | ! g1 is restored later |
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| 528 | ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3 |
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| 529 | ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5 |
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| 530 | ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7 |
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| 531 | |
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| 532 | ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1 |
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| 533 | ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3 |
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| 534 | ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5 |
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| 535 | ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7 |
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| 536 | |
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| 537 | /* |
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| 538 | * Registers: |
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| 539 | * |
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| 540 | * ALL global registers EXCEPT G1 and the input registers have |
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| 541 | * already been restored and thuse off limits. |
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| 542 | * |
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| 543 | * The following is the contents of the local registers: |
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| 544 | * |
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| 545 | * l0 = original psr |
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| 546 | * l1 = return address (i.e. PC) |
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| 547 | * l2 = nPC |
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| 548 | * l3 = CWP |
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| 549 | */ |
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| 550 | |
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| 551 | /* |
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| 552 | * if (CWP + 1) is an invalid window then we need to reload it. |
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| 553 | * |
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| 554 | * WARNING: Traps should now be disabled |
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| 555 | */ |
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| 556 | |
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| 557 | mov %l0, %psr ! **** DISABLE TRAPS **** |
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| 558 | nop |
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| 559 | nop |
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| 560 | nop |
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| 561 | rd %wim, %l4 |
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| 562 | add %l0, 1, %l6 ! l6 = cwp + 1 |
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| 563 | and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it |
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| 564 | srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count |
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| 565 | ! and CWP are conveniently LS 5 bits |
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| 566 | cmp %l5, 1 ! Is tasks window invalid? |
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| 567 | bne good_task_window |
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| 568 | |
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| 569 | /* |
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| 570 | * The following code is the same as a 1 position left rotate of WIM. |
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| 571 | */ |
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| 572 | |
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| 573 | sll %l4, 1, %l5 ! l5 = WIM << 1 |
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| 574 | srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4 |
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| 575 | ! l4 = WIM >> (Number Windows - 1) |
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| 576 | or %l4, %l5, %l4 ! l4 = (WIM << 1) | |
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| 577 | ! (WIM >> (Number Windows - 1)) |
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| 578 | |
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| 579 | /* |
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| 580 | * Now restore the window just as if we underflowed to it. |
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| 581 | */ |
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| 582 | |
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| 583 | wr %l4, 0, %wim ! WIM = new WIM |
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| 584 | nop ! must delay after writing WIM |
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| 585 | nop |
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| 586 | nop |
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| 587 | restore ! now into the tasks window |
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| 588 | |
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| 589 | ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0 |
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| 590 | ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2 |
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| 591 | ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4 |
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| 592 | ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6 |
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| 593 | ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0 |
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| 594 | ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2 |
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| 595 | ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4 |
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| 596 | ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6 |
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| 597 | ! reload of sp clobbers ISF |
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| 598 | save ! Back to ISR dispatch window |
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| 599 | |
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| 600 | good_task_window: |
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| 601 | |
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| 602 | mov %l0, %psr ! **** DISABLE TRAPS **** |
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| 603 | nop; nop; nop |
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| 604 | ! and restore condition codes. |
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| 605 | ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1 |
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| 606 | jmp %l1 ! transfer control and |
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| 607 | rett %l2 ! go back to tasks window |
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| 608 | |
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| 609 | /* end of file */ |
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