1 | /* |
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2 | * Driver for GRLIB port of OpenCores I2C-master |
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3 | * |
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4 | * COPYRIGHT (c) 2007 Gaisler Research |
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5 | * with parts from the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH. |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * This file contains the driver declarations |
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12 | */ |
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13 | #ifndef _I2CMST_H |
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14 | #define _I2CMST_H |
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15 | |
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16 | #include <rtems/libi2c.h> |
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17 | #include <ambapp.h> |
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18 | |
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19 | #ifdef __cplusplus |
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20 | extern "C" { |
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21 | #endif |
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22 | |
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23 | /* I2C-master operational registers */ |
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24 | |
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25 | typedef struct gr_i2cmst_regs { |
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26 | volatile unsigned int prescl; /* Prescale register */ |
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27 | volatile unsigned int ctrl; /* Control register */ |
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28 | volatile unsigned int tdrd; /* Transmit and Receive registers */ |
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29 | volatile unsigned int cmdsts; /* Command and Status registers */ |
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30 | } gr_i2cmst_regs_t; |
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31 | |
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32 | /* Control (CTRL) register */ |
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33 | #define GRI2C_CTRL_EN 0x00000080 /* Enable core */ |
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34 | #define GRI2C_CTRL_IEN 0x00000040 /* Interrupt enable */ |
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35 | |
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36 | /* Command (CMD) register */ |
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37 | #define GRI2C_CMD_STA 0x00000080 /* Generate START condition */ |
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38 | #define GRI2C_CMD_STO 0x00000040 /* Generate STOP condition */ |
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39 | #define GRI2C_CMD_RD 0x00000020 /* Read from slave */ |
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40 | #define GRI2C_CMD_WR 0x00000010 /* Write to slave */ |
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41 | #define GRI2C_CMD_ACK 0x00000008 /* Acknowledge */ |
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42 | #define GRI2C_CMD_IACK 0x00000001 /* Interrupt acknowledge */ |
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43 | |
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44 | /* Status (STS) register */ |
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45 | #define GRI2C_STS_RXACK 0x00000080 /* Receive acknowledge */ |
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46 | #define GRI2C_STS_BUSY 0x00000040 /* I2C-bus busy */ |
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47 | #define GRI2C_STS_AL 0x00000020 /* Arbitration lost */ |
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48 | #define GRI2C_STS_TIP 0x00000002 /* Transfer in progress */ |
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49 | #define GRI2C_STS_IF 0x00000001 /* Interrupt flag */ |
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50 | |
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51 | #define GRI2C_STATUS_IDLE 0x00000000 |
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52 | |
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53 | /* The OC I2C core will perform a write after a start unless the RD bit |
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54 | in the command register has been set. Since the rtems framework has |
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55 | a send_start function we buffer that command and use it when the first |
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56 | data is written. The START is buffered in the sendstart member below */ |
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57 | typedef struct gr_i2cmst_prv { |
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58 | gr_i2cmst_regs_t *reg_ptr; |
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59 | unsigned int sysfreq; /* System clock frequency in kHz */ |
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60 | unsigned char sendstart; /* START events are buffered here */ |
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61 | /* rtems_irq_number irq_number; */ |
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62 | /* rtems_id irq_sema_id; */ |
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63 | } gr_i2cmst_prv_t; |
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64 | |
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65 | typedef struct gr_i2cmst_desc { |
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66 | rtems_libi2c_bus_t bus_desc; |
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67 | gr_i2cmst_prv_t prv; |
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68 | } gr_i2cmst_desc_t; |
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69 | |
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70 | /* Scans for I2CMST core and initalizes i2c library */ |
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71 | rtems_status_code leon_register_i2c(amba_confarea_type *abus); |
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72 | |
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73 | #ifdef __cplusplus |
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74 | } |
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75 | #endif |
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76 | |
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77 | #endif /* _I2CMST_H */ |
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