source: rtems/c/src/lib/libbsp/sparc/shared/include/i2cmst.h @ 44b06ca

4.104.115
Last change on this file since 44b06ca was 44b06ca, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/29/09 at 15:33:28

Whitespace removal.

  • Property mode set to 100644
File size: 2.6 KB
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1/*
2 * Driver for GRLIB port of OpenCores I2C-master
3 *
4 * COPYRIGHT (c) 2007 Gaisler Research
5 * with parts from the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH.
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.com/license/LICENSE.
10 *
11 * This file contains the driver declarations
12 */
13#ifndef _I2CMST_H
14#define _I2CMST_H
15
16#include <rtems/libi2c.h>
17#include <ambapp.h>
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/* I2C-master operational registers */
24
25typedef struct gr_i2cmst_regs {
26  volatile unsigned int prescl; /* Prescale register */
27  volatile unsigned int ctrl;   /* Control register */
28  volatile unsigned int tdrd;   /* Transmit and Receive registers */
29  volatile unsigned int cmdsts; /* Command and Status registers */
30} gr_i2cmst_regs_t;
31
32/* Control (CTRL) register */
33#define GRI2C_CTRL_EN         0x00000080 /* Enable core */
34#define GRI2C_CTRL_IEN        0x00000040 /* Interrupt enable */
35
36/* Command (CMD) register */
37#define GRI2C_CMD_STA         0x00000080 /* Generate START condition */
38#define GRI2C_CMD_STO         0x00000040 /* Generate STOP condition */
39#define GRI2C_CMD_RD          0x00000020 /* Read from slave */
40#define GRI2C_CMD_WR          0x00000010 /* Write to slave */
41#define GRI2C_CMD_ACK         0x00000008 /* Acknowledge */
42#define GRI2C_CMD_IACK        0x00000001 /* Interrupt acknowledge */
43
44/* Status (STS) register */
45#define GRI2C_STS_RXACK       0x00000080 /* Receive acknowledge */
46#define GRI2C_STS_BUSY        0x00000040 /* I2C-bus busy */
47#define GRI2C_STS_AL          0x00000020 /* Arbitration lost */
48#define GRI2C_STS_TIP         0x00000002 /* Transfer in progress */
49#define GRI2C_STS_IF          0x00000001 /* Interrupt flag */
50
51#define GRI2C_STATUS_IDLE     0x00000000
52
53/* The OC I2C core will perform a write after a start unless the RD bit
54   in the command register has been set. Since the rtems framework has
55   a send_start function we buffer that command and use it when the first
56   data is written. The START is buffered in the sendstart member below */
57typedef struct gr_i2cmst_prv {
58  gr_i2cmst_regs_t    *reg_ptr;
59  unsigned int        sysfreq;     /* System clock frequency in kHz */
60  unsigned char       sendstart;   /* START events are buffered here */
61  /* rtems_irq_number irq_number; */
62  /* rtems_id         irq_sema_id; */
63} gr_i2cmst_prv_t;
64
65typedef struct gr_i2cmst_desc {
66  rtems_libi2c_bus_t  bus_desc;
67  gr_i2cmst_prv_t     prv;
68} gr_i2cmst_desc_t;
69
70/* Scans for I2CMST core and initalizes i2c library */
71rtems_status_code leon_register_i2c(amba_confarea_type *abus);
72
73#ifdef __cplusplus
74}
75#endif
76
77#endif /*  _I2CMST_H */
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