source: rtems/c/src/lib/libbsp/sparc/shared/include/grspw_router.h @ cc40f0b

5
Last change on this file since cc40f0b was cc40f0b, checked in by Javier Jalle <javier.jalle@…>, on 10/10/17 at 15:22:40

leon, grspw_router: Move register bit defs to header
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File size: 15.0 KB
Line 
1/*
2 * GRSPW ROUTER APB-Register Driver.
3 *
4 * COPYRIGHT (c) 2010-2017.
5 * Cobham Gaisler AB.
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.org/license/LICENSE.
10 */
11
12#ifndef __GRSPW_ROUTER_H__
13#define __GRSPW_ROUTER_H__
14
15#ifdef __cplusplus
16extern "C" {
17#endif
18
19/* Maximum number of ROUTER devices supported by driver */
20#define ROUTER_MAX 2
21
22#define ROUTER_ERR_OK 0
23#define ROUTER_ERR_EINVAL -1
24#define ROUTER_ERR_ERROR -2
25#define ROUTER_ERR_TOOMANY -3
26#define ROUTER_ERR_IMPLEMENTED -4
27
28/* Hardware Information */
29struct router_hw_info {
30        uint8_t nports_spw;
31        uint8_t nports_amba;
32        uint8_t nports_fifo;
33        int8_t srouting;
34        int8_t pnp_enable;
35        int8_t timers_avail;
36        int8_t pnp_avail;
37        uint8_t ver_major;
38        uint8_t ver_minor;
39        uint8_t ver_patch;
40        uint8_t iid;
41
42        /* Router capabilities */
43        uint8_t amba_port_fifo_size;
44        uint8_t spw_port_fifo_size;
45        uint8_t rmap_maxdlen;
46        int8_t aux_async;
47        int8_t aux_dist_int_support;
48        int8_t dual_port_support;
49        int8_t dist_int_support;
50        int8_t spwd_support;
51        uint8_t pktcnt_support;
52        uint8_t charcnt_support;
53};
54
55#define ROUTER_FLG_CFG          0x01
56#define ROUTER_FLG_IID          0x02
57#define ROUTER_FLG_IDIV         0x04
58#define ROUTER_FLG_TPRES        0x08
59#define ROUTER_FLG_TRLD         0x10
60#define ROUTER_FLG_ALL          0x1f    /* All Above Flags */
61
62struct router_config {
63        uint32_t flags; /* Determine what configuration should be updated */
64
65        /* Router Configuration Register */
66        uint32_t config;
67
68        /* Set Instance ID */
69        uint8_t iid;
70
71        /* SpaceWire Link Initialization Clock Divisor */
72        uint8_t idiv;
73
74        /* Timer Prescaler */
75        uint32_t timer_prescaler;
76};
77
78/* Routing table address control */
79struct router_route_acontrol {
80        uint32_t control[31];
81        uint32_t control_logical[224];
82};
83
84/* Routing table port mapping */
85struct router_route_portmap {
86        uint32_t pmap[31]; /* Port Setup for ports 1-31 */
87        uint32_t pmap_logical[224]; /* Port setup for locgical addresses 32-255 */
88};
89
90/* Routing table */
91#define ROUTER_ROUTE_FLG_MAP 0x01
92#define ROUTER_ROUTE_FLG_CTRL 0x02
93#define ROUTER_ROUTE_FLG_ALL 0x3        /* All Above Flags */
94struct router_routing_table {
95        uint32_t flags; /* Determine what configuration should be updated */
96
97        struct router_route_acontrol acontrol;
98        struct router_route_portmap portmap;
99};
100
101/* Set/Get Port Control/Status */
102#define ROUTER_PORT_FLG_SET_CTRL        0x01
103#define ROUTER_PORT_FLG_GET_CTRL        0x02
104#define ROUTER_PORT_FLG_SET_STS 0x04
105#define ROUTER_PORT_FLG_GET_STS 0x08
106#define ROUTER_PORT_FLG_SET_CTRL2       0x10
107#define ROUTER_PORT_FLG_GET_CTRL2       0x20
108#define ROUTER_PORT_FLG_SET_TIMER       0x40
109#define ROUTER_PORT_FLG_GET_TIMER       0x80
110#define ROUTER_PORT_FLG_SET_PKTLEN      0x100
111#define ROUTER_PORT_FLG_GET_PKTLEN      0x200
112struct router_port {
113        uint32_t flag;
114        /* Port control */
115        uint32_t ctrl;
116        /* Port status */
117        uint32_t sts;
118        /* Port control 2 */
119        uint32_t ctrl2;
120        /* Timer  Reload */
121        uint32_t timer_reload;
122        /* Maximum packet length */
123        uint32_t packet_length;
124};
125
126/* Register GRSPW Router driver to Driver Manager */
127void router_register_drv(void);
128
129extern void *router_open(unsigned int dev_no);
130extern int router_close(void *d);
131extern int router_print(void *d);
132extern int router_hwinfo_get(void *d, struct router_hw_info *hwinfo);
133
134/* Router general config */
135extern int router_config_set(void *d, struct router_config *cfg);
136extern int router_config_get(void *d, struct router_config *cfg);
137
138/* Routing table config */
139extern int router_routing_table_set(void *d,
140                struct router_routing_table *cfg);
141extern int router_routing_table_get(void *d,
142                struct router_routing_table *cfg);
143
144/*
145 * ROUTER PCTRL register fields
146 */
147#define PCTRL_RD (0xff << PCTRL_RD_BIT)
148#define PCTRL_ST (0x1 << PCTRL_ST_BIT)
149#define PCTRL_SR (0x1 << PCTRL_SR_BIT)
150#define PCTRL_AD (0x1 << PCTRL_AD_BIT)
151#define PCTRL_LR (0x1 << PCTRL_LR_BIT)
152#define PCTRL_PL (0x1 << PCTRL_PL_BIT)
153#define PCTRL_TS (0x1 << PCTRL_TS_BIT)
154#define PCTRL_IC (0x1 << PCTRL_IC_BIT)
155#define PCTRL_ET (0x1 << PCTRL_ET_BIT)
156#define PCTRL_NP (0x1 << PCTRL_NP_BIT)
157#define PCTRL_PS (0x1 << PCTRL_PS_BIT)
158#define PCTRL_BE (0x1 << PCTRL_BE_BIT)
159#define PCTRL_DI (0x1 << PCTRL_DI_BIT)
160#define PCTRL_TR (0x1 << PCTRL_TR_BIT)
161#define PCTRL_PR (0x1 << PCTRL_PR_BIT)
162#define PCTRL_TF (0x1 << PCTRL_TF_BIT)
163#define PCTRL_RS (0x1 << PCTRL_RS_BIT)
164#define PCTRL_TE (0x1 << PCTRL_TE_BIT)
165#define PCTRL_CE (0x1 << PCTRL_CE_BIT)
166#define PCTRL_AS (0x1 << PCTRL_AS_BIT)
167#define PCTRL_LS (0x1 << PCTRL_LS_BIT)
168#define PCTRL_LD (0x1 << PCTRL_LD_BIT)
169
170#define PCTRL_RD_BIT 24
171#define PCTRL_ST_BIT 21
172#define PCTRL_SR_BIT 20
173#define PCTRL_AD_BIT 19
174#define PCTRL_LR_BIT 18
175#define PCTRL_PL_BIT 17
176#define PCTRL_TS_BIT 16
177#define PCTRL_IC_BIT 15
178#define PCTRL_ET_BIT 14
179#define PCTRL_NP_BIT 13
180#define PCTRL_PS_BIT 12
181#define PCTRL_BE_BIT 11
182#define PCTRL_DI_BIT 10
183#define PCTRL_TR_BIT 9
184#define PCTRL_PR_BIT 8
185#define PCTRL_TF_BIT 7
186#define PCTRL_RS_BIT 6
187#define PCTRL_TE_BIT 5
188#define PCTRL_CE_BIT 3
189#define PCTRL_AS_BIT 2
190#define PCTRL_LS_BIT 1
191#define PCTRL_LD_BIT 0
192
193/*
194 * ROUTER PCTRL2 register fields
195 */
196#define PCTRL2_SM (0xff << PCTRL2_SM_BIT)
197#define PCTRL2_SV (0xff << PCTRL2_SV_BIT)
198#define PCTRL2_OR (0x1 << PCTRL2_OR_BIT)
199#define PCTRL2_UR (0x1 << PCTRL2_UR_BIT)
200#define PCTRL2_AT (0x1 << PCTRL2_AT_BIT)
201#define PCTRL2_AR (0x1 << PCTRL2_AR_BIT)
202#define PCTRL2_IT (0x1 << PCTRL2_IT_BIT)
203#define PCTRL2_IR (0x1 << PCTRL2_IR_BIT)
204#define PCTRL2_SD (0x1f << PCTRL2_SD_BIT)
205#define PCTRL2_SC (0x1f << PCTRL2_SC_BIT)
206
207#define PCTRL2_SM_BIT 24
208#define PCTRL2_SV_BIT 16
209#define PCTRL2_OR_BIT 15
210#define PCTRL2_UR_BIT 14
211#define PCTRL2_AT_BIT 12
212#define PCTRL2_AR_BIT 11
213#define PCTRL2_IT_BIT 10
214#define PCTRL2_IR_BIT 9
215#define PCTRL2_SD_BIT 1
216#define PCTRL2_SC_BIT 0
217
218/* Router Set/Get Port configuration */
219extern int router_port_ioc(void *d, int port, struct router_port *cfg);
220
221/* Read Port Control register */
222extern int router_port_ctrl_get(void *d, int port, uint32_t *ctrl);
223/* Read Port Control2 register */
224extern int router_port_ctrl2_get(void *d, int port, uint32_t *ctrl2);
225/* Write Port Control Register */
226extern int router_port_ctrl_set(void *d, int port, uint32_t ctrl);
227/* Write Port Control2 Register */
228extern int router_port_ctrl2_set(void *d, int port, uint32_t ctrl2);
229/* Set Timer Reload Value for a specific port */
230extern int router_port_treload_set(void *d, int port, uint32_t reload);
231/* Get Timer Reload Value for a specific port */
232extern int router_port_treload_get(void *d, int port, uint32_t *reload);
233/* Get Maximum packet length for a specific port */
234extern int router_port_maxplen_get(void *d, int port, uint32_t *length);
235/* Set Maximum packet length for a specific port */
236extern int router_port_maxplen_set(void *d, int port, uint32_t length);
237
238/*
239 * ROUTER PSTSCFG register fields
240 */
241#define PSTSCFG_EO (0x1 << PSTSCFG_EO_BIT)
242#define PSTSCFG_EE (0x1 << PSTSCFG_EE_BIT)
243#define PSTSCFG_PL (0x1 << PSTSCFG_PL_BIT)
244#define PSTSCFG_TT (0x1 << PSTSCFG_TT_BIT)
245#define PSTSCFG_PT (0x1 << PSTSCFG_PT_BIT)
246#define PSTSCFG_HC (0x1 << PSTSCFG_HC_BIT)
247#define PSTSCFG_PI (0x1 << PSTSCFG_PI_BIT)
248#define PSTSCFG_CE (0x1 << PSTSCFG_CE_BIT)
249#define PSTSCFG_EC (0xf << PSTSCFG_EC_BIT)
250#define PSTSCFG_TS (0x1 << PSTSCFG_TS_BIT)
251#define PSTSCFG_ME (0x1 << PSTSCFG_ME_BIT)
252#define PSTSCFG_IP (0x1f << PSTSCFG_IP_BIT)
253#define PSTSCFG_CP (0x1 << PSTSCFG_CP_BIT)
254#define PSTSCFG_PC (0xf << PSTSCFG_PC_BIT)
255#define PSTSCFG_WCLEAR (PSTSCFG_EO | PSTSCFG_EE | PSTSCFG_PL | \
256                                                PSTSCFG_TT | PSTSCFG_PT | PSTSCFG_HC | \
257                                                PSTSCFG_PI | PSTSCFG_CE | PSTSCFG_TS | \
258                                                PSTSCFG_ME | PSTSCFG_CP)
259#define PSTSCFG_WCLEAR2 (PSTSCFG_CE | PSTSCFG_CP)
260
261#define PSTSCFG_EO_BIT 31
262#define PSTSCFG_EE_BIT 30
263#define PSTSCFG_PL_BIT 29
264#define PSTSCFG_TT_BIT 28
265#define PSTSCFG_PT_BIT 27
266#define PSTSCFG_HC_BIT 26
267#define PSTSCFG_PI_BIT 25
268#define PSTSCFG_CE_BIT 24
269#define PSTSCFG_EC_BIT 20
270#define PSTSCFG_TS_BIT 18
271#define PSTSCFG_ME_BIT 17
272#define PSTSCFG_IP_BIT 7
273#define PSTSCFG_CP_BIT 4
274#define PSTSCFG_PC_BIT 0
275
276/*
277 * ROUTER PSTS register fields
278 */
279#define PSTS_PT (0x3 << PSTS_PT_BIT)
280#define PSTS_PL (0x1 << PSTS_PL_BIT)
281#define PSTS_TT (0x1 << PSTS_TT_BIT)
282#define PSTS_RS (0x1 << PSTS_RS_BIT)
283#define PSTS_SR (0x1 << PSTS_SR_BIT)
284#define PSTS_LR (0x1 << PSTS_LR_BIT)
285#define PSTS_SP (0x1 << PSTS_SP_BIT)
286#define PSTS_AC (0x1 << PSTS_AC_BIT)
287#define PSTS_TS (0x1 << PSTS_TS_BIT)
288#define PSTS_ME (0x1 << PSTS_ME_BIT)
289#define PSTS_TF (0x1 << PSTS_TF_BIT)
290#define PSTS_RE (0x1 << PSTS_RE_BIT)
291#define PSTS_LS (0x7 << PSTS_LS_BIT)
292#define PSTS_IP (0x1f << PSTS_IP_BIT)
293#define PSTS_PR (0x1 << PSTS_PR_BIT)
294#define PSTS_PB (0x1 << PSTS_PB_BIT)
295#define PSTS_IA (0x1 << PSTS_IA_BIT)
296#define PSTS_CE (0x1 << PSTS_CE_BIT)
297#define PSTS_ER (0x1 << PSTS_ER_BIT)
298#define PSTS_DE (0x1 << PSTS_DE_BIT)
299#define PSTS_PE (0x1 << PSTS_PE_BIT)
300#define PSTS_WCLEAR (PSTS_PL | PSTS_TT | PSTS_RS | PSTS_SR | \
301                                         PSTS_TS | PSTS_ME | PSTS_IA | PSTS_CE | \
302                                         PSTS_ER | PSTS_DE | PSTS_PE)
303
304#define PSTS_PT_BIT 30
305#define PSTS_PL_BIT 29
306#define PSTS_TT_BIT 28
307#define PSTS_RS_BIT 27
308#define PSTS_SR_BIT 26
309#define PSTS_LR_BIT 22
310#define PSTS_SP_BIT 21
311#define PSTS_AC_BIT 20
312#define PSTS_TS_BIT 18
313#define PSTS_ME_BIT 17
314#define PSTS_TF_BIT 16
315#define PSTS_RE_BIT 15
316#define PSTS_LS_BIT 12
317#define PSTS_IP_BIT 7
318#define PSTS_PR_BIT 6
319#define PSTS_PB_BIT 5
320#define PSTS_IA_BIT 4
321#define PSTS_CE_BIT 3
322#define PSTS_ER_BIT 2
323#define PSTS_DE_BIT 1
324#define PSTS_PE_BIT 0
325
326/* Check Port Status register and clear errors if there are */
327extern int router_port_status(void *d, int port, uint32_t *sts);
328
329#define ROUTER_LINK_STATUS_ERROR_RESET 0
330#define ROUTER_LINK_STATUS_ERROR_WAIT 1
331#define ROUTER_LINK_STATUS_READY 2
332#define ROUTER_LINK_STATUS_STARTED 3
333#define ROUTER_LINK_STATUS_CONNECTING 4
334#define ROUTER_LINK_STATUS_RUN_STATE 5
335/* Get Link status */
336extern int router_port_link_status(void *d, int port);
337/* Operate a Link */
338extern int router_port_enable(void *d, int port);
339extern int router_port_disable(void *d, int port);
340extern int router_port_link_stop(void *d, int port);
341extern int router_port_link_start(void *d, int port);
342extern int router_port_link_receive_spill(void *d, int port);
343extern int router_port_link_transmit_reset(void *d, int port);
344
345/* Get port credit counter register */
346extern int router_port_cred_get(void *d, int port, uint32_t *cred);
347
348/*
349 * ROUTER RTACTRL register fields
350 */
351#define RTACTRL_SR (0x1 << RTACTRL_SR_BIT)
352#define RTACTRL_EN (0x1 << RTACTRL_EN_BIT)
353#define RTACTRL_PR (0x1 << RTACTRL_PR_BIT)
354#define RTACTRL_HD (0x1 << RTACTRL_HD_BIT)
355
356#define RTACTRL_SR_BIT 3
357#define RTACTRL_EN_BIT 2
358#define RTACTRL_PR_BIT 1
359#define RTACTRL_HD_BIT 0
360
361/* Individual route modification */
362#define ROUTER_ROUTE_PACKETDISTRIBUTION_ENABLE (0x1 << 16)
363#define ROUTER_ROUTE_PACKETDISTRIBUTION_DISABLE (0x0 << 16)
364#define ROUTER_ROUTE_SPILLIFNOTREADY_ENABLE RTACTRL_SR
365#define ROUTER_ROUTE_SPILLIFNOTREADY_DISABLE 0
366#define ROUTER_ROUTE_ENABLE RTACTRL_EN
367#define ROUTER_ROUTE_DISABLE 0
368#define ROUTER_ROUTE_PRIORITY_HIGH RTACTRL_PR
369#define ROUTER_ROUTE_PRIORITY_LOW 0
370#define ROUTER_ROUTE_HEADERDELETION_ENABLE RTACTRL_HD
371#define ROUTER_ROUTE_HEADERDELETION_DISABLE 0
372struct router_route {
373        uint8_t from_address;
374        uint8_t to_port[32];
375        int count;
376        int options;
377};
378extern int router_route_set(void *d, struct router_route *route);
379extern int router_route_get(void *d, struct router_route *route);
380
381/* Router configuration port write enable */
382extern int router_write_enable(void *d);
383extern int router_write_disable(void *d);
384
385/* Router reset */
386extern int router_reset(void *d);
387
388/* Set Instance ID */
389extern int router_instance_set(void *d, uint8_t iid);
390/* Get Instance ID */
391extern int router_instance_get(void *d, uint8_t *iid);
392
393/* Set SpaceWire Link Initialization Clock Divisor */
394extern int router_idiv_set(void *d, uint8_t idiv);
395/* Get SpaceWire Link Initialization Clock Divisor */
396extern int router_idiv_get(void *d, uint8_t *idiv);
397
398/* Set Timer Prescaler */
399extern int router_tpresc_set(void *d, uint32_t prescaler);
400/* Get Timer Prescaler */
401extern int router_tpresc_get(void *d, uint32_t *prescaler);
402
403/* Set/get Router configuration */
404extern int router_cfgsts_set(void *d, uint32_t cfgsts);
405extern int router_cfgsts_get(void *d, uint32_t *cfgsts);
406
407/* Router timecode */
408extern int router_tc_enable(void *d);
409extern int router_tc_disable(void *d);
410extern int router_tc_reset(void *d);
411extern int router_tc_get(void *d);
412
413/* Router Interrupts */
414/*
415 * ROUTER IMASK register fields
416 */
417#define IMASK_PE (0x1 << IMASK_PE_BIT)
418#define IMASK_SR (0x1 << IMASK_SR_BIT)
419#define IMASK_RS (0x1 << IMASK_RS_BIT)
420#define IMASK_TT (0x1 << IMASK_TT_BIT)
421#define IMASK_PL (0x1 << IMASK_PL_BIT)
422#define IMASK_TS (0x1 << IMASK_TS_BIT)
423#define IMASK_AC (0x1 << IMASK_AC_BIT)
424#define IMASK_RE (0x1 << IMASK_RE_BIT)
425#define IMASK_IA (0x1 << IMASK_IA_BIT)
426#define IMASK_LE (0x1 << IMASK_LE_BIT)
427#define IMASK_ME (0x1 << IMASK_ME_BIT)
428#define IMASK_ALL ( IMASK_PE | IMASK_SR | IMASK_RS | IMASK_TT \
429                IMASK_PL | IMASK_TS | IMASK_AC | IMASK_RE | IMASK_IA \
430                IMASK_LE | IMASK_ME)
431
432#define IMASK_PE_BIT 10
433#define IMASK_SR_BIT 9
434#define IMASK_RS_BIT 8
435#define IMASK_TT_BIT 7
436#define IMASK_PL_BIT 6
437#define IMASK_TS_BIT 5
438#define IMASK_AC_BIT 4
439#define IMASK_RE_BIT 3
440#define IMASK_IA_BIT 2
441#define IMASK_LE_BIT 1
442#define IMASK_ME_BIT 0
443
444#define ROUTER_INTERRUPT_ALL IMASK_ALL
445#define ROUTER_INTERRUPT_SPWPNP_ERROR IMASK_PE
446#define ROUTER_INTERRUPT_SPILLED IMASK_SR
447#define ROUTER_INTERRUPT_RUNSTATE IMASK_RS
448#define ROUTER_INTERRUPT_TC_TRUNCATION IMASK_TT
449#define ROUTER_INTERRUPT_PACKET_TRUNCATION IMASK_PL
450#define ROUTER_INTERRUPT_TIMEOUT IMASK_TS
451#define ROUTER_INTERRUPT_CFGPORT IMASK_AC
452#define ROUTER_INTERRUPT_RMAP_ERROR IMASK_RE
453#define ROUTER_INTERRUPT_INVALID_ADDRESS IMASK_IA
454#define ROUTER_INTERRUPT_LINK_ERROR IMASK_LE
455#define ROUTER_INTERRUPT_MEMORY_ERROR IMASK_ME
456extern int router_port_interrupt_unmask(void *d, int port);
457extern int router_port_interrupt_mask(void *d, int port);
458extern int router_interrupt_unmask(void *d, int options);
459extern int router_interrupt_mask(void *d, int options);
460
461/* Router Interrupt code generation */
462/*
463 * ROUTER ICODEGEN register fields
464 */
465#define ICODEGEN_UA (0x1 << ICODEGEN_UA_BIT)
466#define ICODEGEN_AH (0x1 << ICODEGEN_AH_BIT)
467#define ICODEGEN_IT (0x1 << ICODEGEN_IT_BIT)
468#define ICODEGEN_TE (0x1 << ICODEGEN_TE_BIT)
469#define ICODEGEN_EN (0x1 << ICODEGEN_EN_BIT)
470#define ICODEGEN_IN (0x1f << ICODEGEN_IN_BIT)
471
472#define ICODEGEN_UA_BIT 20
473#define ICODEGEN_AH_BIT 19
474#define ICODEGEN_IT_BIT 18
475#define ICODEGEN_TE_BIT 17
476#define ICODEGEN_EN_BIT 16
477#define ICODEGEN_IN_BIT 0
478
479#define ROUTER_ICODEGEN_ITYPE_EDGE ICODEGEN_IT
480#define ROUTER_ICODEGEN_ITYPE_LEVEL 0
481#define ROUTER_ICODEGEN_AUTOUNACK_ENABLE ICODEGEN_UA
482#define ROUTER_ICODEGEN_AUTOUNACK_DISABLE 0
483#define ROUTER_ICODEGEN_AUTOACK_ENABLE ICODEGEN_AH
484#define ROUTER_ICODEGEN_AUTOACK_DISABLE 0
485extern int router_icodegen_enable(void *d, uint8_t intn, uint32_t aitimer,
486                int options);
487extern int router_icodegen_disable(void *d);
488
489/* Router interrupt change timers */
490extern int router_isrctimer_set(void *d, uint32_t reloadvalue);
491extern int router_isrctimer_get(void *d, uint32_t *reloadvalue);
492
493/* Router interrupt timers */
494extern int router_isrtimer_set(void *d, uint32_t reloadvalue);
495extern int router_isrtimer_get(void *d, uint32_t *reloadvalue);
496
497#ifdef __cplusplus
498}
499#endif
500
501#endif
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