source: rtems/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h @ ef94150f

5
Last change on this file since ef94150f was ef94150f, checked in by Daniel Hellstrom <daniel@…>, on Apr 12, 2016 at 11:53:42 AM

leon, grspw_pkt: Added checks for special list cases

  • Fixed grspw_dma_tx_send() so that it does not fail when an empty user packet is provided.
  • Added empty checks on some of the list handling inline functions for GRSPW_PKT. Their use by the driver may be correct already, but the user might not have been aware of the assumptions that certain lists had to be non-empty.
  • Property mode set to 100644
File size: 23.9 KB
Line 
1/*
2 *  GRSPW/GRSPW2 SpaceWire Kernel Library Interface
3 *
4 *  COPYRIGHT (c) 2011
5 *  Cobham Gaisler AB
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11
12#ifndef __GRSPW_PKT_H__
13#define __GRSPW_PKT_H__
14
15struct grspw_pkt;
16
17/* Maximum number of GRSPW devices supported by driver */
18#define GRSPW_MAX 32
19
20/* Weak overridable variable the user can use to define the worker-task
21 * priority (0..255) or to disable (-1) the creation of the worker-task
22 * and the message queue to save space */
23extern int grspw_work_task_priority;
24
25#ifndef GRSPW_PKT_FLAGS
26#define GRSPW_PKT_FLAGS
27/*** TX Packet flags ***/
28
29/* Enable IRQ generation */
30#define TXPKT_FLAG_IE 0x0040
31
32/* Enable Header CRC generation (if CRC is available in HW)
33 * Header CRC will be appended (one byte at end of header)
34 */
35#define TXPKT_FLAG_HCRC 0x0100
36
37/* Enable Data CRC generation (if CRC is available in HW)
38 * Data CRC will be appended (one byte at end of packet)
39 */
40#define TXPKT_FLAG_DCRC 0x0200
41
42/* Control how many bytes the beginning of the Header
43 * the CRC should not be calculated for */
44#define TXPKT_FLAG_NOCRC_MASK 0x0000000f
45#define TXPKT_FLAG_NOCRC_LEN0 0x00000000
46#define TXPKT_FLAG_NOCRC_LEN1 0x00000001
47#define TXPKT_FLAG_NOCRC_LEN2 0x00000002
48#define TXPKT_FLAG_NOCRC_LEN3 0x00000003
49#define TXPKT_FLAG_NOCRC_LEN4 0x00000004
50#define TXPKT_FLAG_NOCRC_LEN5 0x00000005
51#define TXPKT_FLAG_NOCRC_LEN6 0x00000006
52#define TXPKT_FLAG_NOCRC_LEN7 0x00000007
53#define TXPKT_FLAG_NOCRC_LEN8 0x00000008
54#define TXPKT_FLAG_NOCRC_LEN9 0x00000009
55#define TXPKT_FLAG_NOCRC_LENa 0x0000000a
56#define TXPKT_FLAG_NOCRC_LENb 0x0000000b
57#define TXPKT_FLAG_NOCRC_LENc 0x0000000c
58#define TXPKT_FLAG_NOCRC_LENd 0x0000000d
59#define TXPKT_FLAG_NOCRC_LENe 0x0000000e
60#define TXPKT_FLAG_NOCRC_LENf 0x0000000f
61
62#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \
63                                TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC)
64
65/* Marks if packet was transmitted or not */
66#define TXPKT_FLAG_TX 0x4000
67
68/* Link Error */
69#define TXPKT_FLAG_LINKERR 0x8000
70
71#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR)
72
73/*** RX Packet Flags ***/
74
75/* Enable IRQ generation */
76#define RXPKT_FLAG_IE 0x0010
77
78#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE)
79
80/* Packet was truncated */
81#define RXPKT_FLAG_TRUNK 0x0800
82/* Data CRC error (only valid if RMAP CRC is enabled) */
83#define RXPKT_FLAG_DCRC 0x0400
84/* Header CRC error (only valid if RMAP CRC is enabled) */
85#define RXPKT_FLAG_HCRC 0x0200
86/* Error in End-of-Packet */
87#define RXPKT_FLAG_EEOP 0x0100
88/* Marks if packet was recevied or not */
89#define RXPKT_FLAG_RX 0x8000
90
91#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \
92                                RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP)
93
94/*** General packet flag options ***/
95
96/* Translate Hdr and/or Payload address */
97#define PKT_FLAG_TR_DATA 0x1000
98#define PKT_FLAG_TR_HDR 0x2000
99/* All General options */
100#define PKT_FLAG_MASK 0x3000
101
102#endif
103/* GRSPW RX/TX Packet structure.
104 *
105 * - For RX the 'hdr' and 'hlen' fields are not used, they are not written
106 *   by driver.
107 *
108 * - The 'pkt_id' field is untouched by driver, it is intended for packet
109 *   numbering or user-custom data.
110 *
111 * - The last packet in a list must have 'next' set to NULL.
112 *
113 * - data and hdr pointers are written without modification to hardware,
114 *   this means that caller must do address translation to hardware
115 *   address itself.
116 *
117 * - the 'flags' field are interpreted differently depending on transfer
118 *   type (RX/TX). See XXPKT_FLAG_* options above.
119 */
120struct grspw_pkt {
121        struct grspw_pkt *next; /* Next packet in list. NULL if last packet */
122        unsigned int pkt_id;    /* User assigned ID (not touched by driver) */
123        unsigned short flags;   /* RX/TX Options and status */
124        unsigned char reserved; /* Reserved, must be zero */
125        unsigned char hlen;     /* Length of Header Buffer (only TX) */
126        unsigned int dlen;      /* Length of Data Buffer */
127        void *data;     /* 4-byte or byte aligned depends on HW */
128        void *hdr;      /* 4-byte or byte aligned depends on HW (only TX) */
129};
130
131/* GRSPW SpaceWire Packet List */
132struct grspw_list {
133        struct grspw_pkt *head;
134        struct grspw_pkt *tail;
135};
136
137/* SpaceWire Link State */
138typedef enum {
139        SPW_LS_ERRRST = 0,
140        SPW_LS_ERRWAIT = 1,
141        SPW_LS_READY = 2,
142        SPW_LS_CONNECTING = 3,
143        SPW_LS_STARTED = 4,
144        SPW_LS_RUN = 5
145} spw_link_state_t;
146
147/* Address Configuration */
148struct grspw_addr_config {
149        /* Ignore address field and put all received packets to first
150         * DMA channel.
151         */
152        int promiscuous;
153
154        /* Default Node Address and Mask */
155        unsigned char def_addr;
156        unsigned char def_mask;
157        /* DMA Channel custom Node Address and Mask */
158        struct {
159                char node_en;                   /* Enable Separate Addr */
160                unsigned char node_addr;        /* Node address */
161                unsigned char node_mask;        /* Node address mask */
162        } dma_nacfg[4];
163};
164
165/* Hardware Support in GRSPW Core */
166struct grspw_hw_sup {
167        char    rmap;           /* If RMAP in HW is available */
168        char    rmap_crc;       /* If RMAP CRC is available */
169        char    rx_unalign;     /* RX unaligned (byte boundary) access allowed*/
170        char    nports;         /* Number of Ports (1 or 2) */
171        char    ndma_chans;     /* Number of DMA Channels (1..4) */
172        char    strip_adr;      /* Hardware can strip ADR from packet data */
173        char    strip_pid;      /* Hardware can strip PID from packet data */
174        int     hw_version;     /* GRSPW Hardware Version */
175        char    reserved[2];
176        char    irq;            /* SpW Distributed Interrupt available if 1 */
177        char    irq_num;        /* Number of interrupts that can be generated */
178        char    itmr_width;     /* SpW Intr. ISR timers bit width. 0=no timer */
179};
180
181struct grspw_core_stats {
182        int irq_cnt;
183        int err_credit;
184        int err_eeop;
185        int err_addr;
186        int err_parity;
187        int err_disconnect;
188        int err_escape;
189        int err_wsync; /* only in GRSPW1 */
190};
191
192/* grspw_link_ctrl() options */
193#define LINKOPTS_ENABLE         0x0000
194#define LINKOPTS_DISABLE        0x0001
195#define LINKOPTS_START          0x0002
196#define LINKOPTS_AUTOSTART      0x0004
197#define LINKOPTS_DIS_ONERR      0x0008  /* Disable DMA transmitter on link error
198                                         * Controls LE bit in DMACTRL register.
199                                         */
200#define LINKOPTS_DIS_ON_CE      0x0020000/* Disable Link on Credit error */
201#define LINKOPTS_DIS_ON_ER      0x0040000/* Disable Link on Escape error */
202#define LINKOPTS_DIS_ON_DE      0x0080000/* Disable Link on Disconnect error */
203#define LINKOPTS_DIS_ON_PE      0x0100000/* Disable Link on Parity error */
204#define LINKOPTS_DIS_ON_WE      0x0400000/* Disable Link on write synchonization
205                                          * error (GRSPW1 only)
206                                          */
207#define LINKOPTS_DIS_ON_EE      0x1000000/* Disable Link on Early EOP/EEP error*/
208
209/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */
210#define LINKOPTS_EIRQ           0x0200  /* Enable Error Link IRQ */
211
212#define LINKOPTS_MASK           0x15e020f/* All above options */
213#define LINKOPTS_MASK_DIS_ON    0x15e0000/* All disable link on error options
214                                          * On a certain error the link disable
215                                          * bit will be written and the work
216                                          * task will call dma_stop() for all
217                                          * channels.
218                                          */
219
220#define LINKSTS_CE              0x002   /* Credit error */
221#define LINKSTS_ER              0x004   /* Escape error */
222#define LINKSTS_DE              0x008   /* Disconnect error */
223#define LINKSTS_PE              0x010   /* Parity error */
224#define LINKSTS_WE              0x040   /* Write synchonization error (GRSPW1 only) */
225#define LINKSTS_IA              0x080   /* Invalid address */
226#define LINKSTS_EE              0x100   /* Early EOP/EEP */
227#define LINKSTS_MASK            0x1de
228
229/* grspw_tc_ctrl() options */
230#define TCOPTS_EN_RXIRQ 0x0001  /* Tick-Out IRQ */
231#define TCOPTS_EN_TX    0x0004
232#define TCOPTS_EN_RX    0x0008
233
234/* grspw_ic_ctrl() options:
235 * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines
236 */
237#define ICOPTS_INTNUM           (0x1f << 27)
238#define ICOPTS_EN_SPWIRQ_ON_EE  (1 << 24)
239#define ICOPTS_EN_SPWIRQ_ON_IA  (1 << 23)
240#define ICOPTS_EN_PRIO          (1 << 22)
241#define ICOPTS_EN_TIMEOUTIRQ    (1 << 20)
242#define ICOPTS_EN_ACKIRQ        (1 << 19)
243#define ICOPTS_EN_TICKOUTIRQ    (1 << 18)
244#define ICOPTS_EN_RX            (1 << 17)
245#define ICOPTS_EN_TX            (1 << 16)
246#define ICOPTS_BASEIRQ          (0x1f << 8)
247#define ICOPTS_EN_FLAGFILTER    (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */
248
249/* grspw_ic_rlisr() and grspw_ic_rlintack()  */
250#define ICRELOAD_EN             (1 << 31)
251#define ICRELOAD_MASK           0x7fffffff
252
253/* grspw_rmap_ctrl() options */
254#define RMAPOPTS_EN_RMAP        0x0001
255#define RMAPOPTS_EN_BUF         0x0002
256
257/* grspw_dma_config.flags options */
258#define DMAFLAG_NO_SPILL        0x0001  /* See HW doc DMA-CTRL NS bit */
259#define DMAFLAG_RESV1           0x0002  /* HAS NO EFFECT */
260#define DMAFLAG_STRIP_ADR       0x0004  /* See HW doc DMA-CTRL SA bit */
261#define DMAFLAG_STRIP_PID       0x0008  /* See HW doc DMA-CTRL SP bit */
262#define DMAFLAG_RESV2           0x0010  /* HAS NO EFFECT */
263#define DMAFLAG_MASK    (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID)
264/* grspw_dma_config.flags misc options (not shifted internally) */
265#define DMAFLAG2_TXIE   0x00100000      /* See HW doc DMA-CTRL TI bit.
266                                         * Used to enable TX DMA interrupt
267                                         * when tx_irq_en_cnt=0.
268                                         */
269#define DMAFLAG2_RXIE   0x00200000      /* See HW doc DMA-CTRL RI bit.
270                                         * Used to enable RX DMA interrupt
271                                         * when rx_irq_en_cnt=0.
272                                         */
273#define DMAFLAG2_MASK   (DMAFLAG2_TXIE | DMAFLAG2_RXIE)
274
275struct grspw_dma_config {
276        int flags;              /* DMA config flags, see DMAFLAG1&2_* options */
277        int rxmaxlen;           /* RX Max Packet Length */
278        int rx_irq_en_cnt;      /* Enable RX IRQ every cnt descriptors */
279        int tx_irq_en_cnt;      /* Enable TX IRQ every cnt descriptors */
280};
281
282/* Statistics per DMA channel */
283struct grspw_dma_stats {
284        /* IRQ Statistics */
285        int irq_cnt;            /* Number of DMA IRQs generated by channel */
286
287        /* Descriptor Statistics */
288        int tx_pkts;            /* Number of Transmitted packets */
289        int tx_err_link;        /* Number of Transmitted packets with Link Error*/
290        int rx_pkts;            /* Number of Received packets */
291        int rx_err_trunk;       /* Number of Received Truncated packets */
292        int rx_err_endpkt;      /* Number of Received packets with bad ending */
293
294        /* Diagnostics to help developers sizing their number buffers to avoid
295         * out-of-buffers or other phenomenons.
296         */
297        int send_cnt_min;       /* Minimum number of packets in TX SEND Q */
298        int send_cnt_max;       /* Maximum number of packets in TX SEND Q */
299        int tx_sched_cnt_min;   /* Minimum number of packets in TX SCHED Q */
300        int tx_sched_cnt_max;   /* Maximum number of packets in TX SCHED Q */
301        int sent_cnt_max;       /* Maximum number of packets in TX SENT Q */
302        int tx_work_cnt;        /* Times the work thread processed TX BDs */
303        int tx_work_enabled;    /* No. RX BDs enabled by work thread */
304
305        int ready_cnt_min;      /* Minimum number of packets in RX READY Q */
306        int ready_cnt_max;      /* Maximum number of packets in RX READY Q */
307        int rx_sched_cnt_min;   /* Minimum number of packets in RX SCHED Q */
308        int rx_sched_cnt_max;   /* Maximum number of packets in RX SCHED Q */
309        int recv_cnt_max;       /* Maximum number of packets in RX RECV Q */
310        int rx_work_cnt;        /* Times the work thread processed RX BDs */
311        int rx_work_enabled;    /* No. RX BDs enabled by work thread */
312};
313
314extern void grspw_initialize_user(
315        /* Callback every time a GRSPW device is found. Args: DeviceIndex */
316        void *(*devfound)(int),
317        /* Callback every time a GRSPW device is removed. Args:
318         * int   = DeviceIndex
319         * void* = Return Value from devfound()
320         */
321        void (*devremove)(int,void*)
322        );
323extern int grspw_dev_count(void);
324extern void *grspw_open(int dev_no);
325extern int grspw_close(void *d);
326extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw);
327extern void grspw_stats_read(void *d, struct grspw_core_stats *sts);
328extern void grspw_stats_clr(void *d);
329
330/* Set and Read current node address configuration. The dma_nacfg[N] field
331 * represents the configuration for DMA Channel N.
332 *
333 * Set cfg->promiscous to -1 in order to only read current configuration.
334 */
335extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg);
336
337/*** Link Control interface ***/
338/* Read Link State */
339extern spw_link_state_t grspw_link_state(void *d);
340/* options [in/out]: set to -1 to only read current config
341 *
342 * CLKDIV register contain:
343 *  bits 7..0  : Clock Div RUN (only run-state)
344 *  bits 15..8 : Clock Div During Startup (all link states except run-state)
345 */
346extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv);
347/* Read the current value of the status register */
348extern unsigned int grspw_link_status(void *d);
349/* Clear bits in the status register */
350extern void grspw_link_status_clr(void *d, unsigned int clearmask);
351
352/*** Time Code Interface ***/
353/* Generate Tick-In (increment Time Counter, Send Time Code) */
354extern void grspw_tc_tx(void *d);
355/* Control Timcode settings of core */
356extern void grspw_tc_ctrl(void *d, int *options);
357/* Assign ISR Function to TimeCode RX IRQ */
358extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data);
359/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value
360 * TCTRL   = bits 7 and 6
361 * TIMECNT = bits 5 to 0
362 */
363extern void grspw_tc_time(void *d, int *time);
364
365/*** Interrupt-code Interface ***/
366struct spwpkt_ic_config {
367        unsigned int tomask;
368        unsigned int aamask;
369        unsigned int scaler;
370        unsigned int isr_reload;
371        unsigned int ack_reload;
372};
373/* Function Interrupt-Code ISR callback prototype. Called when respective
374 * interrupt handling option has been enabled by grspw_ic_ctrl(), the
375 * arguments rxirq, rxack and intto are read from the registers of the
376 * GRSPW core read by the GRSPW ISR, they are individually valid only when
377 * repective handling been turned on.
378 *
379 * data    - Custom data provided by user
380 * rxirq   - Interrupt-Code Recevie register of the GRSPW core read by ISR
381 *           (only defined if IQ bit enabled through grspw_ic_ctrl())
382 * rxack   - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR
383 *           (only defined if AQ bit enabled through grspw_ic_ctrl())
384 * intto   - Interrupt Tick-out Recevie register of the GRSPW core read by ISR
385 *           (only defined if TQ bit enabled through grspw_ic_ctrl())
386 */
387typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq,
388                                unsigned int rxack, unsigned int intto);
389/* Control Interrupt-code settings of core
390 * Write if 'options' not pointing to -1, always read current value
391 */
392extern void grspw_ic_ctrl(void *d, unsigned int *options);
393/* Write (rw&1 == 1) configuration parameters to registers and/or,
394 * Read  (rw&2 == 1) configuration parameters from registers, in that sequence.
395 */
396extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg);
397/* Read or Write Interrupt-code status registers.
398 * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write.
399 * If *ptr is NULL no operation.
400 */
401extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack,
402                        unsigned int *intto);
403/* Generate Tick-In for the given Interrupt-code
404 * Returns zero on success and non-zero on failure
405 *
406 * Interrupt code bits (ic):
407 * Bit 5 - ACK if 1
408 * Bits 4-0 Interrupt-code number
409 */
410extern int grspw_ic_tickin(void *d, int ic);
411/* Assign handler function to Interrupt-code timeout IRQ */
412extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data);
413
414/*** RMAP Control Interface ***/
415/* Set (not -1) and/or read RMAP options. */
416extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey);
417extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc);
418
419/*** SpW Port Control Interface ***/
420
421/* Select port, if
422 * -1=The current selected port is returned
423 * 0=Port 0
424 * 1=Port 1
425 * Other positive values=Both Port0 and Port1
426 */
427extern int grspw_port_ctrl(void *d, int *port);
428/* Returns Number ports available in hardware */
429extern int grspw_port_count(void *d);
430/* Returns the current active port */
431extern int grspw_port_active(void *d);
432
433/*** DMA Interface ***/
434extern void *grspw_dma_open(void *d, int chan_no);
435extern int grspw_dma_close(void *c);
436
437extern int grspw_dma_start(void *c);
438extern void grspw_dma_stop(void *c);
439
440/* Schedule List of packets for transmission at some point in
441 * future.
442 *
443 * 1. Move transmitted packets to SENT List (SCHED->SENT)
444 * 2. Add the requested packets to the SEND List (USER->SEND)
445 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
446 *
447 * Call this function with pkts=NULL to just do step 1 and 3. This may be
448 * required in Polling-mode.
449 *
450 * The above steps 1 and 3 may be skipped by setting 'opts':
451 *  bit0 = 1: Skip Step 1.
452 *  bit1 = 1: Skip Step 3.
453 * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then
454 * the work queue will be totaly responsible for handling descriptors.
455 *
456 * The fastest solution in retreiving sent TX packets and sending new frames
457 * is to call:
458 *  A. grspw_dma_tx_reclaim(opts=0)
459 *  B. grspw_dma_tx_send(opts=1)
460 *
461 * NOTE: the TXPKT_FLAG_TX flag must not be set.
462 *
463 * Return Code
464 *  -1   Error
465 *  0    Successfully added pkts to send/sched list
466 *  1    DMA stopped. No operation.
467 */
468extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count);
469
470/* Reclaim TX packet buffers that has previously been scheduled for transmission
471 * with grspw_dma_tx_send().
472 *
473 * 1. Move transmitted packets to SENT List (SCHED->SENT)
474 * 2. Move all SENT List to pkts list (SENT->USER)
475 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
476 *
477 * The above steps 1 may be skipped by setting 'opts':
478 *  bit0 = 1: Skip Step 1.
479 *  bit1 = 1: Skip Step 3.
480 *
481 * The fastest solution in retreiving sent TX packets and sending new frames
482 * is to call:
483 *  A. grspw_dma_tx_reclaim(opts=2) (Skip step 3)
484 *  B. grspw_dma_tx_send(opts=1) (Skip step 1)
485 *
486 * Return Code
487 *  -1   Error
488 *  0    Successful. pkts list filled with all packets from sent list
489 *  1    Same as 0, but indicates that DMA stopped
490 */
491extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count);
492
493/* Get current number of Packets in respective TX Queue. */
494extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *hw);
495
496#define GRSPW_OP_AND 0
497#define GRSPW_OP_OR 1
498/* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q,
499 * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition
500 * is met.
501 * If a link error occurs and the Stop on Link error is defined, this function
502 * will also return to caller.
503 * The timeout argument is used to return after timeout ticks, regardless of
504 * the other conditions. If timeout is zero, the function will wait forever
505 * until the condition is satisfied.
506 *
507 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
508 *       checked, this may hang infinitely unless a timeout has been specified
509 *
510 * Return Code
511 *  -1   Error
512 *  0    Returing to caller because specified conditions are now fullfilled
513 *  1    DMA stopped
514 *  2    Timeout, conditions are not met
515 *  3    Another task is already waiting. Service is Busy.
516 */
517extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout);
518
519/* Get received RX packet buffers that has previously been scheduled for
520 * reception with grspw_dma_rx_prepare().
521 *
522 * 1. Move Scheduled packets to RECV List (SCHED->RECV)
523 * 2. Move all RECV packet to the callers list (RECV->USER)
524 * 3. Schedule as many free packet buffers as possible (READY->SCHED)
525 *
526 * The above steps 1 may be skipped by setting 'opts':
527 *  bit0 = 1: Skip Step 1.
528 *  bit1 = 1: Skip Step 3.
529 *
530 * The fastest solution in retreiving received RX packets and preparing new
531 * packet buffers for future receive, is to call:
532 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
533 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
534 *
535 * Return Code
536 *  -1   Error
537 *  0    Successfully filled pkts list with packets from recv list.
538 *  1    DMA stopped
539 */
540extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count);
541
542/* Add more RX packet buffers for future for reception. The received packets
543 * can later be read out with grspw_dma_rx_recv().
544 *
545 * 1. Move Received packets to RECV List (SCHED->RECV)
546 * 2. Add the "free/ready" packet buffers to the READY List (USER->READY)
547 * 3. Schedule as many packets as possible (READY->SCHED)
548 *
549 * The above steps 1 may be skipped by setting 'opts':
550 *  bit0 = 1: Skip Step 1.
551 *  bit1 = 1: Skip Step 3.
552 *
553 * The fastest solution in retreiving received RX packets and preparing new
554 * packet buffers for future receive, is to call:
555 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
556 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
557 *
558 * Return Code
559 *  -1   Error
560 *  0    Successfully added packet buffers from pkt list into the ready queue
561 *  1    DMA stopped
562 */
563extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count);
564
565/* Get current number of Packets in respective RX Queue. */
566extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int *hw);
567
568/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR),
569 * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q,
570 * condition is met.
571 * If a link error occurs and the Stop on Link error is defined, this function
572 * will also return to caller, however with an error.
573 * The timeout argument is used to return after timeout ticks, regardless of
574 * the other conditions. If timeout is zero, the function will wait forever
575 * until the condition is satisfied.
576 *
577 * NOTE: if IRQ of RX descriptors are not enabled conditions are never
578 *       checked, this may hang infinitely unless a timeout has been specified
579 *
580 * Return Code
581 *  -1   Error
582 *  0    Returing to caller because specified conditions are now fullfilled
583 *  1    DMA stopped
584 *  2    Timeout, conditions are not met
585 *  3    Another task is already waiting. Service is Busy.
586 */
587extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout);
588
589extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg);
590extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg);
591
592extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts);
593extern void grspw_dma_stats_clr(void *c);
594
595/* Register GRSPW packet driver to Driver Manager */
596void grspw2_register_drv (void);
597
598/*** GRSPW SpaceWire Packet List Handling Routines ***/
599
600static inline void grspw_list_clr(struct grspw_list *list)
601{
602        list->head = NULL;
603        list->tail = NULL;
604}
605
606static inline int grspw_list_is_empty(struct grspw_list *list)
607{
608        return (list->head == NULL);
609}
610
611/* Return Number of entries in list */
612static inline int grspw_list_cnt(struct grspw_list *list)
613{
614        struct grspw_pkt *lastpkt = NULL, *pkt = list->head;
615        int cnt = 0;
616        while ( pkt ) {
617                cnt++;
618                lastpkt = pkt;
619                pkt = pkt->next;
620        }
621        if ( lastpkt && (list->tail != lastpkt) )
622                return -1;
623        return cnt;
624}
625
626static inline void
627grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt)
628{
629        pkt->next = NULL;
630        if ( list->tail == NULL ) {
631                list->head = pkt;
632        } else {
633                list->tail->next = pkt;
634        }
635        list->tail = pkt;
636}
637
638static inline void 
639grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt)
640{
641        pkt->next = list->head;
642        if ( list->head == NULL ) {
643                list->tail = pkt;
644        }
645        list->head = pkt;
646}
647
648static inline void
649grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist)
650{
651        if (grspw_list_is_empty(alist)) {
652                return;
653        }
654        alist->tail->next = NULL;
655        if ( list->tail == NULL ) {
656                list->head = alist->head;
657        } else {
658                list->tail->next = alist->head;
659        }
660        list->tail = alist->tail;
661}
662
663static inline void
664grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist)
665{
666        if (grspw_list_is_empty(alist)) {
667                return;
668        }
669        if ( list->head == NULL ) {
670                list->tail = alist->tail;
671                alist->tail->next = NULL;
672        } else {
673                alist->tail->next = list->head;
674        }
675        list->head = alist->head;
676}
677
678/* Remove dlist (delete-list) from head of list */
679static inline void
680grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist)
681{
682        if (grspw_list_is_empty(dlist)) {
683                return;
684        }
685        list->head = dlist->tail->next;
686        if ( list->head == NULL ) {
687                list->tail = NULL;
688        }
689        dlist->tail->next = NULL;
690}
691
692/* Take A number of entries from head of list 'list' and put the entires
693 * to rlist (result list).
694 */
695static inline int
696grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max)
697{
698        int cnt;
699        struct grspw_pkt *pkt, *last;
700
701        pkt = list->head;
702
703        if ( (max < 1) || (pkt == NULL) ) {
704                grspw_list_clr(rlist);
705                return 0;
706        }
707
708        cnt = 0;
709        rlist->head = pkt;
710        last = pkt;
711        while ((cnt < max) && pkt) {
712                last = pkt;
713                pkt = pkt->next;
714                cnt++;
715        }
716        rlist->tail = last;
717        grspw_list_remove_head_list(list, rlist);
718        return cnt;
719}
720
721#endif
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