1 | /* |
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2 | * GRSPW/GRSPW2 SpaceWire Kernel Library Interface |
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3 | * |
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4 | * COPYRIGHT (c) 2011 |
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5 | * Cobham Gaisler AB |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.org/license/LICENSE. |
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10 | */ |
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11 | |
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12 | #ifndef __GRSPW_PKT_H__ |
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13 | #define __GRSPW_PKT_H__ |
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14 | |
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15 | struct grspw_pkt; |
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16 | |
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17 | /* Maximum number of GRSPW devices supported by driver */ |
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18 | #define GRSPW_MAX 32 |
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19 | |
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20 | /* Weak overridable variable the user can use to define the worker-task |
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21 | * priority (0..255) or to disable (-1) the creation of the worker-task |
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22 | * and the message queue to save space */ |
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23 | extern int grspw_work_task_priority; |
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24 | |
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25 | #ifndef GRSPW_PKT_FLAGS |
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26 | #define GRSPW_PKT_FLAGS |
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27 | /*** TX Packet flags ***/ |
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28 | |
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29 | /* Enable IRQ generation */ |
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30 | #define TXPKT_FLAG_IE 0x0040 |
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31 | |
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32 | /* Enable Header CRC generation (if CRC is available in HW) |
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33 | * Header CRC will be appended (one byte at end of header) |
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34 | */ |
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35 | #define TXPKT_FLAG_HCRC 0x0100 |
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36 | |
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37 | /* Enable Data CRC generation (if CRC is available in HW) |
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38 | * Data CRC will be appended (one byte at end of packet) |
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39 | */ |
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40 | #define TXPKT_FLAG_DCRC 0x0200 |
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41 | |
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42 | /* Control how many bytes the beginning of the Header |
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43 | * the CRC should not be calculated for */ |
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44 | #define TXPKT_FLAG_NOCRC_MASK 0x0000000f |
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45 | #define TXPKT_FLAG_NOCRC_LEN0 0x00000000 |
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46 | #define TXPKT_FLAG_NOCRC_LEN1 0x00000001 |
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47 | #define TXPKT_FLAG_NOCRC_LEN2 0x00000002 |
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48 | #define TXPKT_FLAG_NOCRC_LEN3 0x00000003 |
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49 | #define TXPKT_FLAG_NOCRC_LEN4 0x00000004 |
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50 | #define TXPKT_FLAG_NOCRC_LEN5 0x00000005 |
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51 | #define TXPKT_FLAG_NOCRC_LEN6 0x00000006 |
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52 | #define TXPKT_FLAG_NOCRC_LEN7 0x00000007 |
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53 | #define TXPKT_FLAG_NOCRC_LEN8 0x00000008 |
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54 | #define TXPKT_FLAG_NOCRC_LEN9 0x00000009 |
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55 | #define TXPKT_FLAG_NOCRC_LENa 0x0000000a |
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56 | #define TXPKT_FLAG_NOCRC_LENb 0x0000000b |
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57 | #define TXPKT_FLAG_NOCRC_LENc 0x0000000c |
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58 | #define TXPKT_FLAG_NOCRC_LENd 0x0000000d |
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59 | #define TXPKT_FLAG_NOCRC_LENe 0x0000000e |
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60 | #define TXPKT_FLAG_NOCRC_LENf 0x0000000f |
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61 | |
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62 | #define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \ |
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63 | TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC) |
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64 | |
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65 | /* Marks if packet was transmitted or not */ |
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66 | #define TXPKT_FLAG_TX 0x4000 |
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67 | |
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68 | /* Link Error */ |
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69 | #define TXPKT_FLAG_LINKERR 0x8000 |
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70 | |
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71 | #define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR) |
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72 | |
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73 | /*** RX Packet Flags ***/ |
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74 | |
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75 | /* Enable IRQ generation */ |
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76 | #define RXPKT_FLAG_IE 0x0010 |
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77 | |
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78 | #define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE) |
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79 | |
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80 | /* Packet was truncated */ |
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81 | #define RXPKT_FLAG_TRUNK 0x0800 |
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82 | /* Data CRC error (only valid if RMAP CRC is enabled) */ |
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83 | #define RXPKT_FLAG_DCRC 0x0400 |
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84 | /* Header CRC error (only valid if RMAP CRC is enabled) */ |
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85 | #define RXPKT_FLAG_HCRC 0x0200 |
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86 | /* Error in End-of-Packet */ |
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87 | #define RXPKT_FLAG_EEOP 0x0100 |
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88 | /* Marks if packet was recevied or not */ |
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89 | #define RXPKT_FLAG_RX 0x8000 |
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90 | |
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91 | #define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \ |
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92 | RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP) |
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93 | |
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94 | /*** General packet flag options ***/ |
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95 | |
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96 | /* Translate Hdr and/or Payload address */ |
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97 | #define PKT_FLAG_TR_DATA 0x1000 |
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98 | #define PKT_FLAG_TR_HDR 0x2000 |
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99 | /* All General options */ |
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100 | #define PKT_FLAG_MASK 0x3000 |
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101 | |
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102 | #endif |
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103 | /* GRSPW RX/TX Packet structure. |
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104 | * |
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105 | * - For RX the 'hdr' and 'hlen' fields are not used, they are not written |
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106 | * by driver. |
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107 | * |
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108 | * - The 'pkt_id' field is untouched by driver, it is intended for packet |
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109 | * numbering or user-custom data. |
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110 | * |
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111 | * - The last packet in a list must have 'next' set to NULL. |
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112 | * |
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113 | * - data and hdr pointers are written without modification to hardware, |
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114 | * this means that caller must do address translation to hardware |
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115 | * address itself. |
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116 | * |
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117 | * - the 'flags' field are interpreted differently depending on transfer |
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118 | * type (RX/TX). See XXPKT_FLAG_* options above. |
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119 | */ |
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120 | struct grspw_pkt { |
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121 | struct grspw_pkt *next; /* Next packet in list. NULL if last packet */ |
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122 | unsigned int pkt_id; /* User assigned ID (not touched by driver) */ |
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123 | unsigned short flags; /* RX/TX Options and status */ |
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124 | unsigned char reserved; /* Reserved, must be zero */ |
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125 | unsigned char hlen; /* Length of Header Buffer (only TX) */ |
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126 | unsigned int dlen; /* Length of Data Buffer */ |
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127 | void *data; /* 4-byte or byte aligned depends on HW */ |
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128 | void *hdr; /* 4-byte or byte aligned depends on HW (only TX) */ |
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129 | }; |
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130 | |
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131 | /* GRSPW SpaceWire Packet List */ |
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132 | struct grspw_list { |
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133 | struct grspw_pkt *head; |
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134 | struct grspw_pkt *tail; |
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135 | }; |
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136 | |
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137 | /* SpaceWire Link State */ |
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138 | typedef enum { |
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139 | SPW_LS_ERRRST = 0, |
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140 | SPW_LS_ERRWAIT = 1, |
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141 | SPW_LS_READY = 2, |
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142 | SPW_LS_CONNECTING = 3, |
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143 | SPW_LS_STARTED = 4, |
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144 | SPW_LS_RUN = 5 |
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145 | } spw_link_state_t; |
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146 | |
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147 | /* Address Configuration */ |
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148 | struct grspw_addr_config { |
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149 | /* Ignore address field and put all received packets to first |
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150 | * DMA channel. |
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151 | */ |
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152 | int promiscuous; |
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153 | |
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154 | /* Default Node Address and Mask */ |
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155 | unsigned char def_addr; |
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156 | unsigned char def_mask; |
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157 | /* DMA Channel custom Node Address and Mask */ |
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158 | struct { |
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159 | char node_en; /* Enable Separate Addr */ |
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160 | unsigned char node_addr; /* Node address */ |
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161 | unsigned char node_mask; /* Node address mask */ |
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162 | } dma_nacfg[4]; |
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163 | }; |
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164 | |
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165 | /* Hardware Support in GRSPW Core */ |
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166 | struct grspw_hw_sup { |
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167 | char rmap; /* If RMAP in HW is available */ |
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168 | char rmap_crc; /* If RMAP CRC is available */ |
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169 | char rx_unalign; /* RX unaligned (byte boundary) access allowed*/ |
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170 | char nports; /* Number of Ports (1 or 2) */ |
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171 | char ndma_chans; /* Number of DMA Channels (1..4) */ |
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172 | char strip_adr; /* Hardware can strip ADR from packet data */ |
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173 | char strip_pid; /* Hardware can strip PID from packet data */ |
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174 | int hw_version; /* GRSPW Hardware Version */ |
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175 | char reserved[2]; |
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176 | char irq; /* SpW Distributed Interrupt available if 1 */ |
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177 | char irq_num; /* Number of interrupts that can be generated */ |
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178 | char itmr_width; /* SpW Intr. ISR timers bit width. 0=no timer */ |
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179 | }; |
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180 | |
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181 | struct grspw_core_stats { |
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182 | int irq_cnt; |
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183 | int err_credit; |
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184 | int err_eeop; |
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185 | int err_addr; |
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186 | int err_parity; |
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187 | int err_disconnect; |
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188 | int err_escape; |
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189 | int err_wsync; /* only in GRSPW1 */ |
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190 | }; |
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191 | |
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192 | /* grspw_link_ctrl() options */ |
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193 | #define LINKOPTS_ENABLE 0x0000 |
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194 | #define LINKOPTS_DISABLE 0x0001 |
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195 | #define LINKOPTS_START 0x0002 |
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196 | #define LINKOPTS_AUTOSTART 0x0004 |
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197 | #define LINKOPTS_DIS_ONERR 0x0008 /* Disable DMA transmitter on link error |
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198 | * Controls LE bit in DMACTRL register. |
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199 | */ |
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200 | #define LINKOPTS_DIS_ON_CE 0x0020000/* Disable Link on Credit error */ |
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201 | #define LINKOPTS_DIS_ON_ER 0x0040000/* Disable Link on Escape error */ |
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202 | #define LINKOPTS_DIS_ON_DE 0x0080000/* Disable Link on Disconnect error */ |
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203 | #define LINKOPTS_DIS_ON_PE 0x0100000/* Disable Link on Parity error */ |
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204 | #define LINKOPTS_DIS_ON_WE 0x0400000/* Disable Link on write synchonization |
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205 | * error (GRSPW1 only) |
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206 | */ |
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207 | #define LINKOPTS_DIS_ON_EE 0x1000000/* Disable Link on Early EOP/EEP error*/ |
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208 | |
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209 | /*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */ |
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210 | #define LINKOPTS_EIRQ 0x0200 /* Enable Error Link IRQ */ |
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211 | |
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212 | #define LINKOPTS_MASK 0x15e020f/* All above options */ |
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213 | #define LINKOPTS_MASK_DIS_ON 0x15e0000/* All disable link on error options |
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214 | * On a certain error the link disable |
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215 | * bit will be written and the work |
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216 | * task will call dma_stop() for all |
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217 | * channels. |
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218 | */ |
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219 | |
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220 | #define LINKSTS_CE 0x002 /* Credit error */ |
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221 | #define LINKSTS_ER 0x004 /* Escape error */ |
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222 | #define LINKSTS_DE 0x008 /* Disconnect error */ |
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223 | #define LINKSTS_PE 0x010 /* Parity error */ |
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224 | #define LINKSTS_WE 0x040 /* Write synchonization error (GRSPW1 only) */ |
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225 | #define LINKSTS_IA 0x080 /* Invalid address */ |
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226 | #define LINKSTS_EE 0x100 /* Early EOP/EEP */ |
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227 | #define LINKSTS_MASK 0x1de |
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228 | |
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229 | /* grspw_tc_ctrl() options */ |
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230 | #define TCOPTS_EN_RXIRQ 0x0001 /* Tick-Out IRQ */ |
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231 | #define TCOPTS_EN_TX 0x0004 |
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232 | #define TCOPTS_EN_RX 0x0008 |
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233 | |
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234 | /* grspw_ic_ctrl() options: |
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235 | * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines |
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236 | */ |
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237 | #define ICOPTS_INTNUM (0x1f << 27) |
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238 | #define ICOPTS_EN_SPWIRQ_ON_EE (1 << 24) |
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239 | #define ICOPTS_EN_SPWIRQ_ON_IA (1 << 23) |
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240 | #define ICOPTS_EN_PRIO (1 << 22) |
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241 | #define ICOPTS_EN_TIMEOUTIRQ (1 << 20) |
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242 | #define ICOPTS_EN_ACKIRQ (1 << 19) |
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243 | #define ICOPTS_EN_TICKOUTIRQ (1 << 18) |
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244 | #define ICOPTS_EN_RX (1 << 17) |
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245 | #define ICOPTS_EN_TX (1 << 16) |
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246 | #define ICOPTS_BASEIRQ (0x1f << 8) |
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247 | #define ICOPTS_EN_FLAGFILTER (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */ |
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248 | |
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249 | /* grspw_ic_rlisr() and grspw_ic_rlintack() */ |
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250 | #define ICRELOAD_EN (1 << 31) |
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251 | #define ICRELOAD_MASK 0x7fffffff |
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252 | |
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253 | /* grspw_rmap_ctrl() options */ |
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254 | #define RMAPOPTS_EN_RMAP 0x0001 |
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255 | #define RMAPOPTS_EN_BUF 0x0002 |
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256 | |
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257 | /* grspw_dma_config.flags options */ |
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258 | #define DMAFLAG_NO_SPILL 0x0001 /* See HW doc DMA-CTRL NS bit */ |
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259 | #define DMAFLAG_RESV1 0x0002 /* HAS NO EFFECT */ |
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260 | #define DMAFLAG_STRIP_ADR 0x0004 /* See HW doc DMA-CTRL SA bit */ |
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261 | #define DMAFLAG_STRIP_PID 0x0008 /* See HW doc DMA-CTRL SP bit */ |
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262 | #define DMAFLAG_RESV2 0x0010 /* HAS NO EFFECT */ |
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263 | #define DMAFLAG_MASK (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID) |
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264 | |
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265 | struct grspw_dma_config { |
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266 | int flags; /* DMA config flags, see DMAFLAG_* options */ |
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267 | int rxmaxlen; /* RX Max Packet Length */ |
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268 | int rx_irq_en_cnt; /* Enable RX IRQ every cnt descriptors */ |
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269 | int tx_irq_en_cnt; /* Enable TX IRQ every cnt descriptors */ |
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270 | }; |
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271 | |
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272 | /* Statistics per DMA channel */ |
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273 | struct grspw_dma_stats { |
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274 | /* IRQ Statistics */ |
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275 | int irq_cnt; /* Number of DMA IRQs generated by channel */ |
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276 | |
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277 | /* Descriptor Statistics */ |
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278 | int tx_pkts; /* Number of Transmitted packets */ |
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279 | int tx_err_link; /* Number of Transmitted packets with Link Error*/ |
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280 | int rx_pkts; /* Number of Received packets */ |
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281 | int rx_err_trunk; /* Number of Received Truncated packets */ |
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282 | int rx_err_endpkt; /* Number of Received packets with bad ending */ |
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283 | |
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284 | /* Diagnostics to help developers sizing their number buffers to avoid |
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285 | * out-of-buffers or other phenomenons. |
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286 | */ |
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287 | int send_cnt_min; /* Minimum number of packets in TX SEND Q */ |
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288 | int send_cnt_max; /* Maximum number of packets in TX SEND Q */ |
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289 | int tx_sched_cnt_min; /* Minimum number of packets in TX SCHED Q */ |
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290 | int tx_sched_cnt_max; /* Maximum number of packets in TX SCHED Q */ |
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291 | int sent_cnt_max; /* Maximum number of packets in TX SENT Q */ |
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292 | int tx_work_cnt; /* Times the work thread processed TX BDs */ |
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293 | int tx_work_enabled; /* No. RX BDs enabled by work thread */ |
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294 | |
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295 | int ready_cnt_min; /* Minimum number of packets in RX READY Q */ |
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296 | int ready_cnt_max; /* Maximum number of packets in RX READY Q */ |
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297 | int rx_sched_cnt_min; /* Minimum number of packets in RX SCHED Q */ |
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298 | int rx_sched_cnt_max; /* Maximum number of packets in RX SCHED Q */ |
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299 | int recv_cnt_max; /* Maximum number of packets in RX RECV Q */ |
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300 | int rx_work_cnt; /* Times the work thread processed RX BDs */ |
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301 | int rx_work_enabled; /* No. RX BDs enabled by work thread */ |
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302 | }; |
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303 | |
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304 | extern void grspw_initialize_user( |
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305 | /* Callback every time a GRSPW device is found. Args: DeviceIndex */ |
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306 | void *(*devfound)(int), |
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307 | /* Callback every time a GRSPW device is removed. Args: |
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308 | * int = DeviceIndex |
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309 | * void* = Return Value from devfound() |
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310 | */ |
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311 | void (*devremove)(int,void*) |
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312 | ); |
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313 | extern int grspw_dev_count(void); |
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314 | extern void *grspw_open(int dev_no); |
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315 | extern int grspw_close(void *d); |
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316 | extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw); |
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317 | extern void grspw_stats_read(void *d, struct grspw_core_stats *sts); |
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318 | extern void grspw_stats_clr(void *d); |
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319 | |
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320 | /* Set and Read current node address configuration. The dma_nacfg[N] field |
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321 | * represents the configuration for DMA Channel N. |
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322 | * |
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323 | * Set cfg->promiscous to -1 in order to only read current configuration. |
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324 | */ |
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325 | extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg); |
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326 | |
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327 | /*** Link Control interface ***/ |
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328 | /* Read Link State */ |
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329 | extern spw_link_state_t grspw_link_state(void *d); |
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330 | /* options [in/out]: set to -1 to only read current config |
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331 | * |
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332 | * CLKDIV register contain: |
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333 | * bits 7..0 : Clock Div RUN (only run-state) |
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334 | * bits 15..8 : Clock Div During Startup (all link states except run-state) |
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335 | */ |
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336 | extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv); |
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337 | /* Read the current value of the status register */ |
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338 | extern unsigned int grspw_link_status(void *d); |
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339 | /* Clear bits in the status register */ |
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340 | extern void grspw_link_status_clr(void *d, unsigned int clearmask); |
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341 | |
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342 | /*** Time Code Interface ***/ |
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343 | /* Generate Tick-In (increment Time Counter, Send Time Code) */ |
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344 | extern void grspw_tc_tx(void *d); |
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345 | /* Control Timcode settings of core */ |
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346 | extern void grspw_tc_ctrl(void *d, int *options); |
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347 | /* Assign ISR Function to TimeCode RX IRQ */ |
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348 | extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data); |
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349 | /* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value |
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350 | * TCTRL = bits 7 and 6 |
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351 | * TIMECNT = bits 5 to 0 |
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352 | */ |
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353 | extern void grspw_tc_time(void *d, int *time); |
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354 | |
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355 | /*** Interrupt-code Interface ***/ |
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356 | struct spwpkt_ic_config { |
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357 | unsigned int tomask; |
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358 | unsigned int aamask; |
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359 | unsigned int scaler; |
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360 | unsigned int isr_reload; |
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361 | unsigned int ack_reload; |
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362 | }; |
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363 | /* Function Interrupt-Code ISR callback prototype. Called when respective |
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364 | * interrupt handling option has been enabled by grspw_ic_ctrl(), the |
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365 | * arguments rxirq, rxack and intto are read from the registers of the |
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366 | * GRSPW core read by the GRSPW ISR, they are individually valid only when |
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367 | * repective handling been turned on. |
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368 | * |
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369 | * data - Custom data provided by user |
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370 | * rxirq - Interrupt-Code Recevie register of the GRSPW core read by ISR |
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371 | * (only defined if IQ bit enabled through grspw_ic_ctrl()) |
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372 | * rxack - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR |
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373 | * (only defined if AQ bit enabled through grspw_ic_ctrl()) |
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374 | * intto - Interrupt Tick-out Recevie register of the GRSPW core read by ISR |
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375 | * (only defined if TQ bit enabled through grspw_ic_ctrl()) |
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376 | */ |
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377 | typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq, |
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378 | unsigned int rxack, unsigned int intto); |
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379 | /* Control Interrupt-code settings of core |
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380 | * Write if 'options' not pointing to -1, always read current value |
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381 | */ |
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382 | extern void grspw_ic_ctrl(void *d, unsigned int *options); |
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383 | /* Write (rw&1 == 1) configuration parameters to registers and/or, |
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384 | * Read (rw&2 == 1) configuration parameters from registers, in that sequence. |
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385 | */ |
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386 | extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg); |
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387 | /* Read or Write Interrupt-code status registers. |
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388 | * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write. |
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389 | * If *ptr is NULL no operation. |
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390 | */ |
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391 | extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack, |
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392 | unsigned int *intto); |
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393 | /* Generate Tick-In for the given Interrupt-code |
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394 | * Returns zero on success and non-zero on failure |
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395 | * |
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396 | * Interrupt code bits (ic): |
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397 | * Bit 5 - ACK if 1 |
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398 | * Bits 4-0 Interrupt-code number |
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399 | */ |
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400 | extern int grspw_ic_tickin(void *d, int ic); |
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401 | /* Assign handler function to Interrupt-code timeout IRQ */ |
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402 | extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data); |
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403 | |
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404 | /*** RMAP Control Interface ***/ |
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405 | /* Set (not -1) and/or read RMAP options. */ |
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406 | extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey); |
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407 | extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc); |
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408 | |
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409 | /*** SpW Port Control Interface ***/ |
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410 | |
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411 | /* Select port, if |
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412 | * -1=The current selected port is returned |
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413 | * 0=Port 0 |
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414 | * 1=Port 1 |
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415 | * Other positive values=Both Port0 and Port1 |
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416 | */ |
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417 | extern int grspw_port_ctrl(void *d, int *port); |
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418 | /* Returns Number ports available in hardware */ |
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419 | extern int grspw_port_count(void *d); |
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420 | /* Returns the current active port */ |
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421 | extern int grspw_port_active(void *d); |
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422 | |
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423 | /*** DMA Interface ***/ |
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424 | extern void *grspw_dma_open(void *d, int chan_no); |
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425 | extern int grspw_dma_close(void *c); |
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426 | |
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427 | extern int grspw_dma_start(void *c); |
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428 | extern void grspw_dma_stop(void *c); |
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429 | |
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430 | /* Schedule List of packets for transmission at some point in |
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431 | * future. |
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432 | * |
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433 | * 1. Move transmitted packets to SENT List (SCHED->SENT) |
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434 | * 2. Add the requested packets to the SEND List (USER->SEND) |
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435 | * 3. Schedule as many packets as possible for transmission (SEND->SCHED) |
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436 | * |
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437 | * Call this function with pkts=NULL to just do step 1 and 3. This may be |
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438 | * required in Polling-mode. |
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439 | * |
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440 | * The above steps 1 and 3 may be skipped by setting 'opts': |
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441 | * bit0 = 1: Skip Step 1. |
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442 | * bit1 = 1: Skip Step 3. |
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443 | * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then |
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444 | * the work queue will be totaly responsible for handling descriptors. |
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445 | * |
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446 | * The fastest solution in retreiving sent TX packets and sending new frames |
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447 | * is to call: |
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448 | * A. grspw_dma_tx_reclaim(opts=0) |
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449 | * B. grspw_dma_tx_send(opts=1) |
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450 | * |
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451 | * NOTE: the TXPKT_FLAG_TX flag must not be set. |
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452 | * |
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453 | * Return Code |
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454 | * -1 Error |
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455 | * 0 Successfully added pkts to send/sched list |
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456 | * 1 DMA stopped. No operation. |
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457 | */ |
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458 | extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count); |
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459 | |
---|
460 | /* Reclaim TX packet buffers that has previously been scheduled for transmission |
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461 | * with grspw_dma_tx_send(). |
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462 | * |
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463 | * 1. Move transmitted packets to SENT List (SCHED->SENT) |
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464 | * 2. Move all SENT List to pkts list (SENT->USER) |
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465 | * 3. Schedule as many packets as possible for transmission (SEND->SCHED) |
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466 | * |
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467 | * The above steps 1 may be skipped by setting 'opts': |
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468 | * bit0 = 1: Skip Step 1. |
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469 | * bit1 = 1: Skip Step 3. |
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470 | * |
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471 | * The fastest solution in retreiving sent TX packets and sending new frames |
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472 | * is to call: |
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473 | * A. grspw_dma_tx_reclaim(opts=2) (Skip step 3) |
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474 | * B. grspw_dma_tx_send(opts=1) (Skip step 1) |
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475 | * |
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476 | * Return Code |
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477 | * -1 Error |
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478 | * 0 Successful. pkts list filled with all packets from sent list |
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479 | * 1 Same as 0, but indicates that DMA stopped |
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480 | */ |
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481 | extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count); |
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482 | |
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483 | /* Get current number of Packets in respective TX Queue. */ |
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484 | extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent); |
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485 | |
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486 | #define GRSPW_OP_AND 0 |
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487 | #define GRSPW_OP_OR 1 |
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488 | /* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q, |
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489 | * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition |
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490 | * is met. |
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491 | * If a link error occurs and the Stop on Link error is defined, this function |
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492 | * will also return to caller. |
---|
493 | * The timeout argument is used to return after timeout ticks, regardless of |
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494 | * the other conditions. If timeout is zero, the function will wait forever |
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495 | * until the condition is satisfied. |
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496 | * |
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497 | * NOTE: if IRQ of TX descriptors are not enabled conditions are never |
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498 | * checked, this may hang infinitely unless a timeout has been specified |
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499 | * |
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500 | * Return Code |
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501 | * -1 Error |
---|
502 | * 0 Returing to caller because specified conditions are now fullfilled |
---|
503 | * 1 DMA stopped |
---|
504 | * 2 Timeout, conditions are not met |
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505 | * 3 Another task is already waiting. Service is Busy. |
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506 | */ |
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507 | extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout); |
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508 | |
---|
509 | /* Get received RX packet buffers that has previously been scheduled for |
---|
510 | * reception with grspw_dma_rx_prepare(). |
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511 | * |
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512 | * 1. Move Scheduled packets to RECV List (SCHED->RECV) |
---|
513 | * 2. Move all RECV packet to the callers list (RECV->USER) |
---|
514 | * 3. Schedule as many free packet buffers as possible (READY->SCHED) |
---|
515 | * |
---|
516 | * The above steps 1 may be skipped by setting 'opts': |
---|
517 | * bit0 = 1: Skip Step 1. |
---|
518 | * bit1 = 1: Skip Step 3. |
---|
519 | * |
---|
520 | * The fastest solution in retreiving received RX packets and preparing new |
---|
521 | * packet buffers for future receive, is to call: |
---|
522 | * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3) |
---|
523 | * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1) |
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524 | * |
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525 | * Return Code |
---|
526 | * -1 Error |
---|
527 | * 0 Successfully filled pkts list with packets from recv list. |
---|
528 | * 1 DMA stopped |
---|
529 | */ |
---|
530 | extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count); |
---|
531 | |
---|
532 | /* Add more RX packet buffers for future for reception. The received packets |
---|
533 | * can later be read out with grspw_dma_rx_recv(). |
---|
534 | * |
---|
535 | * 1. Move Received packets to RECV List (SCHED->RECV) |
---|
536 | * 2. Add the "free/ready" packet buffers to the READY List (USER->READY) |
---|
537 | * 3. Schedule as many packets as possible (READY->SCHED) |
---|
538 | * |
---|
539 | * The above steps 1 may be skipped by setting 'opts': |
---|
540 | * bit0 = 1: Skip Step 1. |
---|
541 | * bit1 = 1: Skip Step 3. |
---|
542 | * |
---|
543 | * The fastest solution in retreiving received RX packets and preparing new |
---|
544 | * packet buffers for future receive, is to call: |
---|
545 | * A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3) |
---|
546 | * B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1) |
---|
547 | * |
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548 | * Return Code |
---|
549 | * -1 Error |
---|
550 | * 0 Successfully added packet buffers from pkt list into the ready queue |
---|
551 | * 1 DMA stopped |
---|
552 | */ |
---|
553 | extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count); |
---|
554 | |
---|
555 | /* Get current number of Packets in respective RX Queue. */ |
---|
556 | extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv); |
---|
557 | |
---|
558 | /* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR), |
---|
559 | * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q, |
---|
560 | * condition is met. |
---|
561 | * If a link error occurs and the Stop on Link error is defined, this function |
---|
562 | * will also return to caller, however with an error. |
---|
563 | * The timeout argument is used to return after timeout ticks, regardless of |
---|
564 | * the other conditions. If timeout is zero, the function will wait forever |
---|
565 | * until the condition is satisfied. |
---|
566 | * |
---|
567 | * NOTE: if IRQ of RX descriptors are not enabled conditions are never |
---|
568 | * checked, this may hang infinitely unless a timeout has been specified |
---|
569 | * |
---|
570 | * Return Code |
---|
571 | * -1 Error |
---|
572 | * 0 Returing to caller because specified conditions are now fullfilled |
---|
573 | * 1 DMA stopped |
---|
574 | * 2 Timeout, conditions are not met |
---|
575 | * 3 Another task is already waiting. Service is Busy. |
---|
576 | */ |
---|
577 | extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout); |
---|
578 | |
---|
579 | extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg); |
---|
580 | extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg); |
---|
581 | |
---|
582 | extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts); |
---|
583 | extern void grspw_dma_stats_clr(void *c); |
---|
584 | |
---|
585 | /* Register GRSPW packet driver to Driver Manager */ |
---|
586 | void grspw2_register_drv (void); |
---|
587 | |
---|
588 | /*** GRSPW SpaceWire Packet List Handling Routines ***/ |
---|
589 | |
---|
590 | static inline void grspw_list_clr(struct grspw_list *list) |
---|
591 | { |
---|
592 | list->head = NULL; |
---|
593 | list->tail = NULL; |
---|
594 | } |
---|
595 | |
---|
596 | static inline int grspw_list_is_empty(struct grspw_list *list) |
---|
597 | { |
---|
598 | return (list->head == NULL); |
---|
599 | } |
---|
600 | |
---|
601 | /* Return Number of entries in list */ |
---|
602 | static inline int grspw_list_cnt(struct grspw_list *list) |
---|
603 | { |
---|
604 | struct grspw_pkt *lastpkt = NULL, *pkt = list->head; |
---|
605 | int cnt = 0; |
---|
606 | while ( pkt ) { |
---|
607 | cnt++; |
---|
608 | lastpkt = pkt; |
---|
609 | pkt = pkt->next; |
---|
610 | } |
---|
611 | if ( lastpkt && (list->tail != lastpkt) ) |
---|
612 | return -1; |
---|
613 | return cnt; |
---|
614 | } |
---|
615 | |
---|
616 | static inline void |
---|
617 | grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt) |
---|
618 | { |
---|
619 | pkt->next = NULL; |
---|
620 | if ( list->tail == NULL ) { |
---|
621 | list->head = pkt; |
---|
622 | } else { |
---|
623 | list->tail->next = pkt; |
---|
624 | } |
---|
625 | list->tail = pkt; |
---|
626 | } |
---|
627 | |
---|
628 | static inline void |
---|
629 | grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt) |
---|
630 | { |
---|
631 | pkt->next = list->head; |
---|
632 | if ( list->head == NULL ) { |
---|
633 | list->tail = pkt; |
---|
634 | } |
---|
635 | list->head = pkt; |
---|
636 | } |
---|
637 | |
---|
638 | static inline void |
---|
639 | grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist) |
---|
640 | { |
---|
641 | alist->tail->next = NULL; |
---|
642 | if ( list->tail == NULL ) { |
---|
643 | list->head = alist->head; |
---|
644 | } else { |
---|
645 | list->tail->next = alist->head; |
---|
646 | } |
---|
647 | list->tail = alist->tail; |
---|
648 | } |
---|
649 | |
---|
650 | static inline void |
---|
651 | grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist) |
---|
652 | { |
---|
653 | if ( list->head == NULL ) { |
---|
654 | list->tail = alist->tail; |
---|
655 | alist->tail->next = NULL; |
---|
656 | } else { |
---|
657 | alist->tail->next = list->head; |
---|
658 | } |
---|
659 | list->head = alist->head; |
---|
660 | } |
---|
661 | |
---|
662 | /* Remove dlist (delete-list) from head of list */ |
---|
663 | static inline void |
---|
664 | grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist) |
---|
665 | { |
---|
666 | list->head = dlist->tail->next; |
---|
667 | if ( list->head == NULL ) { |
---|
668 | list->tail = NULL; |
---|
669 | } |
---|
670 | dlist->tail->next = NULL; |
---|
671 | } |
---|
672 | |
---|
673 | /* Take A number of entries from head of list 'list' and put the entires |
---|
674 | * to rlist (result list). |
---|
675 | */ |
---|
676 | static inline int |
---|
677 | grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max) |
---|
678 | { |
---|
679 | int cnt; |
---|
680 | struct grspw_pkt *pkt, *last; |
---|
681 | |
---|
682 | pkt = list->head; |
---|
683 | |
---|
684 | if ( (max < 1) || (pkt == NULL) ) { |
---|
685 | grspw_list_clr(rlist); |
---|
686 | return 0; |
---|
687 | } |
---|
688 | |
---|
689 | cnt = 0; |
---|
690 | rlist->head = pkt; |
---|
691 | last = pkt; |
---|
692 | while ((cnt < max) && pkt) { |
---|
693 | last = pkt; |
---|
694 | pkt = pkt->next; |
---|
695 | cnt++; |
---|
696 | } |
---|
697 | rlist->tail = last; |
---|
698 | grspw_list_remove_head_list(list, rlist); |
---|
699 | return cnt; |
---|
700 | } |
---|
701 | |
---|
702 | #endif |
---|