source: rtems/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h @ ab9b447

5
Last change on this file since ab9b447 was ab9b447, checked in by Daniel Hellstrom <daniel@…>, on Jan 22, 2017 at 2:01:55 PM

leon, grspw_pkt: added work-task configuration options

Following changes:

  • possible for user to create work-tasks and assign custom message queues.
  • possible for user to override default ISR message to implement custom handling of DMA error, DMA RX/TX and link error from ISR.
  • work-task now checks message to determine which work to perform rather than looking at registers only, this makes it possible for user to implement custom handling.
  • exported work-queue message definitions and separated them so that a user can assign custom DMA RX/TX handling of a specific DMA channel.
  • added a work-task event callback to let user add custom handling or monitoring of DMA Stop, DMA error, Link Error or work-task exits etc.
  • Property mode set to 100644
File size: 28.1 KB
Line 
1/*
2 *  GRSPW/GRSPW2 SpaceWire Kernel Library Interface
3 *
4 *  COPYRIGHT (c) 2011
5 *  Cobham Gaisler AB
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11
12#ifndef __GRSPW_PKT_H__
13#define __GRSPW_PKT_H__
14
15struct grspw_pkt;
16
17/* Maximum number of GRSPW devices supported by driver */
18#define GRSPW_MAX 32
19
20/* Weak overridable variable the user can use to define the worker-task
21 * priority (0..255) or to disable (-1) the creation of the worker-task
22 * and the message queue to save space */
23extern int grspw_work_task_priority;
24
25#ifndef GRSPW_PKT_FLAGS
26#define GRSPW_PKT_FLAGS
27/*** TX Packet flags ***/
28
29/* Enable IRQ generation */
30#define TXPKT_FLAG_IE 0x0040
31
32/* Enable Header CRC generation (if CRC is available in HW)
33 * Header CRC will be appended (one byte at end of header)
34 */
35#define TXPKT_FLAG_HCRC 0x0100
36
37/* Enable Data CRC generation (if CRC is available in HW)
38 * Data CRC will be appended (one byte at end of packet)
39 */
40#define TXPKT_FLAG_DCRC 0x0200
41
42/* Control how many bytes the beginning of the Header
43 * the CRC should not be calculated for */
44#define TXPKT_FLAG_NOCRC_MASK 0x0000000f
45#define TXPKT_FLAG_NOCRC_LEN0 0x00000000
46#define TXPKT_FLAG_NOCRC_LEN1 0x00000001
47#define TXPKT_FLAG_NOCRC_LEN2 0x00000002
48#define TXPKT_FLAG_NOCRC_LEN3 0x00000003
49#define TXPKT_FLAG_NOCRC_LEN4 0x00000004
50#define TXPKT_FLAG_NOCRC_LEN5 0x00000005
51#define TXPKT_FLAG_NOCRC_LEN6 0x00000006
52#define TXPKT_FLAG_NOCRC_LEN7 0x00000007
53#define TXPKT_FLAG_NOCRC_LEN8 0x00000008
54#define TXPKT_FLAG_NOCRC_LEN9 0x00000009
55#define TXPKT_FLAG_NOCRC_LENa 0x0000000a
56#define TXPKT_FLAG_NOCRC_LENb 0x0000000b
57#define TXPKT_FLAG_NOCRC_LENc 0x0000000c
58#define TXPKT_FLAG_NOCRC_LENd 0x0000000d
59#define TXPKT_FLAG_NOCRC_LENe 0x0000000e
60#define TXPKT_FLAG_NOCRC_LENf 0x0000000f
61
62#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \
63                                TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC)
64
65/* Marks if packet was transmitted or not */
66#define TXPKT_FLAG_TX 0x4000
67
68/* Link Error */
69#define TXPKT_FLAG_LINKERR 0x8000
70
71#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR)
72
73/*** RX Packet Flags ***/
74
75/* Enable IRQ generation */
76#define RXPKT_FLAG_IE 0x0010
77
78#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE)
79
80/* Packet was truncated */
81#define RXPKT_FLAG_TRUNK 0x0800
82/* Data CRC error (only valid if RMAP CRC is enabled) */
83#define RXPKT_FLAG_DCRC 0x0400
84/* Header CRC error (only valid if RMAP CRC is enabled) */
85#define RXPKT_FLAG_HCRC 0x0200
86/* Error in End-of-Packet */
87#define RXPKT_FLAG_EEOP 0x0100
88/* Marks if packet was recevied or not */
89#define RXPKT_FLAG_RX 0x8000
90
91#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \
92                                RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP)
93
94/*** General packet flag options ***/
95
96/* Translate Hdr and/or Payload address */
97#define PKT_FLAG_TR_DATA 0x1000
98#define PKT_FLAG_TR_HDR 0x2000
99/* All General options */
100#define PKT_FLAG_MASK 0x3000
101
102#endif
103/* GRSPW RX/TX Packet structure.
104 *
105 * - For RX the 'hdr' and 'hlen' fields are not used, they are not written
106 *   by driver.
107 *
108 * - The 'pkt_id' field is untouched by driver, it is intended for packet
109 *   numbering or user-custom data.
110 *
111 * - The last packet in a list must have 'next' set to NULL.
112 *
113 * - data and hdr pointers are written without modification to hardware,
114 *   this means that caller must do address translation to hardware
115 *   address itself.
116 *
117 * - the 'flags' field are interpreted differently depending on transfer
118 *   type (RX/TX). See XXPKT_FLAG_* options above.
119 */
120struct grspw_pkt {
121        struct grspw_pkt *next; /* Next packet in list. NULL if last packet */
122        unsigned int pkt_id;    /* User assigned ID (not touched by driver) */
123        unsigned short flags;   /* RX/TX Options and status */
124        unsigned char reserved; /* Reserved, must be zero */
125        unsigned char hlen;     /* Length of Header Buffer (only TX) */
126        unsigned int dlen;      /* Length of Data Buffer */
127        void *data;     /* 4-byte or byte aligned depends on HW */
128        void *hdr;      /* 4-byte or byte aligned depends on HW (only TX) */
129};
130
131/* GRSPW SpaceWire Packet List */
132struct grspw_list {
133        struct grspw_pkt *head;
134        struct grspw_pkt *tail;
135};
136
137/* SpaceWire Link State */
138typedef enum {
139        SPW_LS_ERRRST = 0,
140        SPW_LS_ERRWAIT = 1,
141        SPW_LS_READY = 2,
142        SPW_LS_CONNECTING = 3,
143        SPW_LS_STARTED = 4,
144        SPW_LS_RUN = 5
145} spw_link_state_t;
146
147/* Address Configuration */
148struct grspw_addr_config {
149        /* Ignore address field and put all received packets to first
150         * DMA channel.
151         */
152        int promiscuous;
153
154        /* Default Node Address and Mask */
155        unsigned char def_addr;
156        unsigned char def_mask;
157        /* DMA Channel custom Node Address and Mask */
158        struct {
159                char node_en;                   /* Enable Separate Addr */
160                unsigned char node_addr;        /* Node address */
161                unsigned char node_mask;        /* Node address mask */
162        } dma_nacfg[4];
163};
164
165/* Hardware Support in GRSPW Core */
166struct grspw_hw_sup {
167        char    rmap;           /* If RMAP in HW is available */
168        char    rmap_crc;       /* If RMAP CRC is available */
169        char    rx_unalign;     /* RX unaligned (byte boundary) access allowed*/
170        char    nports;         /* Number of Ports (1 or 2) */
171        char    ndma_chans;     /* Number of DMA Channels (1..4) */
172        char    strip_adr;      /* Hardware can strip ADR from packet data */
173        char    strip_pid;      /* Hardware can strip PID from packet data */
174        int     hw_version;     /* GRSPW Hardware Version */
175        char    reserved[2];
176        char    irq;            /* SpW Distributed Interrupt available if 1 */
177        char    irq_num;        /* Number of interrupts that can be generated */
178        char    itmr_width;     /* SpW Intr. ISR timers bit width. 0=no timer */
179};
180
181struct grspw_core_stats {
182        int irq_cnt;
183        int err_credit;
184        int err_eeop;
185        int err_addr;
186        int err_parity;
187        int err_disconnect;
188        int err_escape;
189        int err_wsync; /* only in GRSPW1 */
190};
191
192/* grspw_link_ctrl() options */
193#define LINKOPTS_ENABLE         0x0000
194#define LINKOPTS_DISABLE        0x0001
195#define LINKOPTS_START          0x0002
196#define LINKOPTS_AUTOSTART      0x0004
197#define LINKOPTS_DIS_ONERR      0x0008  /* Disable DMA transmitter on link error
198                                         * Controls LE bit in DMACTRL register.
199                                         */
200#define LINKOPTS_DIS_ON_CE      0x0020000/* Disable Link on Credit error */
201#define LINKOPTS_DIS_ON_ER      0x0040000/* Disable Link on Escape error */
202#define LINKOPTS_DIS_ON_DE      0x0080000/* Disable Link on Disconnect error */
203#define LINKOPTS_DIS_ON_PE      0x0100000/* Disable Link on Parity error */
204#define LINKOPTS_DIS_ON_WE      0x0400000/* Disable Link on write synchonization
205                                          * error (GRSPW1 only)
206                                          */
207#define LINKOPTS_DIS_ON_EE      0x1000000/* Disable Link on Early EOP/EEP error*/
208
209/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */
210#define LINKOPTS_EIRQ           0x0200  /* Enable Error Link IRQ */
211
212#define LINKOPTS_MASK           0x15e020f/* All above options */
213#define LINKOPTS_MASK_DIS_ON    0x15e0000/* All disable link on error options
214                                          * On a certain error the link disable
215                                          * bit will be written and the work
216                                          * task will call dma_stop() for all
217                                          * channels.
218                                          */
219
220#define LINKSTS_CE              0x002   /* Credit error */
221#define LINKSTS_ER              0x004   /* Escape error */
222#define LINKSTS_DE              0x008   /* Disconnect error */
223#define LINKSTS_PE              0x010   /* Parity error */
224#define LINKSTS_WE              0x040   /* Write synchonization error (GRSPW1 only) */
225#define LINKSTS_IA              0x080   /* Invalid address */
226#define LINKSTS_EE              0x100   /* Early EOP/EEP */
227#define LINKSTS_MASK            0x1de
228
229/* grspw_tc_ctrl() options */
230#define TCOPTS_EN_RXIRQ 0x0001  /* Tick-Out IRQ */
231#define TCOPTS_EN_TX    0x0004
232#define TCOPTS_EN_RX    0x0008
233
234/* grspw_ic_ctrl() options:
235 * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines
236 */
237#define ICOPTS_INTNUM           (0x1f << 27)
238#define ICOPTS_EN_SPWIRQ_ON_EE  (1 << 24)
239#define ICOPTS_EN_SPWIRQ_ON_IA  (1 << 23)
240#define ICOPTS_EN_PRIO          (1 << 22)
241#define ICOPTS_EN_TIMEOUTIRQ    (1 << 20)
242#define ICOPTS_EN_ACKIRQ        (1 << 19)
243#define ICOPTS_EN_TICKOUTIRQ    (1 << 18)
244#define ICOPTS_EN_RX            (1 << 17)
245#define ICOPTS_EN_TX            (1 << 16)
246#define ICOPTS_BASEIRQ          (0x1f << 8)
247#define ICOPTS_EN_FLAGFILTER    (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */
248
249/* grspw_ic_rlisr() and grspw_ic_rlintack()  */
250#define ICRELOAD_EN             (1 << 31)
251#define ICRELOAD_MASK           0x7fffffff
252
253/* grspw_rmap_ctrl() options */
254#define RMAPOPTS_EN_RMAP        0x0001
255#define RMAPOPTS_EN_BUF         0x0002
256
257/* grspw_dma_config.flags options */
258#define DMAFLAG_NO_SPILL        0x0001  /* See HW doc DMA-CTRL NS bit */
259#define DMAFLAG_RESV1           0x0002  /* HAS NO EFFECT */
260#define DMAFLAG_STRIP_ADR       0x0004  /* See HW doc DMA-CTRL SA bit */
261#define DMAFLAG_STRIP_PID       0x0008  /* See HW doc DMA-CTRL SP bit */
262#define DMAFLAG_RESV2           0x0010  /* HAS NO EFFECT */
263#define DMAFLAG_MASK    (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID)
264/* grspw_dma_config.flags misc options (not shifted internally) */
265#define DMAFLAG2_TXIE   0x00100000      /* See HW doc DMA-CTRL TI bit.
266                                         * Used to enable TX DMA interrupt
267                                         * when tx_irq_en_cnt=0.
268                                         */
269#define DMAFLAG2_RXIE   0x00200000      /* See HW doc DMA-CTRL RI bit.
270                                         * Used to enable RX DMA interrupt
271                                         * when rx_irq_en_cnt=0.
272                                         */
273#define DMAFLAG2_MASK   (DMAFLAG2_TXIE | DMAFLAG2_RXIE)
274
275struct grspw_dma_config {
276        int flags;              /* DMA config flags, see DMAFLAG1&2_* options */
277        int rxmaxlen;           /* RX Max Packet Length */
278        int rx_irq_en_cnt;      /* Enable RX IRQ every cnt descriptors */
279        int tx_irq_en_cnt;      /* Enable TX IRQ every cnt descriptors */
280};
281
282/* Statistics per DMA channel */
283struct grspw_dma_stats {
284        /* IRQ Statistics */
285        int irq_cnt;            /* Number of DMA IRQs generated by channel */
286
287        /* Descriptor Statistics */
288        int tx_pkts;            /* Number of Transmitted packets */
289        int tx_err_link;        /* Number of Transmitted packets with Link Error*/
290        int rx_pkts;            /* Number of Received packets */
291        int rx_err_trunk;       /* Number of Received Truncated packets */
292        int rx_err_endpkt;      /* Number of Received packets with bad ending */
293
294        /* Diagnostics to help developers sizing their number buffers to avoid
295         * out-of-buffers or other phenomenons.
296         */
297        int send_cnt_min;       /* Minimum number of packets in TX SEND Q */
298        int send_cnt_max;       /* Maximum number of packets in TX SEND Q */
299        int tx_sched_cnt_min;   /* Minimum number of packets in TX SCHED Q */
300        int tx_sched_cnt_max;   /* Maximum number of packets in TX SCHED Q */
301        int sent_cnt_max;       /* Maximum number of packets in TX SENT Q */
302        int tx_work_cnt;        /* Times the work thread processed TX BDs */
303        int tx_work_enabled;    /* No. RX BDs enabled by work thread */
304
305        int ready_cnt_min;      /* Minimum number of packets in RX READY Q */
306        int ready_cnt_max;      /* Maximum number of packets in RX READY Q */
307        int rx_sched_cnt_min;   /* Minimum number of packets in RX SCHED Q */
308        int rx_sched_cnt_max;   /* Maximum number of packets in RX SCHED Q */
309        int recv_cnt_max;       /* Maximum number of packets in RX RECV Q */
310        int rx_work_cnt;        /* Times the work thread processed RX BDs */
311        int rx_work_enabled;    /* No. RX BDs enabled by work thread */
312};
313
314/* ISR message sending call back. Compatible with rtems_message_queue_send().
315 * The 'buf' parameter has a pointer to a WORK-TASK message defined by the
316 * WORK_* macros below. The message indicates what GRSPW device operations
317 * are pending, thus what caused the interrupt.
318 *
319 * \param data   defined by grspw_work_config.msgisr_arg, default a rtems_id.
320 * \param buf    Pointer to a 32-bit message word
321 * \param n      Always 4 (byte size of buf).
322 */
323typedef int (*grspw_msgqisr_t)(void *data, unsigned int *buf, unsigned int n);
324
325/* Work message definitions, the int sent to *buf
326 * Bits 31..24: reserved.
327 * Bits 23..16: GRSPW device number message is associated with.
328 * Bit  15:     reserved.
329 * Bit  14:     work-task shall delete message queue on exit.
330 * Bit  13:     work-task shall exit and delete itself.
331 * Bit  12:     link error - shut down all DMA operations (stop DMA channels).
332 * Bit  11..8:  Indicats DMA error on DMA channel 3..0.
333 * Bit  7..0:   Indicats RX and/or TX packets completed on channel 3..0.
334 */
335#define WORK_NONE         0
336#define WORK_SHUTDOWN     0x1000 /* Signal shut down */
337#define WORK_QUIT_TASK    0x2000 /* Work task shall exit (delete itself) */
338#define WORK_FREE_MSGQ    0x4000 /* Delete MsgQ (valid when WORK_QUIT_TASK) */
339#define WORK_DMA(chan, rxtx) (((rxtx) & 0x3) << ((chan) * 2))
340#define WORK_DMA_TX(chan) WORK_DMA(chan, 1)
341#define WORK_DMA_RX(chan) WORK_DMA(chan, 2)
342#define WORK_DMA_ER(chan) (0x1 << ((chan) + 8))
343#define WORK_DMA_MASK     0xfff /* max 4 channels all work */
344#define WORK_DMA_TX_MASK  0x055 /* max 4 channels TX work */
345#define WORK_DMA_RX_MASK  0x0aa /* max 4 channels RX work */
346#define WORK_DMA_ER_MASK  0xf00 /* max 4 channels Error work */
347#define WORK_DMA_CHAN_MASK(chan) (WORK_DMA_ER(chan) | WORK_DMA(chan, 0x3))
348#define WORK_CORE_BIT     16
349#define WORK_CORE_MASK    0x00ff0000
350#define WORK_CORE(device) ((device) << WORK_CORE_BIT)
351
352/* Message Q used to send messages to work task */
353struct grspw_work_config {
354        grspw_msgqisr_t msgisr;
355        void *msgisr_arg; /* example: rtems_id to Msg Q */
356};
357
358extern void grspw_initialize_user(
359        /* Callback every time a GRSPW device is found. Args: DeviceIndex */
360        void *(*devfound)(int),
361        /* Callback every time a GRSPW device is removed. Args:
362         * int   = DeviceIndex
363         * void* = Return Value from devfound()
364         */
365        void (*devremove)(int,void*)
366        );
367
368/* Creates a MsgQ (optional) and spawns a worker task associated with the
369 * message Q. The task can also be associated with a custom msgQ if *msgQ.
370 * is non-zero.
371 *
372 * \param prio     Task priority, set to -1 for default.
373 * \param stack    Task stack size, set to 0 for default.
374 * \param msgQ     pMsgQ=NULL: illegal,
375 *                 pMsqQ==0: create new MsgQ with task and place in *pMsgQ,
376 *                 *pmsqQ!=0: pointer to MsgQ used for task.
377 * \param msgMax   Maximum number of messages, set to 0 for default.
378 * \return         0 on failure, task id on success.
379 */
380extern rtems_id grspw_work_spawn(int prio, int stack, rtems_id *pMsgQ, int msgMax);
381
382/* Free task associated with message queue and optionally also the message
383 * queue itself. The message queue is deleted by the work task and is therefore
384 * delayed until it the work task resumes its execution.
385 */
386extern rtems_status_code grspw_work_free(rtems_id msgQ, int freeMsgQ);
387
388/* Configure a GRSPW device Work task and Message Q set up.
389 * This affects messages to:
390 *  - DMA AHB error interrupt handling (mandatory)
391 *  - Link status interrupt handling (optional)
392 *  - RX DMA, defaults to common msgQ (configured per DMA channel)
393 */
394extern void grspw_work_cfg(void *d, struct grspw_work_config *wc);
395
396/* Work-task function, called only from the work task. The function is provided
397 * as a way for the user to create its own work tasks.
398 * The argument determines which message queue the task shall read its
399 * work jobs from.
400 *
401 * The messages are always 32-bit words and follows the format defined by the
402 * WORK_* macros above.
403 */
404extern void grspw_work_func(rtems_id msgQ);
405
406enum grspw_worktask_ev {
407        WORKTASK_EV_NONE = 0,
408        WORKTASK_EV_QUIT = 1,
409        WORKTASK_EV_SHUTDOWN = 2,
410        WORKTASK_EV_DMA_STOP = 3,
411};
412
413/* Weak function to let user override. Function called every time one of the
414 * events above is handled by the work-task. The message 'msg' is the current
415 * message being processed by the work-task.
416 * The user can for example add custom code to invoke on a DMA error, link
417 * error or monitor when the work-task exits after a call to grspw_work_free().
418 */
419extern void grspw_work_event(enum grspw_worktask_ev ev, unsigned int msg);
420
421extern int grspw_dev_count(void);
422extern void *grspw_open(int dev_no);
423extern int grspw_close(void *d);
424extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw);
425extern void grspw_stats_read(void *d, struct grspw_core_stats *sts);
426extern void grspw_stats_clr(void *d);
427
428/* Set and Read current node address configuration. The dma_nacfg[N] field
429 * represents the configuration for DMA Channel N.
430 *
431 * Set cfg->promiscous to -1 in order to only read current configuration.
432 */
433extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg);
434
435/*** Link Control interface ***/
436/* Read Link State */
437extern spw_link_state_t grspw_link_state(void *d);
438/* options [in/out]: set to -1 to only read current config
439 *
440 * CLKDIV register contain:
441 *  bits 7..0  : Clock Div RUN (only run-state)
442 *  bits 15..8 : Clock Div During Startup (all link states except run-state)
443 */
444extern void grspw_link_ctrl(void *d, int *options, int *stscfg, int *clkdiv);
445/* Read the current value of the status register */
446extern unsigned int grspw_link_status(void *d);
447/* Clear bits in the status register */
448extern void grspw_link_status_clr(void *d, unsigned int clearmask);
449
450/*** Time Code Interface ***/
451/* Generate Tick-In (increment Time Counter, Send Time Code) */
452extern void grspw_tc_tx(void *d);
453/* Control Timcode settings of core */
454extern void grspw_tc_ctrl(void *d, int *options);
455/* Assign ISR Function to TimeCode RX IRQ */
456extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data);
457/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value
458 * TCTRL   = bits 7 and 6
459 * TIMECNT = bits 5 to 0
460 */
461extern void grspw_tc_time(void *d, int *time);
462
463/*** Interrupt-code Interface ***/
464struct spwpkt_ic_config {
465        unsigned int tomask;
466        unsigned int aamask;
467        unsigned int scaler;
468        unsigned int isr_reload;
469        unsigned int ack_reload;
470};
471/* Function Interrupt-Code ISR callback prototype. Called when respective
472 * interrupt handling option has been enabled by grspw_ic_ctrl(), the
473 * arguments rxirq, rxack and intto are read from the registers of the
474 * GRSPW core read by the GRSPW ISR, they are individually valid only when
475 * repective handling been turned on.
476 *
477 * data    - Custom data provided by user
478 * rxirq   - Interrupt-Code Recevie register of the GRSPW core read by ISR
479 *           (only defined if IQ bit enabled through grspw_ic_ctrl())
480 * rxack   - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR
481 *           (only defined if AQ bit enabled through grspw_ic_ctrl())
482 * intto   - Interrupt Tick-out Recevie register of the GRSPW core read by ISR
483 *           (only defined if TQ bit enabled through grspw_ic_ctrl())
484 */
485typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq,
486                                unsigned int rxack, unsigned int intto);
487/* Control Interrupt-code settings of core
488 * Write if 'options' not pointing to -1, always read current value
489 */
490extern void grspw_ic_ctrl(void *d, unsigned int *options);
491/* Write (rw&1 == 1) configuration parameters to registers and/or,
492 * Read  (rw&2 == 1) configuration parameters from registers, in that sequence.
493 */
494extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg);
495/* Read or Write Interrupt-code status registers.
496 * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write.
497 * If *ptr is NULL no operation.
498 */
499extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack,
500                        unsigned int *intto);
501/* Generate Tick-In for the given Interrupt-code
502 * Returns zero on success and non-zero on failure
503 *
504 * Interrupt code bits (ic):
505 * Bit 5 - ACK if 1
506 * Bits 4-0 Interrupt-code number
507 */
508extern int grspw_ic_tickin(void *d, int ic);
509/* Assign handler function to Interrupt-code timeout IRQ */
510extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data);
511
512/*** RMAP Control Interface ***/
513/* Set (not -1) and/or read RMAP options. */
514extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey);
515extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc);
516
517/*** SpW Port Control Interface ***/
518
519/* Select port, if
520 * -1=The current selected port is returned
521 * 0=Port 0
522 * 1=Port 1
523 * Other positive values=Both Port0 and Port1
524 */
525extern int grspw_port_ctrl(void *d, int *port);
526/* Returns Number ports available in hardware */
527extern int grspw_port_count(void *d);
528/* Returns the current active port */
529extern int grspw_port_active(void *d);
530
531/*** DMA Interface ***/
532extern void *grspw_dma_open(void *d, int chan_no);
533extern int grspw_dma_close(void *c);
534
535extern int grspw_dma_start(void *c);
536extern void grspw_dma_stop(void *c);
537
538/* Schedule List of packets for transmission at some point in
539 * future.
540 *
541 * 1. Move transmitted packets to SENT List (SCHED->SENT)
542 * 2. Add the requested packets to the SEND List (USER->SEND)
543 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
544 *
545 * Call this function with pkts=NULL to just do step 1 and 3. This may be
546 * required in Polling-mode.
547 *
548 * The above steps 1 and 3 may be skipped by setting 'opts':
549 *  bit0 = 1: Skip Step 1.
550 *  bit1 = 1: Skip Step 3.
551 * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then
552 * the work queue will be totaly responsible for handling descriptors.
553 *
554 * The fastest solution in retreiving sent TX packets and sending new frames
555 * is to call:
556 *  A. grspw_dma_tx_reclaim(opts=0)
557 *  B. grspw_dma_tx_send(opts=1)
558 *
559 * NOTE: the TXPKT_FLAG_TX flag must not be set.
560 *
561 * Return Code
562 *  -1   Error
563 *  0    Successfully added pkts to send/sched list
564 *  1    DMA stopped. No operation.
565 */
566extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count);
567
568/* Reclaim TX packet buffers that has previously been scheduled for transmission
569 * with grspw_dma_tx_send().
570 *
571 * 1. Move transmitted packets to SENT List (SCHED->SENT)
572 * 2. Move all SENT List to pkts list (SENT->USER)
573 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
574 *
575 * The above steps 1 may be skipped by setting 'opts':
576 *  bit0 = 1: Skip Step 1.
577 *  bit1 = 1: Skip Step 3.
578 *
579 * The fastest solution in retreiving sent TX packets and sending new frames
580 * is to call:
581 *  A. grspw_dma_tx_reclaim(opts=2) (Skip step 3)
582 *  B. grspw_dma_tx_send(opts=1) (Skip step 1)
583 *
584 * Return Code
585 *  -1   Error
586 *  0    Successful. pkts list filled with all packets from sent list
587 *  1    Same as 0, but indicates that DMA stopped
588 */
589extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count);
590
591/* Get current number of Packets in respective TX Queue. */
592extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent, int *hw);
593
594#define GRSPW_OP_AND 0
595#define GRSPW_OP_OR 1
596/* Block until send_cnt or fewer packets are Queued in "Send and Scheduled" Q,
597 * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition
598 * is met.
599 * If a link error occurs and the Stop on Link error is defined, this function
600 * will also return to caller.
601 * The timeout argument is used to return after timeout ticks, regardless of
602 * the other conditions. If timeout is zero, the function will wait forever
603 * until the condition is satisfied.
604 *
605 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
606 *       checked, this may hang infinitely unless a timeout has been specified
607 *
608 * Return Code
609 *  -1   Error
610 *  0    Returing to caller because specified conditions are now fullfilled
611 *  1    DMA stopped
612 *  2    Timeout, conditions are not met
613 *  3    Another task is already waiting. Service is Busy.
614 */
615extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout);
616
617/* Get received RX packet buffers that has previously been scheduled for
618 * reception with grspw_dma_rx_prepare().
619 *
620 * 1. Move Scheduled packets to RECV List (SCHED->RECV)
621 * 2. Move all RECV packet to the callers list (RECV->USER)
622 * 3. Schedule as many free packet buffers as possible (READY->SCHED)
623 *
624 * The above steps 1 may be skipped by setting 'opts':
625 *  bit0 = 1: Skip Step 1.
626 *  bit1 = 1: Skip Step 3.
627 *
628 * The fastest solution in retreiving received RX packets and preparing new
629 * packet buffers for future receive, is to call:
630 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
631 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
632 *
633 * Return Code
634 *  -1   Error
635 *  0    Successfully filled pkts list with packets from recv list.
636 *  1    DMA stopped
637 */
638extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count);
639
640/* Add more RX packet buffers for future for reception. The received packets
641 * can later be read out with grspw_dma_rx_recv().
642 *
643 * 1. Move Received packets to RECV List (SCHED->RECV)
644 * 2. Add the "free/ready" packet buffers to the READY List (USER->READY)
645 * 3. Schedule as many packets as possible (READY->SCHED)
646 *
647 * The above steps 1 may be skipped by setting 'opts':
648 *  bit0 = 1: Skip Step 1.
649 *  bit1 = 1: Skip Step 3.
650 *
651 * The fastest solution in retreiving received RX packets and preparing new
652 * packet buffers for future receive, is to call:
653 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
654 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
655 *
656 * Return Code
657 *  -1   Error
658 *  0    Successfully added packet buffers from pkt list into the ready queue
659 *  1    DMA stopped
660 */
661extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count);
662
663/* Get current number of Packets in respective RX Queue. */
664extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv, int *hw);
665
666/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR),
667 * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q,
668 * condition is met.
669 * If a link error occurs and the Stop on Link error is defined, this function
670 * will also return to caller, however with an error.
671 * The timeout argument is used to return after timeout ticks, regardless of
672 * the other conditions. If timeout is zero, the function will wait forever
673 * until the condition is satisfied.
674 *
675 * NOTE: if IRQ of RX descriptors are not enabled conditions are never
676 *       checked, this may hang infinitely unless a timeout has been specified
677 *
678 * Return Code
679 *  -1   Error
680 *  0    Returing to caller because specified conditions are now fullfilled
681 *  1    DMA stopped
682 *  2    Timeout, conditions are not met
683 *  3    Another task is already waiting. Service is Busy.
684 */
685extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout);
686
687extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg);
688extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg);
689
690extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts);
691extern void grspw_dma_stats_clr(void *c);
692
693/* Register GRSPW packet driver to Driver Manager */
694void grspw2_register_drv (void);
695
696/*** GRSPW SpaceWire Packet List Handling Routines ***/
697
698static inline void grspw_list_clr(struct grspw_list *list)
699{
700        list->head = NULL;
701        list->tail = NULL;
702}
703
704static inline int grspw_list_is_empty(struct grspw_list *list)
705{
706        return (list->head == NULL);
707}
708
709/* Return Number of entries in list */
710static inline int grspw_list_cnt(struct grspw_list *list)
711{
712        struct grspw_pkt *lastpkt = NULL, *pkt = list->head;
713        int cnt = 0;
714        while ( pkt ) {
715                cnt++;
716                lastpkt = pkt;
717                pkt = pkt->next;
718        }
719        if ( lastpkt && (list->tail != lastpkt) )
720                return -1;
721        return cnt;
722}
723
724static inline void
725grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt)
726{
727        pkt->next = NULL;
728        if ( list->tail == NULL ) {
729                list->head = pkt;
730        } else {
731                list->tail->next = pkt;
732        }
733        list->tail = pkt;
734}
735
736static inline void 
737grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt)
738{
739        pkt->next = list->head;
740        if ( list->head == NULL ) {
741                list->tail = pkt;
742        }
743        list->head = pkt;
744}
745
746static inline void
747grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist)
748{
749        if (grspw_list_is_empty(alist)) {
750                return;
751        }
752        alist->tail->next = NULL;
753        if ( list->tail == NULL ) {
754                list->head = alist->head;
755        } else {
756                list->tail->next = alist->head;
757        }
758        list->tail = alist->tail;
759}
760
761static inline void
762grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist)
763{
764        if (grspw_list_is_empty(alist)) {
765                return;
766        }
767        if ( list->head == NULL ) {
768                list->tail = alist->tail;
769                alist->tail->next = NULL;
770        } else {
771                alist->tail->next = list->head;
772        }
773        list->head = alist->head;
774}
775
776/* Remove dlist (delete-list) from head of list */
777static inline void
778grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist)
779{
780        if (grspw_list_is_empty(dlist)) {
781                return;
782        }
783        list->head = dlist->tail->next;
784        if ( list->head == NULL ) {
785                list->tail = NULL;
786        }
787        dlist->tail->next = NULL;
788}
789
790/* Take A number of entries from head of list 'list' and put the entires
791 * to rlist (result list).
792 */
793static inline int
794grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max)
795{
796        int cnt;
797        struct grspw_pkt *pkt, *last;
798
799        pkt = list->head;
800
801        if ( (max < 1) || (pkt == NULL) ) {
802                grspw_list_clr(rlist);
803                return 0;
804        }
805
806        cnt = 0;
807        rlist->head = pkt;
808        last = pkt;
809        while ((cnt < max) && pkt) {
810                last = pkt;
811                pkt = pkt->next;
812                cnt++;
813        }
814        rlist->tail = last;
815        grspw_list_remove_head_list(list, rlist);
816        return cnt;
817}
818
819#endif
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