source: rtems/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h @ 56fc7809

4.115
Last change on this file since 56fc7809 was 56fc7809, checked in by Andreas Larsson <andreas@…>, on 07/03/13 at 08:16:30

GRSPW_PKT: Add support for Interrupt-codes

Update: Daniel Hellstrom updated SpW-IRQ implementation accoring to

changes in hardware register layout and features.
  • Property mode set to 100644
File size: 21.7 KB
Line 
1/*
2 *  GRSPW/GRSPW2 SpaceWire Kernel Library Interface
3 *
4 *  COPYRIGHT (c) 2011
5 *  Cobham Gaisler AB
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 */
11
12#ifndef __GRSPW_PKT_H__
13#define __GRSPW_PKT_H__
14
15struct grspw_pkt;
16
17/* Maximum number of GRSPW devices supported by driver */
18#define GRSPW_MAX 32
19
20/* Weak overridable variable the user can use to define the worker-task
21 * priority (0..255) or to disable (-1) the creation of the worker-task
22 * and the message queue to save space */
23extern int grspw_work_task_priority;
24
25#ifndef GRSPW_PKT_FLAGS
26#define GRSPW_PKT_FLAGS
27/*** TX Packet flags ***/
28
29/* Enable IRQ generation */
30#define TXPKT_FLAG_IE 0x0040
31
32/* Enable Header CRC generation (if CRC is available in HW)
33 * Header CRC will be appended (one byte at end of header)
34 */
35#define TXPKT_FLAG_HCRC 0x0100
36
37/* Enable Data CRC generation (if CRC is available in HW)
38 * Data CRC will be appended (one byte at end of packet)
39 */
40#define TXPKT_FLAG_DCRC 0x0200
41
42/* Control how many bytes the beginning of the Header
43 * the CRC should not be calculated for */
44#define TXPKT_FLAG_NOCRC_MASK 0x0000000f
45#define TXPKT_FLAG_NOCRC_LEN0 0x00000000
46#define TXPKT_FLAG_NOCRC_LEN1 0x00000001
47#define TXPKT_FLAG_NOCRC_LEN2 0x00000002
48#define TXPKT_FLAG_NOCRC_LEN3 0x00000003
49#define TXPKT_FLAG_NOCRC_LEN4 0x00000004
50#define TXPKT_FLAG_NOCRC_LEN5 0x00000005
51#define TXPKT_FLAG_NOCRC_LEN6 0x00000006
52#define TXPKT_FLAG_NOCRC_LEN7 0x00000007
53#define TXPKT_FLAG_NOCRC_LEN8 0x00000008
54#define TXPKT_FLAG_NOCRC_LEN9 0x00000009
55#define TXPKT_FLAG_NOCRC_LENa 0x0000000a
56#define TXPKT_FLAG_NOCRC_LENb 0x0000000b
57#define TXPKT_FLAG_NOCRC_LENc 0x0000000c
58#define TXPKT_FLAG_NOCRC_LENd 0x0000000d
59#define TXPKT_FLAG_NOCRC_LENe 0x0000000e
60#define TXPKT_FLAG_NOCRC_LENf 0x0000000f
61
62/* Marks if packet was transmitted or not */
63#define TXPKT_FLAG_TX 0x8000
64
65#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \
66                                TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC)
67
68/* Link Error */
69#define TXPKT_FLAG_LINKERR 0x4000
70
71#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_LINKERR)
72
73/*** RX Packet Flags ***/
74
75/* Enable IRQ generation */
76#define RXPKT_FLAG_IE 0x0010
77
78#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE)
79
80/* Packet was truncated */
81#define RXPKT_FLAG_TRUNK 0x0800
82/* Data CRC error (only valid if RMAP CRC is enabled) */
83#define RXPKT_FLAG_DCRC 0x0400
84/* Header CRC error (only valid if RMAP CRC is enabled) */
85#define RXPKT_FLAG_HCRC 0x0200
86/* Error in End-of-Packet */
87#define RXPKT_FLAG_EEOP 0x0100
88/* Marks if packet was recevied or not */
89#define RXPKT_FLAG_RX 0x8000
90
91#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \
92                                RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP)
93
94/*** General packet flag options ***/
95
96/* Translate Hdr and/or Payload address */
97#define PKT_FLAG_TR_DATA 0x1000
98#define PKT_FLAG_TR_HDR 0x2000
99/* All General options */
100#define PKT_FLAG_MASK 0x3000
101
102#endif
103/* GRSPW RX/TX Packet structure.
104 *
105 * - For RX the 'hdr' and 'hlen' fields are not used, they are not written
106 *   by driver.
107 *
108 * - The 'pkt_id' field is untouched by driver, it is intended for packet
109 *   numbering or user-custom data.
110 *
111 * - The last packet in a list must have 'next' set to NULL.
112 *
113 * - data and hdr pointers are written without modification to hardware,
114 *   this means that caller must do address translation to hardware
115 *   address itself.
116 *
117 * - the 'flags' field are interpreted differently depending on transfer
118 *   type (RX/TX). See XXPKT_FLAG_* options above.
119 */
120struct grspw_pkt {
121        struct grspw_pkt *next;
122        unsigned int pkt_id;    /* User assigned ID */
123        unsigned short flags;   /* RX/TX Options */
124        unsigned char reserved; /* Reserved, must be zero */
125        unsigned char hlen;     /* Length of Header Buffer */
126        unsigned int dlen;      /* Length of Data Buffer */
127        void *data;     /* 4-byte or byte aligned depends on HW */
128        void *hdr;      /* 4-byte or byte aligned depends on HW */
129};
130
131/* GRSPW SpaceWire Packet List */
132struct grspw_list {
133        struct grspw_pkt *head;
134        struct grspw_pkt *tail;
135};
136
137/* SpaceWire Link State */
138typedef enum {
139        SPW_LS_ERRRST = 0,
140        SPW_LS_ERRWAIT = 1,
141        SPW_LS_READY = 2,
142        SPW_LS_CONNECTING = 3,
143        SPW_LS_STARTED = 4,
144        SPW_LS_RUN = 5
145} spw_link_state_t;
146
147/* Address Configuration */
148struct grspw_addr_config {
149        /* Ignore address field and put all received packets to first
150         * DMA channel.
151         */
152        int promiscuous;
153
154        /* Default Node Address and Mask */
155        unsigned char def_addr;
156        unsigned char def_mask;
157        /* DMA Channel custom Node Address and Mask */
158        struct {
159                char node_en;                   /* Enable Separate Addr */
160                unsigned char node_addr;        /* Node address */
161                unsigned char node_mask;        /* Node address mask */
162        } dma_nacfg[4];
163};
164
165/* Hardware Support in GRSPW Core */
166struct grspw_hw_sup {
167        char    rmap;           /* If RMAP in HW is available */
168        char    rmap_crc;       /* If RMAP CRC is available */
169        char    rx_unalign;     /* RX unaligned (byte boundary) access allowed*/
170        char    nports;         /* Number of Ports (1 or 2) */
171        char    ndma_chans;     /* Number of DMA Channels (1..4) */
172        char    strip_adr;      /* Hardware can strip ADR from packet data */
173        char    strip_pid;      /* Hardware can strip PID from packet data */
174        int     hw_version;     /* GRSPW Hardware Version */
175        char    reserved[2];
176        char    irq;            /* SpW Distributed Interrupt available if 1 */
177        char    irq_num;        /* Number of interrupts that can be generated */
178        char    itmr_width;     /* SpW Intr. ISR timers bit width. 0=no timer */
179};
180
181struct grspw_core_stats {
182        int irq_cnt;
183        int err_credit;
184        int err_eeop;
185        int err_addr;
186        int err_parity;
187        int err_escape;
188        int err_wsync; /* only in GRSPW1 */
189};
190
191/* grspw_link_ctrl() options */
192#define LINKOPTS_ENABLE         0x0000
193#define LINKOPTS_DISABLE        0x0001
194#define LINKOPTS_START          0x0002
195#define LINKOPTS_AUTOSTART      0x0004
196#define LINKOPTS_DIS_ONERR      0x0008
197/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */
198#define LINKOPTS_IRQ            0x0200  /* Enable Error Link IRQ */
199#define LINKOPTS_MASK           0x020f  /* All above options */
200
201/* grspw_tc_ctrl() options */
202#define TCOPTS_EN_RXIRQ 0x0001  /* Tick-Out IRQ */
203#define TCOPTS_EN_TX    0x0004
204#define TCOPTS_EN_RX    0x0008
205
206/* grspw_ic_ctrl() options:
207 * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines
208 */
209#define ICOPTS_INTNUM           (0x1f << 27)
210#define ICOPTS_EN_SPWIRQ_ON_EE  (1 << 24)
211#define ICOPTS_EN_SPWIRQ_ON_IA  (1 << 23)
212#define ICOPTS_EN_PRIO          (1 << 22)
213#define ICOPTS_EN_TIMEOUTIRQ    (1 << 20)
214#define ICOPTS_EN_ACKIRQ        (1 << 19)
215#define ICOPTS_EN_TICKOUTIRQ    (1 << 18)
216#define ICOPTS_EN_RX            (1 << 17)
217#define ICOPTS_EN_TX            (1 << 16)
218#define ICOPTS_BASEIRQ          (0x1f << 8)
219#define ICOPTS_EN_FLAGFILTER    (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */
220
221/* grspw_ic_rlisr() and grspw_ic_rlintack()  */
222#define ICRELOAD_EN             (1 << 31)
223#define ICRELOAD_MASK           0x7fffffff
224
225/* grspw_rmap_ctrl() options */
226#define RMAPOPTS_EN_RMAP        0x0001
227#define RMAPOPTS_EN_BUF         0x0002
228
229/* grspw_dma_config.flags options */
230#define DMAFLAG_NO_SPILL        0x0001  /* See HW doc DMA-CTRL NS bit */
231#define DMAFLAG_RESV1           0x0002  /* HAS NO EFFECT */
232#define DMAFLAG_STRIP_ADR       0x0004  /* See HW doc DMA-CTRL SA bit */
233#define DMAFLAG_STRIP_PID       0x0008  /* See HW doc DMA-CTRL SP bit */
234#define DMAFLAG_RESV2           0x0010  /* HAS NO EFFECT */
235#define DMAFLAG_MASK    (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID)
236
237struct grspw_dma_config {
238        int flags;
239
240        int rxmaxlen;           /* RX Max Packet Length */
241        int rx_irq_en_cnt;      /* Enable RX IRQ every cnt descriptors */
242        int tx_irq_en_cnt;      /* Enable TX IRQ every cnt descriptors */
243};
244
245/* Statistics per DMA channel */
246struct grspw_dma_stats {
247        /* IRQ Statistics */
248        int irq_cnt;            /* Number of DMA IRQs generated by channel */
249
250        /* Descriptor Statistics */
251        int tx_pkts;            /* Number of Transmitted packets */
252        int tx_err_link;        /* Number of Transmitted packets with Link Error*/
253        int rx_pkts;            /* Number of Received packets */
254        int rx_err_trunk;       /* Number of Received Truncated packets */
255        int rx_err_endpkt;      /* Number of Received packets with bad ending */
256
257        /* Diagnostics to help developers sizing their number buffers to avoid
258         * out-of-buffers or other phenomenons.
259         */
260        int send_cnt_min;       /* Minimum number of packets in TX SEND Q */
261        int send_cnt_max;       /* Maximum number of packets in TX SEND Q */
262        int tx_sched_cnt_min;   /* Minimum number of packets in TX SCHED Q */
263        int tx_sched_cnt_max;   /* Maximum number of packets in TX SCHED Q */
264        int sent_cnt_max;       /* Maximum number of packets in TX SENT Q */
265        int tx_work_cnt;        /* Times the work thread processed TX BDs */
266        int tx_work_enabled;    /* No. RX BDs enabled by work thread */
267
268        int ready_cnt_min;      /* Minimum number of packets in RX READY Q */
269        int ready_cnt_max;      /* Maximum number of packets in RX READY Q */
270        int rx_sched_cnt_min;   /* Minimum number of packets in RX SCHED Q */
271        int rx_sched_cnt_max;   /* Maximum number of packets in RX SCHED Q */
272        int recv_cnt_max;       /* Maximum number of packets in RX RECV Q */
273        int rx_work_cnt;        /* Times the work thread processed RX BDs */
274        int rx_work_enabled;    /* No. RX BDs enabled by work thread */
275};
276
277extern void grspw_initialize_user(
278        /* Callback every time a GRSPW device is found. Args: DeviceIndex */
279        void *(*devfound)(int),
280        /* Callback every time a GRSPW device is removed. Args:
281         * int   = DeviceIndex
282         * void* = Return Value from devfound()
283         */
284        void (*devremove)(int,void*)
285        );
286extern int grspw_dev_count(void);
287extern void *grspw_open(int dev_no);
288extern void grspw_close(void *d);
289extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw);
290extern void grspw_stats_read(void *d, struct grspw_core_stats *sts);
291extern void grspw_stats_clr(void *d);
292
293/* Set and Read current node address configuration. The dma_nacfg[N] field
294 * represents the configuration for DMA Channel N.
295 *
296 * Set cfg->promiscous to -1 in order to only read current configuration.
297 */
298extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg);
299
300/*** Link Control interface ***/
301/* Read Link State */
302extern spw_link_state_t grspw_link_state(void *d);
303/* options [in/out]: set to -1 to only read current config
304 *
305 * CLKDIV register contain:
306 *  bits 7..0  : Clock Div RUN (only run-state)
307 *  bits 15..8 : Clock Div During Startup (all link states except run-state)
308 */
309extern void grspw_link_ctrl(void *d, int *options, int *clkdiv);
310/* Read the current value of the status register */
311extern unsigned int grspw_status(void *d);
312
313/*** Time Code Interface ***/
314/* Generate Tick-In (increment Time Counter, Send Time Code) */
315extern void grspw_tc_tx(void *d);
316/* Control Timcode settings of core */
317extern void grspw_tc_ctrl(void *d, int *options);
318/* Assign ISR Function to TimeCode RX IRQ */
319extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data);
320/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value
321 * TCTRL   = bits 7 and 6
322 * TIMECNT = bits 5 to 0
323 */
324extern void grspw_tc_time(void *d, int *time);
325
326/*** Interrupt-code Interface ***/
327struct spwpkt_ic_config {
328        unsigned int tomask;
329        unsigned int aamask;
330        unsigned int scaler;
331        unsigned int isr_reload;
332        unsigned int ack_reload;
333};
334/* Function Interrupt-Code ISR callback prototype. Called when respective
335 * interrupt handling option has been enabled by grspw_ic_ctrl(), the
336 * arguments rxirq, rxack and intto are read from the registers of the
337 * GRSPW core read by the GRSPW ISR, they are individually valid only when
338 * repective handling been turned on.
339 *
340 * data    - Custom data provided by user
341 * rxirq   - Interrupt-Code Recevie register of the GRSPW core read by ISR
342 *           (only defined if IQ bit enabled through grspw_ic_ctrl())
343 * rxack   - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR
344 *           (only defined if AQ bit enabled through grspw_ic_ctrl())
345 * intto   - Interrupt Tick-out Recevie register of the GRSPW core read by ISR
346 *           (only defined if TQ bit enabled through grspw_ic_ctrl())
347 */
348typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq,
349                                unsigned int rxack, unsigned int intto);
350/* Control Interrupt-code settings of core
351 * Write if 'options' not pointing to -1, always read current value
352 */
353extern void grspw_ic_ctrl(void *d, unsigned int *options);
354/* Write (rw&1 == 1) configuration parameters to registers and/or,
355 * Read  (rw&2 == 1) configuration parameters from registers, in that sequence.
356 */
357extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg);
358/* Read or Write Interrupt-code status registers.
359 * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write.
360 * If *ptr is NULL no operation.
361 */
362extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack,
363                        unsigned int *intto);
364/* Generate Tick-In for the given Interrupt-code
365 * Returns zero on success and non-zero on failure
366 *
367 * Interrupt code bits (ic):
368 * Bit 5 - ACK if 1
369 * Bits 4-0 Interrupt-code number
370 */
371extern int grspw_ic_tickin(void *d, int ic);
372/* Assign handler function to Interrupt-code timeout IRQ */
373extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data);
374
375/*** RMAP Control Interface ***/
376/* Set (not -1) and/or read RMAP options. */
377extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey);
378extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc);
379
380/*** SpW Port Control Interface ***/
381
382/* Select port, if
383 * -1=The current selected port is returned
384 * 0=Port 0
385 * 1=Port 1
386 * Other positive values=Both Port0 and Port1
387 */
388extern int grspw_port_ctrl(void *d, int *port);
389/* Returns Number ports available in hardware */
390extern int grspw_port_count(void *d);
391/* Returns the current active port */
392extern int grspw_port_active(void *d);
393
394/*** DMA Interface ***/
395extern void *grspw_dma_open(void *d, int chan_no);
396extern void grspw_dma_close(void *c);
397
398extern int grspw_dma_start(void *c);
399extern void grspw_dma_stop(void *c);
400
401/* Schedule List of packets for transmission at some point in
402 * future.
403 *
404 * 1. Move transmitted packets to SENT List (SCHED->SENT)
405 * 2. Add the requested packets to the SEND List (USER->SEND)
406 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
407 *
408 * Call this function with pkts=NULL to just do step 1 and 3. This may be
409 * required in Polling-mode.
410 *
411 * The above steps 1 and 3 may be skipped by setting 'opts':
412 *  bit0 = 1: Skip Step 1.
413 *  bit1 = 1: Skip Step 3.
414 * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then
415 * the work queue will be totaly responsible for handling descriptors.
416 *
417 * The fastest solution in retreiving sent TX packets and sending new frames
418 * is to call:
419 *  A. grspw_dma_tx_reclaim(opts=0)
420 *  B. grspw_dma_tx_send(opts=1)
421 *
422 * NOTE: the TXPKT_FLAG_TX flag must not be set.
423 *
424 * Return Code
425 *  -1   Error
426 *  0    Successfully added pkts to send/sched list
427 *  1    DMA stopped. No operation.
428 */
429extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count);
430
431/* Reclaim TX packet buffers that has previously been scheduled for transmission
432 * with grspw_dma_tx_send().
433 *
434 * 1. Move transmitted packets to SENT List (SCHED->SENT)
435 * 2. Move all SENT List to pkts list (SENT->USER)
436 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
437 *
438 * The above steps 1 may be skipped by setting 'opts':
439 *  bit0 = 1: Skip Step 1.
440 *  bit1 = 1: Skip Step 3.
441 *
442 * The fastest solution in retreiving sent TX packets and sending new frames
443 * is to call:
444 *  A. grspw_dma_tx_reclaim(opts=2) (Skip step 3)
445 *  B. grspw_dma_tx_send(opts=1) (Skip step 1)
446 *
447 * Return Code
448 *  -1   Error
449 *  0    Successful. pkts list filled with all packets from sent list
450 *  1    Same as 0, but indicates that DMA stopped
451 */
452extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count);
453
454/* Get current number of Packets in respective TX Queue. */
455extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent);
456
457#define GRSPW_OP_AND 0
458#define GRSPW_OP_OR 1
459/* Block until ready_cnt or fewer packets are Queued in "Send and Scheduled" Q,
460 * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition
461 * is met.
462 * If a link error occurs and the Stop on Link error is defined, this function
463 * will also return to caller.
464 * The timeout argument is used to return after timeout ticks, regardless of
465 * the other conditions. If timeout is zero, the function will wait forever
466 * until the condition is satisfied.
467 *
468 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
469 *       checked, this may hang infinitely unless a timeout has been specified
470 *
471 * Return Code
472 *  -1   Error
473 *  0    Returing to caller because specified conditions are now fullfilled
474 *  1    DMA stopped
475 *  2    Timeout, conditions are not met
476 */
477extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout);
478
479/* Get received RX packet buffers that has previously been scheduled for
480 * reception with grspw_dma_rx_prepare().
481 *
482 * 1. Move Scheduled packets to RECV List (SCHED->RECV)
483 * 2. Move all RECV packet to the callers list (RECV->USER)
484 * 3. Schedule as many free packet buffers as possible (READY->SCHED)
485 *
486 * The above steps 1 may be skipped by setting 'opts':
487 *  bit0 = 1: Skip Step 1.
488 *  bit1 = 1: Skip Step 3.
489 *
490 * The fastest solution in retreiving received RX packets and preparing new
491 * packet buffers for future receive, is to call:
492 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
493 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
494 *
495 * Return Code
496 *  -1   Error
497 *  0    Successfully filled pkts list with packets from recv list.
498 *  1    DMA stopped
499 */
500extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count);
501
502/* Add more RX packet buffers for future for reception. The received packets
503 * can later be read out with grspw_dma_rx_recv().
504 *
505 * 1. Move Received packets to RECV List (SCHED->RECV)
506 * 2. Add the "free/ready" packet buffers to the READY List (USER->READY)
507 * 3. Schedule as many packets as possible (READY->SCHED)
508 *
509 * The above steps 1 may be skipped by setting 'opts':
510 *  bit0 = 1: Skip Step 1.
511 *  bit1 = 1: Skip Step 3.
512 *
513 * The fastest solution in retreiving received RX packets and preparing new
514 * packet buffers for future receive, is to call:
515 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
516 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
517 *
518 * Return Code
519 *  -1   Error
520 *  0    Successfully added packet buffers from pkt list into the ready queue
521 *  1    DMA stopped
522 */
523extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count);
524
525/* Get current number of Packets in respective RX Queue. */
526extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv);
527
528/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR),
529 * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q,
530 * condition is met.
531 * If a link error occurs and the Stop on Link error is defined, this function
532 * will also return to caller, however with an error.
533 * The timeout argument is used to return after timeout ticks, regardless of
534 * the other conditions. If timeout is zero, the function will wait forever
535 * until the condition is satisfied.
536 *
537 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
538 *       checked, this may hang infinitely unless a timeout has been specified
539 *
540 * Return Code
541 *  -1   Error
542 *  0    Returing to caller because specified conditions are now fullfilled
543 *  1    DMA stopped
544 *  2    Timeout, conditions are not met
545 */
546extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout);
547
548extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg);
549extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg);
550
551extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts);
552extern void grspw_dma_stats_clr(void *c);
553
554/*** GRSPW SpaceWire Packet List Handling Routines ***/
555
556static inline void grspw_list_clr(struct grspw_list *list)
557{
558        list->head = NULL;
559        list->tail = NULL;
560}
561
562static inline int grspw_list_is_empty(struct grspw_list *list)
563{
564        return (list->head == NULL);
565}
566
567/* Return Number of entries in list */
568static inline int grspw_list_cnt(struct grspw_list *list)
569{
570        struct grspw_pkt *lastpkt = NULL, *pkt = list->head;
571        int cnt = 0;
572        while ( pkt ) {
573                cnt++;
574                lastpkt = pkt;
575                pkt = pkt->next;
576        }
577        if ( lastpkt && (list->tail != lastpkt) )
578                return -1;
579        return cnt;
580}
581
582static inline void
583grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt)
584{
585        pkt->next = NULL;
586        if ( list->tail == NULL ) {
587                list->head = pkt;
588        } else {
589                list->tail->next = pkt;
590        }
591        list->tail = pkt;
592}
593
594static inline void
595grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt)
596{
597        pkt->next = list->head;
598        if ( list->head == NULL ) {
599                list->tail = pkt;
600        }
601        list->head = pkt;
602}
603
604static inline void
605grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist)
606{
607        alist->tail->next = NULL;
608        if ( list->tail == NULL ) {
609                list->head = alist->head;
610        } else {
611                list->tail->next = alist->head;
612        }
613        list->tail = alist->tail;
614}
615
616static inline void
617grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist)
618{
619        if ( list->head == NULL ) {
620                list->tail = alist->tail;
621                alist->tail->next = NULL;
622        } else {
623                alist->tail->next = list->head;
624        }
625        list->head = alist->head;
626}
627
628/* Remove dlist (delete-list) from head of list */
629static inline void
630grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist)
631{
632        list->head = dlist->tail->next;
633        if ( list->head == NULL ) {
634                list->tail = NULL;
635        }
636        dlist->tail->next = NULL;
637}
638
639/* Take A number of entries from head of list 'list' and put the entires
640 * to rlist (result list).
641 */
642static inline int
643grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max)
644{
645        int cnt;
646        struct grspw_pkt *pkt, *last;
647
648        pkt = list->head;
649
650        if ( (max < 1) || (pkt == NULL) ) {
651                grspw_list_clr(rlist);
652                return 0;
653        }
654
655        cnt = 0;
656        rlist->head = pkt;
657        last = pkt;
658        while ((cnt < max) && pkt) {
659                last = pkt;
660                pkt = pkt->next;
661                cnt++;
662        }
663        rlist->tail = last;
664        grspw_list_remove_head_list(list, rlist);
665        return cnt;
666}
667
668#endif
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