source: rtems/c/src/lib/libbsp/sparc/shared/include/grspw_pkt.h @ 49cf776e

5
Last change on this file since 49cf776e was 49cf776e, checked in by Daniel Hellstrom <daniel@…>, on 03/22/16 at 14:37:36

leon, grspw_pkt: added link_ctrl options

Improved the link error handling options. Its now possible to
disable the link on individual link errors/warnings instead of
always on all or none.

Changed name of LINKOPTS_IRQ to LINKOPTS_EIRQ to match Linux
and VxWorks? SpW driver.

  • Property mode set to 100644
File size: 22.7 KB
Line 
1/*
2 *  GRSPW/GRSPW2 SpaceWire Kernel Library Interface
3 *
4 *  COPYRIGHT (c) 2011
5 *  Cobham Gaisler AB
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11
12#ifndef __GRSPW_PKT_H__
13#define __GRSPW_PKT_H__
14
15struct grspw_pkt;
16
17/* Maximum number of GRSPW devices supported by driver */
18#define GRSPW_MAX 32
19
20/* Weak overridable variable the user can use to define the worker-task
21 * priority (0..255) or to disable (-1) the creation of the worker-task
22 * and the message queue to save space */
23extern int grspw_work_task_priority;
24
25#ifndef GRSPW_PKT_FLAGS
26#define GRSPW_PKT_FLAGS
27/*** TX Packet flags ***/
28
29/* Enable IRQ generation */
30#define TXPKT_FLAG_IE 0x0040
31
32/* Enable Header CRC generation (if CRC is available in HW)
33 * Header CRC will be appended (one byte at end of header)
34 */
35#define TXPKT_FLAG_HCRC 0x0100
36
37/* Enable Data CRC generation (if CRC is available in HW)
38 * Data CRC will be appended (one byte at end of packet)
39 */
40#define TXPKT_FLAG_DCRC 0x0200
41
42/* Control how many bytes the beginning of the Header
43 * the CRC should not be calculated for */
44#define TXPKT_FLAG_NOCRC_MASK 0x0000000f
45#define TXPKT_FLAG_NOCRC_LEN0 0x00000000
46#define TXPKT_FLAG_NOCRC_LEN1 0x00000001
47#define TXPKT_FLAG_NOCRC_LEN2 0x00000002
48#define TXPKT_FLAG_NOCRC_LEN3 0x00000003
49#define TXPKT_FLAG_NOCRC_LEN4 0x00000004
50#define TXPKT_FLAG_NOCRC_LEN5 0x00000005
51#define TXPKT_FLAG_NOCRC_LEN6 0x00000006
52#define TXPKT_FLAG_NOCRC_LEN7 0x00000007
53#define TXPKT_FLAG_NOCRC_LEN8 0x00000008
54#define TXPKT_FLAG_NOCRC_LEN9 0x00000009
55#define TXPKT_FLAG_NOCRC_LENa 0x0000000a
56#define TXPKT_FLAG_NOCRC_LENb 0x0000000b
57#define TXPKT_FLAG_NOCRC_LENc 0x0000000c
58#define TXPKT_FLAG_NOCRC_LENd 0x0000000d
59#define TXPKT_FLAG_NOCRC_LENe 0x0000000e
60#define TXPKT_FLAG_NOCRC_LENf 0x0000000f
61
62#define TXPKT_FLAG_INPUT_MASK (TXPKT_FLAG_NOCRC_MASK | TXPKT_FLAG_IE | \
63                                TXPKT_FLAG_HCRC | TXPKT_FLAG_DCRC)
64
65/* Marks if packet was transmitted or not */
66#define TXPKT_FLAG_TX 0x4000
67
68/* Link Error */
69#define TXPKT_FLAG_LINKERR 0x8000
70
71#define TXPKT_FLAG_OUTPUT_MASK (TXPKT_FLAG_TX | TXPKT_FLAG_LINKERR)
72
73/*** RX Packet Flags ***/
74
75/* Enable IRQ generation */
76#define RXPKT_FLAG_IE 0x0010
77
78#define RXPKT_FLAG_INPUT_MASK (RXPKT_FLAG_IE)
79
80/* Packet was truncated */
81#define RXPKT_FLAG_TRUNK 0x0800
82/* Data CRC error (only valid if RMAP CRC is enabled) */
83#define RXPKT_FLAG_DCRC 0x0400
84/* Header CRC error (only valid if RMAP CRC is enabled) */
85#define RXPKT_FLAG_HCRC 0x0200
86/* Error in End-of-Packet */
87#define RXPKT_FLAG_EEOP 0x0100
88/* Marks if packet was recevied or not */
89#define RXPKT_FLAG_RX 0x8000
90
91#define RXPKT_FLAG_OUTPUT_MASK (RXPKT_FLAG_TRUNK | RXPKT_FLAG_DCRC | \
92                                RXPKT_FLAG_HCRC | RXPKT_FLAG_EEOP)
93
94/*** General packet flag options ***/
95
96/* Translate Hdr and/or Payload address */
97#define PKT_FLAG_TR_DATA 0x1000
98#define PKT_FLAG_TR_HDR 0x2000
99/* All General options */
100#define PKT_FLAG_MASK 0x3000
101
102#endif
103/* GRSPW RX/TX Packet structure.
104 *
105 * - For RX the 'hdr' and 'hlen' fields are not used, they are not written
106 *   by driver.
107 *
108 * - The 'pkt_id' field is untouched by driver, it is intended for packet
109 *   numbering or user-custom data.
110 *
111 * - The last packet in a list must have 'next' set to NULL.
112 *
113 * - data and hdr pointers are written without modification to hardware,
114 *   this means that caller must do address translation to hardware
115 *   address itself.
116 *
117 * - the 'flags' field are interpreted differently depending on transfer
118 *   type (RX/TX). See XXPKT_FLAG_* options above.
119 */
120struct grspw_pkt {
121        struct grspw_pkt *next;
122        unsigned int pkt_id;    /* User assigned ID */
123        unsigned short flags;   /* RX/TX Options */
124        unsigned char reserved; /* Reserved, must be zero */
125        unsigned char hlen;     /* Length of Header Buffer */
126        unsigned int dlen;      /* Length of Data Buffer */
127        void *data;     /* 4-byte or byte aligned depends on HW */
128        void *hdr;      /* 4-byte or byte aligned depends on HW */
129};
130
131/* GRSPW SpaceWire Packet List */
132struct grspw_list {
133        struct grspw_pkt *head;
134        struct grspw_pkt *tail;
135};
136
137/* SpaceWire Link State */
138typedef enum {
139        SPW_LS_ERRRST = 0,
140        SPW_LS_ERRWAIT = 1,
141        SPW_LS_READY = 2,
142        SPW_LS_CONNECTING = 3,
143        SPW_LS_STARTED = 4,
144        SPW_LS_RUN = 5
145} spw_link_state_t;
146
147/* Address Configuration */
148struct grspw_addr_config {
149        /* Ignore address field and put all received packets to first
150         * DMA channel.
151         */
152        int promiscuous;
153
154        /* Default Node Address and Mask */
155        unsigned char def_addr;
156        unsigned char def_mask;
157        /* DMA Channel custom Node Address and Mask */
158        struct {
159                char node_en;                   /* Enable Separate Addr */
160                unsigned char node_addr;        /* Node address */
161                unsigned char node_mask;        /* Node address mask */
162        } dma_nacfg[4];
163};
164
165/* Hardware Support in GRSPW Core */
166struct grspw_hw_sup {
167        char    rmap;           /* If RMAP in HW is available */
168        char    rmap_crc;       /* If RMAP CRC is available */
169        char    rx_unalign;     /* RX unaligned (byte boundary) access allowed*/
170        char    nports;         /* Number of Ports (1 or 2) */
171        char    ndma_chans;     /* Number of DMA Channels (1..4) */
172        char    strip_adr;      /* Hardware can strip ADR from packet data */
173        char    strip_pid;      /* Hardware can strip PID from packet data */
174        int     hw_version;     /* GRSPW Hardware Version */
175        char    reserved[2];
176        char    irq;            /* SpW Distributed Interrupt available if 1 */
177        char    irq_num;        /* Number of interrupts that can be generated */
178        char    itmr_width;     /* SpW Intr. ISR timers bit width. 0=no timer */
179};
180
181struct grspw_core_stats {
182        int irq_cnt;
183        int err_credit;
184        int err_eeop;
185        int err_addr;
186        int err_parity;
187        int err_escape;
188        int err_wsync; /* only in GRSPW1 */
189};
190
191/* grspw_link_ctrl() options */
192#define LINKOPTS_ENABLE         0x0000
193#define LINKOPTS_DISABLE        0x0001
194#define LINKOPTS_START          0x0002
195#define LINKOPTS_AUTOSTART      0x0004
196#define LINKOPTS_DIS_ONERR      0x0008  /* Disable DMA transmitter on link error
197                                         * Controls LE bit in DMACTRL register.
198                                         */
199#define LINKOPTS_DIS_ON_CE      0x0020000/* Disable Link on Credit error */
200#define LINKOPTS_DIS_ON_ER      0x0040000/* Disable Link on Escape error */
201#define LINKOPTS_DIS_ON_DE      0x0080000/* Disable Link on Disconnect error */
202#define LINKOPTS_DIS_ON_PE      0x0100000/* Disable Link on Parity error */
203#define LINKOPTS_DIS_ON_WE      0x0400000/* Disable Link on write synchonization
204                                          * error (GRSPW1 only)
205                                          */
206#define LINKOPTS_DIS_ON_EE      0x1000000/* Disable Link on Early EOP/EEP error*/
207
208/*#define LINKOPTS_TICK_OUT_IRQ 0x0100*//* Enable Tick-out IRQ */
209#define LINKOPTS_EIRQ           0x0200  /* Enable Error Link IRQ */
210
211#define LINKOPTS_MASK           0x15e020f/* All above options */
212#define LINKOPTS_MASK_DIS_ON    0x15e0000/* All disable link on error options
213                                          * On a certain error the link disable
214                                          * bit will be written and the work
215                                          * task will call dma_stop() for all
216                                          * channels.
217                                          */
218
219
220/* grspw_tc_ctrl() options */
221#define TCOPTS_EN_RXIRQ 0x0001  /* Tick-Out IRQ */
222#define TCOPTS_EN_TX    0x0004
223#define TCOPTS_EN_RX    0x0008
224
225/* grspw_ic_ctrl() options:
226 * Corresponds code duplicatingly to GRSPW_CTRL_XX_BIT defines
227 */
228#define ICOPTS_INTNUM           (0x1f << 27)
229#define ICOPTS_EN_SPWIRQ_ON_EE  (1 << 24)
230#define ICOPTS_EN_SPWIRQ_ON_IA  (1 << 23)
231#define ICOPTS_EN_PRIO          (1 << 22)
232#define ICOPTS_EN_TIMEOUTIRQ    (1 << 20)
233#define ICOPTS_EN_ACKIRQ        (1 << 19)
234#define ICOPTS_EN_TICKOUTIRQ    (1 << 18)
235#define ICOPTS_EN_RX            (1 << 17)
236#define ICOPTS_EN_TX            (1 << 16)
237#define ICOPTS_BASEIRQ          (0x1f << 8)
238#define ICOPTS_EN_FLAGFILTER    (1 << 0) /* NOTE: Not in icctrl. CTRL.bit12 */
239
240/* grspw_ic_rlisr() and grspw_ic_rlintack()  */
241#define ICRELOAD_EN             (1 << 31)
242#define ICRELOAD_MASK           0x7fffffff
243
244/* grspw_rmap_ctrl() options */
245#define RMAPOPTS_EN_RMAP        0x0001
246#define RMAPOPTS_EN_BUF         0x0002
247
248/* grspw_dma_config.flags options */
249#define DMAFLAG_NO_SPILL        0x0001  /* See HW doc DMA-CTRL NS bit */
250#define DMAFLAG_RESV1           0x0002  /* HAS NO EFFECT */
251#define DMAFLAG_STRIP_ADR       0x0004  /* See HW doc DMA-CTRL SA bit */
252#define DMAFLAG_STRIP_PID       0x0008  /* See HW doc DMA-CTRL SP bit */
253#define DMAFLAG_RESV2           0x0010  /* HAS NO EFFECT */
254#define DMAFLAG_MASK    (DMAFLAG_NO_SPILL|DMAFLAG_STRIP_ADR|DMAFLAG_STRIP_PID)
255
256struct grspw_dma_config {
257        int flags;
258
259        int rxmaxlen;           /* RX Max Packet Length */
260        int rx_irq_en_cnt;      /* Enable RX IRQ every cnt descriptors */
261        int tx_irq_en_cnt;      /* Enable TX IRQ every cnt descriptors */
262};
263
264/* Statistics per DMA channel */
265struct grspw_dma_stats {
266        /* IRQ Statistics */
267        int irq_cnt;            /* Number of DMA IRQs generated by channel */
268
269        /* Descriptor Statistics */
270        int tx_pkts;            /* Number of Transmitted packets */
271        int tx_err_link;        /* Number of Transmitted packets with Link Error*/
272        int rx_pkts;            /* Number of Received packets */
273        int rx_err_trunk;       /* Number of Received Truncated packets */
274        int rx_err_endpkt;      /* Number of Received packets with bad ending */
275
276        /* Diagnostics to help developers sizing their number buffers to avoid
277         * out-of-buffers or other phenomenons.
278         */
279        int send_cnt_min;       /* Minimum number of packets in TX SEND Q */
280        int send_cnt_max;       /* Maximum number of packets in TX SEND Q */
281        int tx_sched_cnt_min;   /* Minimum number of packets in TX SCHED Q */
282        int tx_sched_cnt_max;   /* Maximum number of packets in TX SCHED Q */
283        int sent_cnt_max;       /* Maximum number of packets in TX SENT Q */
284        int tx_work_cnt;        /* Times the work thread processed TX BDs */
285        int tx_work_enabled;    /* No. RX BDs enabled by work thread */
286
287        int ready_cnt_min;      /* Minimum number of packets in RX READY Q */
288        int ready_cnt_max;      /* Maximum number of packets in RX READY Q */
289        int rx_sched_cnt_min;   /* Minimum number of packets in RX SCHED Q */
290        int rx_sched_cnt_max;   /* Maximum number of packets in RX SCHED Q */
291        int recv_cnt_max;       /* Maximum number of packets in RX RECV Q */
292        int rx_work_cnt;        /* Times the work thread processed RX BDs */
293        int rx_work_enabled;    /* No. RX BDs enabled by work thread */
294};
295
296extern void grspw_initialize_user(
297        /* Callback every time a GRSPW device is found. Args: DeviceIndex */
298        void *(*devfound)(int),
299        /* Callback every time a GRSPW device is removed. Args:
300         * int   = DeviceIndex
301         * void* = Return Value from devfound()
302         */
303        void (*devremove)(int,void*)
304        );
305extern int grspw_dev_count(void);
306extern void *grspw_open(int dev_no);
307extern void grspw_close(void *d);
308extern void grspw_hw_support(void *d, struct grspw_hw_sup *hw);
309extern void grspw_stats_read(void *d, struct grspw_core_stats *sts);
310extern void grspw_stats_clr(void *d);
311
312/* Set and Read current node address configuration. The dma_nacfg[N] field
313 * represents the configuration for DMA Channel N.
314 *
315 * Set cfg->promiscous to -1 in order to only read current configuration.
316 */
317extern void grspw_addr_ctrl(void *d, struct grspw_addr_config *cfg);
318
319/*** Link Control interface ***/
320/* Read Link State */
321extern spw_link_state_t grspw_link_state(void *d);
322/* options [in/out]: set to -1 to only read current config
323 *
324 * CLKDIV register contain:
325 *  bits 7..0  : Clock Div RUN (only run-state)
326 *  bits 15..8 : Clock Div During Startup (all link states except run-state)
327 */
328extern void grspw_link_ctrl(void *d, int *options, int *clkdiv);
329/* Read the current value of the status register */
330extern unsigned int grspw_link_status(void *d);
331/* Clear bits in the status register */
332extern void grspw_link_status_clr(void *d, unsigned int clearmask);
333
334/*** Time Code Interface ***/
335/* Generate Tick-In (increment Time Counter, Send Time Code) */
336extern void grspw_tc_tx(void *d);
337/* Control Timcode settings of core */
338extern void grspw_tc_ctrl(void *d, int *options);
339/* Assign ISR Function to TimeCode RX IRQ */
340extern void grspw_tc_isr(void *d, void (*tcisr)(void *data, int tc), void *data);
341/* Read/Write TCTRL and TIMECNT. Write if not -1, always read current value
342 * TCTRL   = bits 7 and 6
343 * TIMECNT = bits 5 to 0
344 */
345extern void grspw_tc_time(void *d, int *time);
346
347/*** Interrupt-code Interface ***/
348struct spwpkt_ic_config {
349        unsigned int tomask;
350        unsigned int aamask;
351        unsigned int scaler;
352        unsigned int isr_reload;
353        unsigned int ack_reload;
354};
355/* Function Interrupt-Code ISR callback prototype. Called when respective
356 * interrupt handling option has been enabled by grspw_ic_ctrl(), the
357 * arguments rxirq, rxack and intto are read from the registers of the
358 * GRSPW core read by the GRSPW ISR, they are individually valid only when
359 * repective handling been turned on.
360 *
361 * data    - Custom data provided by user
362 * rxirq   - Interrupt-Code Recevie register of the GRSPW core read by ISR
363 *           (only defined if IQ bit enabled through grspw_ic_ctrl())
364 * rxack   - Interrupt-Ack-Code Recevie register of the GRSPW core read by ISR
365 *           (only defined if AQ bit enabled through grspw_ic_ctrl())
366 * intto   - Interrupt Tick-out Recevie register of the GRSPW core read by ISR
367 *           (only defined if TQ bit enabled through grspw_ic_ctrl())
368 */
369typedef void (*spwpkt_ic_isr_t)(void *data, unsigned int rxirq,
370                                unsigned int rxack, unsigned int intto);
371/* Control Interrupt-code settings of core
372 * Write if 'options' not pointing to -1, always read current value
373 */
374extern void grspw_ic_ctrl(void *d, unsigned int *options);
375/* Write (rw&1 == 1) configuration parameters to registers and/or,
376 * Read  (rw&2 == 1) configuration parameters from registers, in that sequence.
377 */
378extern void grspw_ic_config(void *d, int rw, struct spwpkt_ic_config *cfg);
379/* Read or Write Interrupt-code status registers.
380 * If pointer argument *ptr == 0 then only read, if *ptr != 0 then only write.
381 * If *ptr is NULL no operation.
382 */
383extern void grspw_ic_sts(void *d, unsigned int *rxirq, unsigned int *rxack,
384                        unsigned int *intto);
385/* Generate Tick-In for the given Interrupt-code
386 * Returns zero on success and non-zero on failure
387 *
388 * Interrupt code bits (ic):
389 * Bit 5 - ACK if 1
390 * Bits 4-0 Interrupt-code number
391 */
392extern int grspw_ic_tickin(void *d, int ic);
393/* Assign handler function to Interrupt-code timeout IRQ */
394extern void grspw_ic_isr(void *d, spwpkt_ic_isr_t handler, void *data);
395
396/*** RMAP Control Interface ***/
397/* Set (not -1) and/or read RMAP options. */
398extern int grspw_rmap_ctrl(void *d, int *options, int *dstkey);
399extern void grspw_rmap_support(void *d, char *rmap, char *rmap_crc);
400
401/*** SpW Port Control Interface ***/
402
403/* Select port, if
404 * -1=The current selected port is returned
405 * 0=Port 0
406 * 1=Port 1
407 * Other positive values=Both Port0 and Port1
408 */
409extern int grspw_port_ctrl(void *d, int *port);
410/* Returns Number ports available in hardware */
411extern int grspw_port_count(void *d);
412/* Returns the current active port */
413extern int grspw_port_active(void *d);
414
415/*** DMA Interface ***/
416extern void *grspw_dma_open(void *d, int chan_no);
417extern void grspw_dma_close(void *c);
418
419extern int grspw_dma_start(void *c);
420extern void grspw_dma_stop(void *c);
421
422/* Schedule List of packets for transmission at some point in
423 * future.
424 *
425 * 1. Move transmitted packets to SENT List (SCHED->SENT)
426 * 2. Add the requested packets to the SEND List (USER->SEND)
427 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
428 *
429 * Call this function with pkts=NULL to just do step 1 and 3. This may be
430 * required in Polling-mode.
431 *
432 * The above steps 1 and 3 may be skipped by setting 'opts':
433 *  bit0 = 1: Skip Step 1.
434 *  bit1 = 1: Skip Step 3.
435 * Skipping both step 1 and 3 may be usefull when IRQ is enabled, then
436 * the work queue will be totaly responsible for handling descriptors.
437 *
438 * The fastest solution in retreiving sent TX packets and sending new frames
439 * is to call:
440 *  A. grspw_dma_tx_reclaim(opts=0)
441 *  B. grspw_dma_tx_send(opts=1)
442 *
443 * NOTE: the TXPKT_FLAG_TX flag must not be set.
444 *
445 * Return Code
446 *  -1   Error
447 *  0    Successfully added pkts to send/sched list
448 *  1    DMA stopped. No operation.
449 */
450extern int grspw_dma_tx_send(void *c, int opts, struct grspw_list *pkts, int count);
451
452/* Reclaim TX packet buffers that has previously been scheduled for transmission
453 * with grspw_dma_tx_send().
454 *
455 * 1. Move transmitted packets to SENT List (SCHED->SENT)
456 * 2. Move all SENT List to pkts list (SENT->USER)
457 * 3. Schedule as many packets as possible for transmission (SEND->SCHED)
458 *
459 * The above steps 1 may be skipped by setting 'opts':
460 *  bit0 = 1: Skip Step 1.
461 *  bit1 = 1: Skip Step 3.
462 *
463 * The fastest solution in retreiving sent TX packets and sending new frames
464 * is to call:
465 *  A. grspw_dma_tx_reclaim(opts=2) (Skip step 3)
466 *  B. grspw_dma_tx_send(opts=1) (Skip step 1)
467 *
468 * Return Code
469 *  -1   Error
470 *  0    Successful. pkts list filled with all packets from sent list
471 *  1    Same as 0, but indicates that DMA stopped
472 */
473extern int grspw_dma_tx_reclaim(void *c, int opts, struct grspw_list *pkts, int *count);
474
475/* Get current number of Packets in respective TX Queue. */
476extern void grspw_dma_tx_count(void *c, int *send, int *sched, int *sent);
477
478#define GRSPW_OP_AND 0
479#define GRSPW_OP_OR 1
480/* Block until ready_cnt or fewer packets are Queued in "Send and Scheduled" Q,
481 * op (AND or OR), sent_cnt or more packet "have been sent" (Sent Q) condition
482 * is met.
483 * If a link error occurs and the Stop on Link error is defined, this function
484 * will also return to caller.
485 * The timeout argument is used to return after timeout ticks, regardless of
486 * the other conditions. If timeout is zero, the function will wait forever
487 * until the condition is satisfied.
488 *
489 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
490 *       checked, this may hang infinitely unless a timeout has been specified
491 *
492 * Return Code
493 *  -1   Error
494 *  0    Returing to caller because specified conditions are now fullfilled
495 *  1    DMA stopped
496 *  2    Timeout, conditions are not met
497 */
498extern int grspw_dma_tx_wait(void *c, int send_cnt, int op, int sent_cnt, int timeout);
499
500/* Get received RX packet buffers that has previously been scheduled for
501 * reception with grspw_dma_rx_prepare().
502 *
503 * 1. Move Scheduled packets to RECV List (SCHED->RECV)
504 * 2. Move all RECV packet to the callers list (RECV->USER)
505 * 3. Schedule as many free packet buffers as possible (READY->SCHED)
506 *
507 * The above steps 1 may be skipped by setting 'opts':
508 *  bit0 = 1: Skip Step 1.
509 *  bit1 = 1: Skip Step 3.
510 *
511 * The fastest solution in retreiving received RX packets and preparing new
512 * packet buffers for future receive, is to call:
513 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
514 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
515 *
516 * Return Code
517 *  -1   Error
518 *  0    Successfully filled pkts list with packets from recv list.
519 *  1    DMA stopped
520 */
521extern int grspw_dma_rx_recv(void *c, int opts, struct grspw_list *pkts, int *count);
522
523/* Add more RX packet buffers for future for reception. The received packets
524 * can later be read out with grspw_dma_rx_recv().
525 *
526 * 1. Move Received packets to RECV List (SCHED->RECV)
527 * 2. Add the "free/ready" packet buffers to the READY List (USER->READY)
528 * 3. Schedule as many packets as possible (READY->SCHED)
529 *
530 * The above steps 1 may be skipped by setting 'opts':
531 *  bit0 = 1: Skip Step 1.
532 *  bit1 = 1: Skip Step 3.
533 *
534 * The fastest solution in retreiving received RX packets and preparing new
535 * packet buffers for future receive, is to call:
536 *  A. grspw_dma_rx_recv(opts=2, &recvlist) (Skip step 3)
537 *  B. grspw_dma_rx_prepare(opts=1, &freelist) (Skip step 1)
538 *
539 * Return Code
540 *  -1   Error
541 *  0    Successfully added packet buffers from pkt list into the ready queue
542 *  1    DMA stopped
543 */
544extern int grspw_dma_rx_prepare(void *c, int opts, struct grspw_list *pkts, int count);
545
546/* Get current number of Packets in respective RX Queue. */
547extern void grspw_dma_rx_count(void *c, int *ready, int *sched, int *recv);
548
549/* Block until recv_cnt or more packets are Queued in RECV Q, op (AND or OR),
550 * ready_cnt or fewer packet buffers are available in the "READY and Scheduled" Q,
551 * condition is met.
552 * If a link error occurs and the Stop on Link error is defined, this function
553 * will also return to caller, however with an error.
554 * The timeout argument is used to return after timeout ticks, regardless of
555 * the other conditions. If timeout is zero, the function will wait forever
556 * until the condition is satisfied.
557 *
558 * NOTE: if IRQ of TX descriptors are not enabled conditions are never
559 *       checked, this may hang infinitely unless a timeout has been specified
560 *
561 * Return Code
562 *  -1   Error
563 *  0    Returing to caller because specified conditions are now fullfilled
564 *  1    DMA stopped
565 *  2    Timeout, conditions are not met
566 */
567extern int grspw_dma_rx_wait(void *c, int recv_cnt, int op, int ready_cnt, int timeout);
568
569extern int grspw_dma_config(void *c, struct grspw_dma_config *cfg);
570extern void grspw_dma_config_read(void *c, struct grspw_dma_config *cfg);
571
572extern void grspw_dma_stats_read(void *c, struct grspw_dma_stats *sts);
573extern void grspw_dma_stats_clr(void *c);
574
575/* Register GRSPW packet driver to Driver Manager */
576void grspw2_register_drv (void);
577
578/*** GRSPW SpaceWire Packet List Handling Routines ***/
579
580static inline void grspw_list_clr(struct grspw_list *list)
581{
582        list->head = NULL;
583        list->tail = NULL;
584}
585
586static inline int grspw_list_is_empty(struct grspw_list *list)
587{
588        return (list->head == NULL);
589}
590
591/* Return Number of entries in list */
592static inline int grspw_list_cnt(struct grspw_list *list)
593{
594        struct grspw_pkt *lastpkt = NULL, *pkt = list->head;
595        int cnt = 0;
596        while ( pkt ) {
597                cnt++;
598                lastpkt = pkt;
599                pkt = pkt->next;
600        }
601        if ( lastpkt && (list->tail != lastpkt) )
602                return -1;
603        return cnt;
604}
605
606static inline void
607grspw_list_append(struct grspw_list *list, struct grspw_pkt *pkt)
608{
609        pkt->next = NULL;
610        if ( list->tail == NULL ) {
611                list->head = pkt;
612        } else {
613                list->tail->next = pkt;
614        }
615        list->tail = pkt;
616}
617
618static inline void
619grspw_list_prepend(struct grspw_list *list, struct grspw_pkt *pkt)
620{
621        pkt->next = list->head;
622        if ( list->head == NULL ) {
623                list->tail = pkt;
624        }
625        list->head = pkt;
626}
627
628static inline void
629grspw_list_append_list(struct grspw_list *list, struct grspw_list *alist)
630{
631        alist->tail->next = NULL;
632        if ( list->tail == NULL ) {
633                list->head = alist->head;
634        } else {
635                list->tail->next = alist->head;
636        }
637        list->tail = alist->tail;
638}
639
640static inline void
641grspw_list_prepend_list(struct grspw_list *list, struct grspw_list *alist)
642{
643        if ( list->head == NULL ) {
644                list->tail = alist->tail;
645                alist->tail->next = NULL;
646        } else {
647                alist->tail->next = list->head;
648        }
649        list->head = alist->head;
650}
651
652/* Remove dlist (delete-list) from head of list */
653static inline void
654grspw_list_remove_head_list(struct grspw_list *list, struct grspw_list *dlist)
655{
656        list->head = dlist->tail->next;
657        if ( list->head == NULL ) {
658                list->tail = NULL;
659        }
660        dlist->tail->next = NULL;
661}
662
663/* Take A number of entries from head of list 'list' and put the entires
664 * to rlist (result list).
665 */
666static inline int
667grspw_list_take_head_list(struct grspw_list *list, struct grspw_list *rlist, int max)
668{
669        int cnt;
670        struct grspw_pkt *pkt, *last;
671
672        pkt = list->head;
673
674        if ( (max < 1) || (pkt == NULL) ) {
675                grspw_list_clr(rlist);
676                return 0;
677        }
678
679        cnt = 0;
680        rlist->head = pkt;
681        last = pkt;
682        while ((cnt < max) && pkt) {
683                last = pkt;
684                pkt = pkt->next;
685                cnt++;
686        }
687        rlist->tail = last;
688        grspw_list_remove_head_list(list, rlist);
689        return cnt;
690}
691
692#endif
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