1 | /* |
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2 | * GRPWM PWM Driver interface. |
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3 | * |
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4 | * COPYRIGHT (c) 2009. |
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5 | * Cobham Gaisler AB. |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | */ |
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11 | |
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12 | #ifndef __GRPWM_H__ |
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13 | #define __GRPWM_H__ |
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14 | |
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15 | #ifdef __cplusplus |
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16 | extern "C" { |
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17 | #endif |
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18 | |
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19 | extern void grpwm_register_drv (void); |
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20 | |
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21 | #define GRPWM_IOCTL_GET_CAP 1 /* Get Capabilities */ |
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22 | #define GRPWM_IOCTL_SET_CONFIG 2 /* Configure one PWM Channel */ |
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23 | #define GRPWM_IOCTL_SET_SCALER 3 /* Set one scaler */ |
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24 | #define GRPWM_IOCTL_UPDATE 4 /* Set current period and compare value */ |
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25 | #define GRPWM_IOCTL_IRQ 5 /* Set up IRQ handling */ |
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26 | |
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27 | /*** Argument for GRPWM_IOCTL_GET_CAP ***/ |
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28 | |
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29 | /* The Capability of the PWM core */ |
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30 | struct grpwm_ioctl_cap { |
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31 | int channel_cnt; /* Number of channels */ |
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32 | unsigned int pwm; /* Capability1 register */ |
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33 | unsigned int wave; /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */ |
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34 | }; |
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35 | |
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36 | /*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/ |
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37 | |
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38 | /* Config One PWM */ |
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39 | struct grpwm_ioctl_config { |
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40 | unsigned int channel; /* Select channel to configure */ |
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41 | |
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42 | /* Specific for one PWM channel */ |
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43 | unsigned int options; /* PWM options */ |
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44 | unsigned char dbscaler; /* value greater than 15 disable Dead band */ |
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45 | unsigned char scaler_index; /* Select scaler used by PWM channel */ |
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46 | |
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47 | /* IRQ Setup */ |
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48 | unsigned char irqscaler; /* IRQ scaler */ |
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49 | void *isr_arg; /* Argument of IRQ handler */ |
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50 | void (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */ |
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51 | |
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52 | /* Waveform set up */ |
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53 | int wave_activate; /* Enables Waveform functionality */ |
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54 | unsigned int wave_synccfg; /* Bits [29,30,31] is written into Wave-Config register */ |
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55 | unsigned int wave_sync; /* Sets sync compare register */ |
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56 | unsigned int *wave_data; /* If not NULL, the Wave RAM is filled with data */ |
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57 | unsigned int wave_data_length; /* Length of Wave RAM Data, Also used for wstopaddr */ |
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58 | }; |
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59 | |
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60 | #define GRPWM_CONFIG_OPTION_FLIP 0x04000000 /* Set this to Flip PWM output pair */ |
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61 | #define GRPWM_CONFIG_OPTION_DEAD_BAND 0x00200000 /* Dead Band enable */ |
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62 | #define GRPWM_CONFIG_OPTION_SYMMETRIC 0x00000040 /* If not defined, asymmetric */ |
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63 | #define GRPWM_CONFIG_OPTION_ASYMMERTIC 0 |
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64 | #define GRPWM_CONFIG_OPTION_DUAL 0x00000020 /* Dual Compare Enable */ |
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65 | #define GRPWM_CONFIG_OPTION_PAIR 0x00000004 /* PWM Pair Enable */ |
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66 | #define GRPWM_CONFIG_OPTION_SINGLE 0x00000000 /* PWM Pair Disable */ |
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67 | #define GRPWM_CONFIG_OPTION_POLARITY_HIGH 0x00000002 /* PWM Polarity HIGH */ |
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68 | #define GRPWM_CONFIG_OPTION_POLARITY_LOW 0x00000000 /* PWM Polarity LOW */ |
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69 | |
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70 | #define GRPWM_CONFIG_OPTION_MASK ( \ |
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71 | GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \ |
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72 | GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \ |
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73 | GRPWM_CONFIG_OPTION_POLARITY_HIGH \ |
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74 | ) |
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75 | |
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76 | /*** Argument for GPPWM_IOCTL_SET_SCALER ***/ |
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77 | |
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78 | struct grpwm_ioctl_scaler { |
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79 | unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */ |
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80 | unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<<N is set */ |
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81 | }; |
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82 | |
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83 | /*** Argument for GRPWM_IOCTL_UPDATE ***/ |
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84 | |
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85 | #define GRPWM_UPDATE_OPTION_ENABLE 0x01 /* Enable the PWM core */ |
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86 | #define GRPWM_UPDATE_OPTION_DISABLE 0x02 /* Disable the PWM core */ |
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87 | #define GRPWM_UPDATE_OPTION_PERIOD 0x04 /* Update period register */ |
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88 | #define GRPWM_UPDATE_OPTION_COMP 0x08 /* Update Compare register */ |
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89 | #define GRPWM_UPDATE_OPTION_DBCOMP 0x10 /* Update Dead band register */ |
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90 | #define GRPWM_UPDATE_OPTION_FIX 0x20 /* Update fix output pins (bypass PWM) */ |
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91 | |
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92 | /* FIX PIN bit-mask */ |
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93 | #define GRPWM_UPDATE_FIX_ENABLE 1 /* Enable force ouput */ |
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94 | #define GRPWM_UPDATE_FIX_DISABLE 0 /* Disable force ouput */ |
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95 | #define GRPWM_UPDATE_FIX_0_LOW 0 /* PIN 0 OUPUT: LOW */ |
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96 | #define GRPWM_UPDATE_FIX_0_HIGH 2 /* PIN 0 OUPUT: HIGH */ |
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97 | #define GRPWM_UPDATE_FIX_1_LOW 0 /* PIN 1 OUPUT: LOW */ |
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98 | #define GRPWM_UPDATE_FIX_1_HIGH 4 /* PIN 1 OUPUT: HIGH */ |
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99 | |
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100 | struct grpwm_ioctl_update_chan { |
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101 | unsigned int options; /* Select what is updated */ |
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102 | unsigned int period; /* Period register content */ |
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103 | unsigned int compare; /* Compare register content */ |
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104 | unsigned int dbcomp; /* Dead band register content */ |
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105 | unsigned char fix; /* Bit-mask that select output on one or two PWM |
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106 | * output pins. Depends on PAIR config value. |
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107 | */ |
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108 | }; |
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109 | struct grpwm_ioctl_update { |
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110 | unsigned char chanmask; /* Bit Mask select channels */ |
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111 | struct grpwm_ioctl_update_chan channels[8]; /* */ |
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112 | }; |
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113 | |
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114 | /*** Argument for GPPWM_IOCTL_IRQ ***/ |
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115 | |
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116 | #define GRPWM_IRQ_DISABLE 0 /* Disable IRQ */ |
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117 | #define GRPWM_IRQ_PERIOD 1 /* Enable IRQ on period match */ |
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118 | #define GRPWM_IRQ_COMPARE 3 /* Enable IRQ on Compare Match */ |
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119 | #define GRPWM_IRQ_CLEAR 0x10 /* Clear any pending IRQ on GRPWM and IRQ controller */ |
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120 | |
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121 | #define GRPWM_IRQ_CHAN 0x100 /* Channel N is selected, by adding 0x100*N */ |
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122 | |
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123 | #ifdef __cplusplus |
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124 | } |
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125 | #endif |
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126 | |
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127 | #endif |
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