source: rtems/c/src/lib/libbsp/sparc/shared/include/grpwm.h @ 3bb4122

4.11
Last change on this file since 3bb4122 was 3bb4122, checked in by Daniel Hellstrom <daniel@…>, on Feb 23, 2015 at 12:02:39 PM

LEON: added new drivers to the LEON2/LEON3 BSPs

Most drivers use the Driver Manager for device probing, they
work on AMBA-over-PCI systems if PCI is big-endian.

New APIs:

  • GPIO Library, interfaced to GRGPIO
  • GENIRQ, Generic interrupt service implementation helper

New GRLIB Drivers:

  • ACTEL 1553 RT, user interface is similar to 1553 BRM driver
  • GR1553 (1553 BC, RT and BM core)
  • AHBSTAT (AHB error status core)
  • GRADCDAC (Core interfacing to ADC/DAC hardware)
  • GRGPIO (GPIO port accessed from GPIO Library)
  • MCTRL (Memory controller settings configuration)
  • GRETH (10/100/1000 Ethernet driver using Driver manager)
  • GRPWM (Pulse Width Modulation core)
  • SPICTRL (SPI master interface)
  • GRSPW_ROUTER (SpaceWire? Router AMBA configuration interface)
  • GRCTM (SpaceCraft? on-board Time Management core)
  • SPWCUC (Time distribution over SpaceWire?)
  • GRTC (SpaceCraft? up-link Tele core)
  • GRTM (SpaceCraft? down-link Tele Metry core)

GR712RC ASIC specific interfaces:

  • GRASCS
  • CANMUX (select between OCCAN and SATCAN)
  • SATCAN
  • SLINK
  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 *  GRPWM PWM Driver interface.
3 *
4 *  COPYRIGHT (c) 2009.
5 *  Cobham Gaisler AB.
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 */
11
12#ifndef __GRPWM_H__
13#define __GRPWM_H__
14
15#ifdef __cplusplus
16extern "C" {
17#endif
18
19extern void grpwm_register_drv (void);
20
21#define GRPWM_IOCTL_GET_CAP     1       /* Get Capabilities */
22#define GRPWM_IOCTL_SET_CONFIG  2       /* Configure one PWM Channel */
23#define GRPWM_IOCTL_SET_SCALER  3       /* Set one scaler */
24#define GRPWM_IOCTL_UPDATE      4       /* Set current period and compare value */
25#define GRPWM_IOCTL_IRQ         5       /* Set up IRQ handling */
26
27/*** Argument for GRPWM_IOCTL_GET_CAP ***/
28
29/* The Capability of the PWM core */
30struct grpwm_ioctl_cap {
31        int             channel_cnt;    /* Number of channels */
32        unsigned int    pwm;            /* Capability1 register */
33        unsigned int    wave;           /* Capability2 register, Wave form capabilities of last PWM channel, otherwise 0 */
34};
35
36/*** Argument for GRPWM_IOCTL_GET_CONFIG and GRPWM_IOCTL_SET_CONFIG ***/
37
38/* Config One PWM */
39struct grpwm_ioctl_config {
40        unsigned int    channel;        /* Select channel to configure */
41
42        /* Specific for one PWM channel */
43        unsigned int    options;        /* PWM options */
44        unsigned char   dbscaler;       /* value greater than 15 disable Dead band */
45        unsigned char   scaler_index;   /* Select scaler used by PWM channel */
46
47        /* IRQ Setup */
48        unsigned char   irqscaler;      /* IRQ scaler */
49        void            *isr_arg;       /* Argument of IRQ handler */
50        void            (*isr)(int channel, void *arg); /* Interrupt service routine for this PWM Channel */
51
52        /* Waveform set up */
53        int             wave_activate;          /* Enables Waveform functionality */
54        unsigned int    wave_synccfg;           /* Bits [29,30,31] is written into Wave-Config register */
55        unsigned int    wave_sync;              /* Sets sync compare register */
56        unsigned int    *wave_data;             /* If not NULL, the Wave RAM is filled with data */
57        unsigned int    wave_data_length;       /* Length of Wave RAM Data, Also used for wstopaddr */
58};
59
60#define GRPWM_CONFIG_OPTION_FLIP                0x04000000      /* Set this to Flip PWM output pair */
61#define GRPWM_CONFIG_OPTION_DEAD_BAND           0x00200000      /* Dead Band enable */
62#define GRPWM_CONFIG_OPTION_SYMMETRIC           0x00000040      /* If not defined, asymmetric */
63#define GRPWM_CONFIG_OPTION_ASYMMERTIC          0
64#define GRPWM_CONFIG_OPTION_DUAL                0x00000020      /* Dual Compare Enable */
65#define GRPWM_CONFIG_OPTION_PAIR                0x00000004      /* PWM Pair Enable */
66#define GRPWM_CONFIG_OPTION_SINGLE              0x00000000      /* PWM Pair Disable */
67#define GRPWM_CONFIG_OPTION_POLARITY_HIGH       0x00000002      /* PWM Polarity HIGH */
68#define GRPWM_CONFIG_OPTION_POLARITY_LOW        0x00000000      /* PWM Polarity LOW */
69
70#define GRPWM_CONFIG_OPTION_MASK ( \
71        GRPWM_CONFIG_OPTION_DEAD_BAND | GRPWM_CONFIG_OPTION_SYMMETRIC | \
72        GRPWM_CONFIG_OPTION_DUAL | GRPWM_CONFIG_OPTION_PAIR | \
73        GRPWM_CONFIG_OPTION_POLARITY_HIGH \
74        )
75
76/*** Argument for GPPWM_IOCTL_SET_SCALER ***/
77
78struct grpwm_ioctl_scaler {
79        unsigned int index_mask;/* Scaler update index mask, bit 0 = Scaler 0, bit 1 = Scaler 1 */
80        unsigned int values[8]; /* Scaler update values, values[N] is stored into scaler N, if mask & 1<<N is set */
81};
82
83/*** Argument for GRPWM_IOCTL_UPDATE ***/
84
85#define GRPWM_UPDATE_OPTION_ENABLE      0x01    /* Enable the PWM core */
86#define GRPWM_UPDATE_OPTION_DISABLE     0x02    /* Disable the PWM core */
87#define GRPWM_UPDATE_OPTION_PERIOD      0x04    /* Update period register */
88#define GRPWM_UPDATE_OPTION_COMP        0x08    /* Update Compare register */
89#define GRPWM_UPDATE_OPTION_DBCOMP      0x10    /* Update Dead band register */
90#define GRPWM_UPDATE_OPTION_FIX         0x20    /* Update fix output pins (bypass PWM) */
91
92/* FIX PIN bit-mask */
93#define GRPWM_UPDATE_FIX_ENABLE         1       /* Enable force ouput */
94#define GRPWM_UPDATE_FIX_DISABLE        0       /* Disable force ouput */
95#define GRPWM_UPDATE_FIX_0_LOW          0       /* PIN 0 OUPUT: LOW */
96#define GRPWM_UPDATE_FIX_0_HIGH         2       /* PIN 0 OUPUT: HIGH */
97#define GRPWM_UPDATE_FIX_1_LOW          0       /* PIN 1 OUPUT: LOW */
98#define GRPWM_UPDATE_FIX_1_HIGH         4       /* PIN 1 OUPUT: HIGH */
99
100struct grpwm_ioctl_update_chan {
101        unsigned int    options;        /* Select what is updated */
102        unsigned int    period;         /* Period register content */
103        unsigned int    compare;        /* Compare register content */
104        unsigned int    dbcomp;         /* Dead band register content */
105        unsigned char   fix;            /* Bit-mask that select output on one or two PWM
106                                         * output pins. Depends on PAIR config value.
107                                         */
108};
109struct grpwm_ioctl_update {
110        unsigned char                   chanmask; /* Bit Mask select channels */
111        struct grpwm_ioctl_update_chan  channels[8]; /*  */
112};
113
114/*** Argument for GPPWM_IOCTL_IRQ ***/
115
116#define GRPWM_IRQ_DISABLE       0       /* Disable IRQ */
117#define GRPWM_IRQ_PERIOD        1       /* Enable IRQ on period match */
118#define GRPWM_IRQ_COMPARE       3       /* Enable IRQ on Compare Match */
119#define GRPWM_IRQ_CLEAR         0x10    /* Clear any pending IRQ on GRPWM and IRQ controller */
120
121#define GRPWM_IRQ_CHAN          0x100   /* Channel N is selected, by adding 0x100*N */
122
123#ifdef __cplusplus
124}
125#endif
126
127#endif
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