1 | /* GRLIB GRPCI2 PCI HOST driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2011 |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.org/license/LICENSE. |
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9 | */ |
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10 | |
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11 | #ifndef __GRPCI2_H__ |
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12 | #define __GRPCI2_H__ |
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13 | |
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14 | #ifdef __cplusplus |
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15 | extern "C" { |
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16 | #endif |
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17 | |
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18 | extern void grpci2_register_drv(void); |
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19 | |
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20 | /* Driver Resources: |
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21 | * |
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22 | * PCI Interrupts |
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23 | * ============== |
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24 | * The interrupt settings are normally autodetected from Plyg&Play, however |
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25 | * if IRQs are routed using custom GPIO pins in order to reduce the PIN count |
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26 | * reserved for PCI, the options below can be used to tell GRPCI2 driver which |
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27 | * System IRQ a PCI interrupt is connected to. |
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28 | * Name="INTA#", Type=INT, System Interrupt number that PCI INTA is connected to |
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29 | * Name="INTB#", Type=INT, System Interrupt number that PCI INTB is connected to |
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30 | * Name="INTC#", Type=INT, System Interrupt number that PCI INTC is connected to |
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31 | * Name="INTD#", Type=INT, System Interrupt number that PCI INTD is connected to |
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32 | * |
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33 | * Name="IRQmask", Type=INT, |
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34 | * |
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35 | * PCI Bytetwisting (endianess) |
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36 | * ============================ |
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37 | * Name="byteTwisting", Type=INT, Enable/Disable Bytetwisting by hardware |
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38 | * |
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39 | * PCI Host's Target BARs setup |
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40 | * ============================ |
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41 | * The Host's BARs are not configured by the configuration routines, by default |
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42 | * the BARs are configured disabled (BAR=0) except for BAR0 which is mapped to |
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43 | * the Main Memory for the Host. |
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44 | * Name="tgtBarCfg", Type=PTR (*grpci2_pcibar_cfg), Target PCI BARs of Host |
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45 | */ |
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46 | |
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47 | /* When the Host acts as a target on the PCI bus, the PCI BARs of the host's |
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48 | * configuration space determine at which PCI address the Host will be accessed |
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49 | * at and when accessing a BAR which AMBA address it will be translated to. |
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50 | */ |
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51 | struct grpci2_pcibar_cfg { |
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52 | unsigned int pciadr; /* PCI address of BAR (BAR content) */ |
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53 | unsigned int ahbadr; /* 'pciadr' translated to this AHB Address */ |
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54 | unsigned int barsize; /* PCI BAR Size, must be a power of 2 */ |
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55 | }; |
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56 | |
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57 | #ifdef __cplusplus |
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58 | } |
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59 | #endif |
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60 | |
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61 | #endif |
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