source: rtems/c/src/lib/libbsp/sparc/shared/include/greth.h @ 4a7d1026

4.11
Last change on this file since 4a7d1026 was 4a7d1026, checked in by Daniel Hellstrom <daniel@…>, on Apr 13, 2015 at 8:25:52 AM

sparc bsps: updated license to rtems.org

  • Property mode set to 100644
File size: 5.3 KB
Line 
1/*
2 * Cobham Gaisler ethernet MAC driver
3 * adapted from Opencores driver by Marko Isomaki
4 *
5 * The license and distribution terms for this file may be
6 * found in found in the file LICENSE in this distribution or at
7 * http://www.rtems.org/license/LICENSE.
8 */
9
10#ifndef __GRETH_H__
11#define __GRETH_H__
12
13#ifdef __cplusplus
14extern "C" {
15#endif
16
17/* Ethernet configuration registers */
18
19typedef struct _greth_regs {
20   volatile uint32_t ctrl;         /* Ctrl Register */
21   volatile uint32_t status;       /* Status Register */
22   volatile uint32_t mac_addr_msb; /* Bit 47-32 of MAC address */
23   volatile uint32_t mac_addr_lsb; /* Bit 31-0 of MAC address */
24   volatile uint32_t mdio_ctrl;    /* MDIO control and status */
25   volatile uint32_t txdesc;       /* Transmit descriptor pointer */
26   volatile uint32_t rxdesc;       /* Receive descriptor pointer */
27} greth_regs;
28
29#define GRETH_TOTAL_BD           128
30#define GRETH_MAXBUF_LEN         1520
31                               
32/* Tx BD */                     
33#define GRETH_TXD_ENABLE      0x0800 /* Tx BD Enable */
34#define GRETH_TXD_WRAP        0x1000 /* Tx BD Wrap (last BD) */
35#define GRETH_TXD_IRQ         0x2000 /* Tx BD IRQ Enable */
36#define GRETH_TXD_MORE        0x20000 /* Tx BD More (more descs for packet) */
37#define GRETH_TXD_IPCS        0x40000 /* Tx BD insert ip chksum */
38#define GRETH_TXD_TCPCS       0x80000 /* Tx BD insert tcp chksum */
39#define GRETH_TXD_UDPCS       0x100000 /* Tx BD insert udp chksum */
40
41#define GRETH_TXD_UNDERRUN    0x4000 /* Tx BD Underrun Status */
42#define GRETH_TXD_RETLIM      0x8000 /* Tx BD Retransmission Limit Status */
43#define GRETH_TXD_LATECOL     0x10000 /* Tx BD Late Collision */
44
45#define GRETH_TXD_STATS       (GRETH_TXD_UNDERRUN            | \
46                               GRETH_TXD_RETLIM              | \
47                               GRETH_TXD_LATECOL)
48
49#define GRETH_TXD_CS          (GRETH_TXD_IPCS            | \
50                               GRETH_TXD_TCPCS           | \
51                               GRETH_TXD_UDPCS)
52                               
53/* Rx BD */                     
54#define GRETH_RXD_ENABLE      0x0800 /* Rx BD Enable */
55#define GRETH_RXD_WRAP        0x1000 /* Rx BD Wrap (last BD) */
56#define GRETH_RXD_IRQ         0x2000 /* Rx BD IRQ Enable */
57
58#define GRETH_RXD_DRIBBLE     0x4000 /* Rx BD Dribble Nibble Status */                               
59#define GRETH_RXD_TOOLONG     0x8000 /* Rx BD Too Long Status */
60#define GRETH_RXD_CRCERR      0x10000 /* Rx BD CRC Error Status */
61#define GRETH_RXD_OVERRUN     0x20000 /* Rx BD Overrun Status */
62#define GRETH_RXD_LENERR      0x40000 /* Rx BD Length Error */
63#define GRETH_RXD_ID          0x40000 /* Rx BD IP Detected */
64#define GRETH_RXD_IR          0x40000 /* Rx BD IP Chksum Error */
65#define GRETH_RXD_UD          0x40000 /* Rx BD UDP Detected*/
66#define GRETH_RXD_UR          0x40000 /* Rx BD UDP Chksum Error */
67#define GRETH_RXD_TD          0x40000 /* Rx BD TCP Detected */
68#define GRETH_RXD_TR          0x40000 /* Rx BD TCP Chksum Error */
69
70
71#define GRETH_RXD_STATS       (GRETH_RXD_OVERRUN             | \
72                               GRETH_RXD_DRIBBLE             | \
73                               GRETH_RXD_TOOLONG             | \
74                               GRETH_RXD_CRCERR)
75
76/* CTRL Register */
77#define GRETH_CTRL_TXEN         0x00000001 /* Transmit Enable */
78#define GRETH_CTRL_RXEN         0x00000002 /* Receive Enable  */
79#define GRETH_CTRL_TXIRQ        0x00000004 /* Transmit Enable */
80#define GRETH_CTRL_RXIRQ        0x00000008 /* Receive Enable  */
81#define GRETH_CTRL_FULLD        0x00000010 /* Full Duplex */
82#define GRETH_CTRL_PRO          0x00000020 /* Promiscuous (receive all) */
83#define GRETH_CTRL_RST          0x00000040 /* Reset MAC */
84#define GRETH_CTRL_DD           0x00001000 /* Disable EDCL Duplex Detection */
85
86/* Status Register */
87#define GRETH_STATUS_RXERR      0x00000001 /* Receive Error */
88#define GRETH_STATUS_TXERR      0x00000002 /* Transmit Error IRQ */
89#define GRETH_STATUS_RXIRQ      0x00000004 /* Receive Frame IRQ */
90#define GRETH_STATUS_TXIRQ      0x00000008 /* Transmit Error IRQ */
91#define GRETH_STATUS_RXAHBERR   0x00000010 /* Receiver AHB Error */
92#define GRETH_STATUS_TXAHBERR   0x00000020 /* Transmitter AHB Error */
93
94/* MDIO Control  */
95#define GRETH_MDIO_WRITE        0x00000001 /* MDIO Write */
96#define GRETH_MDIO_READ         0x00000002 /* MDIO Read */
97#define GRETH_MDIO_LINKFAIL     0x00000004 /* MDIO Link failed */
98#define GRETH_MDIO_BUSY         0x00000008 /* MDIO Link Busy */
99#define GRETH_MDIO_REGADR       0x000007C0 /* Register Address */
100#define GRETH_MDIO_PHYADR       0x0000F800 /* PHY address */
101#define GRETH_MDIO_DATA         0xFFFF0000 /* MDIO DATA */
102
103
104/* MII registers */
105#define GRETH_MII_EXTADV_1000FD 0x00000200
106#define GRETH_MII_EXTADV_1000HD 0x00000100
107#define GRETH_MII_EXTPRT_1000FD 0x00000800
108#define GRETH_MII_EXTPRT_1000HD 0x00000400
109
110#define GRETH_MII_100T4         0x00000200
111#define GRETH_MII_100TXFD       0x00000100
112#define GRETH_MII_100TXHD       0x00000080
113#define GRETH_MII_10FD          0x00000040
114#define GRETH_MII_10HD          0x00000020
115
116
117/* Attach routine */
118
119void greth_register_drv(void);
120
121/* PHY data */
122struct phy_device_info
123{
124   int vendor;
125   int device;
126   int rev;
127   
128   int adv;
129   int part;
130
131   int extadv;
132   int extpart;
133};
134
135/*
136#ifdef CPU_U32_FIX
137void ipalign(struct mbuf *m);
138#endif
139
140*/
141#ifdef __cplusplus
142}
143#endif
144
145#endif
146
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