source: rtems/c/src/lib/libbsp/sparc/shared/include/grcan.h @ 229c4249

5
Last change on this file since 229c4249 was 3681925, checked in by Daniel Hellstrom <daniel@…>, on 12/20/11 at 15:27:54

LEON: updated shared drivers to Driver Manger framework

Some bugfixes at the same time. After this patch the drivers
may be used on RASTA systems having a big-endian PCI layout.

Removed not up to date changelogs, rely on git log instead.
  • Property mode set to 100644
File size: 6.3 KB
Line 
1/**
2 * @file
3 * @ingroup sparc_bsp
4 * @defgroup can GRCAN
5 * @ingroup can
6 * @brief Macros used for grcan controller
7 */
8
9/*
10 *  COPYRIGHT (c) 2007.
11 *  Cobham Gaisler AB.
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 */
17
18#ifndef __GRCAN_H__
19#define __GRCAN_H__
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25struct grcan_regs {
26    volatile unsigned int conf;          /* 0x00 */
27    volatile unsigned int stat;          /* 0x04 */
28    volatile unsigned int ctrl;          /* 0x08 */
29    volatile unsigned int dummy0[3];     /* 0x0C-0x014 */
30    volatile unsigned int smask;         /* 0x18 */
31    volatile unsigned int scode;         /* 0x1C */
32
33    volatile unsigned int dummy1[56];    /* 0x20-0xFC */
34
35    volatile unsigned int pimsr;         /* 0x100 */
36    volatile unsigned int pimr;          /* 0x104 */
37    volatile unsigned int pisr;          /* 0x108 */
38    volatile unsigned int pir;           /* 0x10C */
39    volatile unsigned int imr;           /* 0x110 */
40    volatile unsigned int picr;          /* 0x114 */
41
42    volatile unsigned int dummy2[58];    /* 0x118-0x1FC */
43
44    volatile unsigned int tx0ctrl;       /* 0x200 */
45    volatile unsigned int tx0addr;       /* 0x204 */
46    volatile unsigned int tx0size;       /* 0x208 */
47    volatile unsigned int tx0wr;         /* 0x20C */
48    volatile unsigned int tx0rd;         /* 0x210 */
49    volatile unsigned int tx0irq;        /* 0x214 */
50
51    volatile unsigned int dummy3[58];    /* 0x218-0x2FC */
52
53    volatile unsigned int rx0ctrl;       /* 0x300 */
54    volatile unsigned int rx0addr;       /* 0x304 */
55    volatile unsigned int rx0size;       /* 0x308 */
56    volatile unsigned int rx0wr;         /* 0x30C */
57    volatile unsigned int rx0rd;         /* 0x310 */
58    volatile unsigned int rx0irq;        /* 0x314 */
59    volatile unsigned int rx0mask;       /* 0x318 */
60    volatile unsigned int rx0code;       /* 0x31C */
61};
62
63struct grcan_stats {
64        unsigned int passive_cnt;
65        unsigned int overrun_cnt;
66        unsigned int rxsync_cnt;
67        unsigned int txsync_cnt;
68  unsigned int txloss_cnt;
69  unsigned int ahberr_cnt;
70  unsigned int ints;
71};
72
73struct grcan_timing {
74        unsigned char scaler;
75        unsigned char ps1;
76        unsigned char ps2;
77        unsigned int  rsj;
78        unsigned char bpr;
79};
80
81struct grcan_selection {
82        int selection;
83        int enable0;
84        int enable1;
85};
86
87struct grcan_filter {
88        unsigned long long mask;
89        unsigned long long code;
90};
91
92/* CAN MESSAGE */
93typedef struct {
94        char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */
95        char rtr; /* RTR - Remote Transmission Request */
96        char unused; /* unused */
97        unsigned char len;
98        unsigned char data[8];
99        unsigned int id;
100} CANMsg;
101
102#define GRCAN_CFG_ABORT      0x00000001
103#define GRCAN_CFG_ENABLE0    0x00000002
104#define GRCAN_CFG_ENABLE1    0x00000004
105#define GRCAN_CFG_SELECTION  0x00000008
106#define GRCAN_CFG_SILENT     0x00000010
107#define GRCAN_CFG_BPR        0x00000300
108#define GRCAN_CFG_RSJ        0x00007000
109#define GRCAN_CFG_PS1        0x00f00000
110#define GRCAN_CFG_PS2        0x000f0000
111#define GRCAN_CFG_SCALER     0xff000000
112
113#define GRCAN_CFG_BPR_BIT    8
114#define GRCAN_CFG_RSJ_BIT    12
115#define GRCAN_CFG_PS1_BIT    20
116#define GRCAN_CFG_PS2_BIT    16
117#define GRCAN_CFG_SCALER_BIT 24
118
119#define GRCAN_CTRL_RESET  0x2
120#define GRCAN_CTRL_ENABLE 0x1
121
122#define GRCAN_TXCTRL_ENABLE 1
123#define GRCAN_TXCTRL_ONGOING 1
124
125#define GRCAN_RXCTRL_ENABLE 1
126#define GRCAN_RXCTRL_ONGOING 1
127
128/* Relative offset of IRQ sources to AMBA Plug&Play */
129#define GRCAN_IRQ_IRQ 0
130#define GRCAN_IRQ_TXSYNC 1
131#define GRCAN_IRQ_RXSYNC 2
132
133#define GRCAN_ERR_IRQ        0x1
134#define GRCAN_OFF_IRQ        0x2
135#define GRCAN_OR_IRQ         0x4
136#define GRCAN_RXAHBERR_IRQ   0x8
137#define GRCAN_TXAHBERR_IRQ   0x10
138#define GRCAN_RXIRQ_IRQ      0x20
139#define GRCAN_TXIRQ_IRQ      0x40
140#define GRCAN_RXFULL_IRQ     0x80
141#define GRCAN_TXEMPTY_IRQ    0x100
142#define GRCAN_RX_IRQ         0x200
143#define GRCAN_TX_IRQ         0x400
144#define GRCAN_RXSYNC_IRQ     0x800
145#define GRCAN_TXSYNC_IRQ     0x1000
146#define GRCAN_RXERR_IRQ      0x2000
147#define GRCAN_TXERR_IRQ      0x4000
148#define GRCAN_RXMISS_IRQ     0x8000
149#define GRCAN_TXLOSS_IRQ     0x10000
150
151#define GRCAN_STAT_PASS      0x1
152#define GRCAN_STAT_OFF       0x2
153#define GRCAN_STAT_OR        0x4
154#define GRCAN_STAT_AHBERR    0x8
155#define GRCAN_STAT_ACTIVE    0x10
156#define GRCAN_STAT_RXERRCNT  0xff00
157#define GRCAN_STAT_TXERRCNT  0xff0000
158
159/* IOCTL Commands controlling operational
160 * mode
161 */
162#define GRCAN_IOC_START          1   /* Bring the link up after open or bus-off */
163#define GRCAN_IOC_STOP           2   /* stop to change baud rate/config or closing down */
164#define GRCAN_IOC_ISSTARTED      3   /* return RTEMS_SUCCESSFUL when started, othervise EBUSY */
165#define GRCAN_IOC_FLUSH          4   /* Waits until all TX messages has been sent */
166
167/* IOCTL Commands that require connection
168 * to be stopped
169 */
170#define GRCAN_IOC_SET_SILENT     16  /* enable silent mode read only state */
171#define GRCAN_IOC_SET_ABORT      17  /* enable/disable stopping link on AHB Error */
172#define GRCAN_IOC_SET_SELECTION  18  /* Set Enable0,Enable1,Selection */
173#define GRCAN_IOC_SET_SPEED      19  /* Set baudrate by using driver's baud rate timing calculation routines */
174#define GRCAN_IOC_SET_BTRS       20  /* Set baudrate by specifying the timing registers manually */
175
176/* IOCTL Commands can be called whenever */
177#define GRCAN_IOC_SET_RXBLOCK    32  /* Enable/disable Blocking on reception (until at least one message has been received) */
178#define GRCAN_IOC_SET_TXBLOCK    33  /* Enable/disable Blocking on transmission (until at least one message has been transmitted) */
179#define GRCAN_IOC_SET_TXCOMPLETE 34  /* Enable/disable Blocking until all requested messages has been sent */
180#define GRCAN_IOC_SET_RXCOMPLETE 35  /* Enable/disable Blocking until all requested has been received */
181#define GRCAN_IOC_GET_STATS      36  /* Get Statistics */
182#define GRCAN_IOC_CLR_STATS      37  /* Clear Statistics */
183#define GRCAN_IOC_SET_AFILTER    38  /* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */
184#define GRCAN_IOC_SET_SFILTER    40  /* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */
185#define GRCAN_IOC_GET_STATUS     41  /* Get status register of GRCAN core */
186
187
188void grcan_register_drv(void);
189
190#ifdef __cplusplus
191}
192#endif
193
194#endif
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