1 | /* GR-RASTA-TMTC PCI Target driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * Configures the GR-RASTA-TMTC interface PCI board. |
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7 | * This driver provides a AMBA PnP bus by using the general part |
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8 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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9 | * |
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10 | * Driver resources for the AMBA PnP bus provided can be set using |
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11 | * gr_rasta_tmtc_set_resources(). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #ifndef __GR_RASTA_TMTC_H__ |
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19 | #define __GR_RASTA_TMTC_H__ |
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20 | |
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21 | #include <drvmgr/drvmgr.h> |
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22 | |
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23 | #ifdef __cplusplus |
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24 | extern "C" { |
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25 | #endif |
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26 | |
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27 | /* GPIO TM/TC configuration pin definitions |
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28 | * --31 PWRX (1=PW2APB, 0=TM VC3/4) |
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29 | * --30 PWTC (1=APB2PW, 0=TC MAP1/2) |
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30 | * --29 Redundant TM (1=enable, 0=disable) |
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31 | * --28 Redundant TC (1=enable, 0=disable) |
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32 | * --27 Select TM output (1=GRTM, 0=PTME) |
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33 | * --26 Loop back PW (1=enable, 0=disable) |
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34 | * --25 Transponder clock (1=PLL, 0=PLL bypass) |
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35 | * --24 PWTX-SELECT (0=TX0-0, 1=TX0-1) |
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36 | * --23 PDEC Map Switch (1=on, 0=off) |
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37 | * --22 PDEC Ext CPDU (1=on, 0=off) |
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38 | * --21 PDEC Super User (1=on, 0=off) |
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39 | * --20 PDEC RM On (1=on, 0=off) |
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40 | * --19 PDEC AU Enable (1=on, 0=off) |
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41 | * --18 PDEC Dynamic Mode (1=on, 0=off) |
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42 | * --17 PDEC Priority (1=on, 0=off) |
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43 | * --16 TC PSS Support (1=on, 0=off) |
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44 | * --15 TC Mark (1=on, 0=off) |
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45 | * --14 TC Pseudo (1=on, 0=off) |
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46 | * --13 TC Rising Clock (1=rise, 0=fall) |
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47 | * --12 TC Active High (1=high, 0=low) |
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48 | * --11 Bit Lock Positive (1=high, 0=low) |
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49 | * --10 RF Avail Positive (1=high, 0=low) |
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50 | * -- 9 : 0 SpaceCraft ID |
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51 | */ |
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52 | |
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53 | #define GR_TMTC_GPIO_PWRX (1<<31) |
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54 | #define GR_TMTC_GPIO_PWTC (1<<30) |
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55 | #define GR_TMTC_GPIO_RED_TM (1<<29) |
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56 | #define GR_TMTC_GPIO_RED_TC (1<<28) |
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57 | #define GR_TMTC_GPIO_GRTM_SEL (1<<27) |
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58 | #define GR_TMTC_GPIO_LB_PW (1<<26) |
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59 | #define GR_TMTC_GPIO_TRANSP_CLK (1<<25) |
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60 | #define GR_TMTC_GPIO_PWTX_SEL (1<<24) |
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61 | #define GR_TMTC_GPIO_PDEC_MAP (1<<23) |
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62 | #define GR_TMTC_GPIO_PDEC_CPDU (1<<22) |
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63 | #define GR_TMTC_GPIO_PDEC_SU (1<<21) |
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64 | #define GR_TMTC_GPIO_PDEC_RM (1<<20) |
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65 | #define GR_TMTC_GPIO_PDEC_AU (1<<19) |
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66 | #define GR_TMTC_GPIO_PDEC_DYN_MODE (1<<18) |
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67 | #define GR_TMTC_GPIO_PDEC_PRIO (1<<17) |
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68 | #define GR_TMTC_GPIO_TC_PSS (1<<16) |
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69 | #define GR_TMTC_GPIO_TC_MARK (1<<15) |
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70 | #define GR_TMTC_GPIO_TC_PSEUDO (1<<14) |
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71 | #define GR_TMTC_GPIO_TC_RISING_CLK (1<<13) |
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72 | #define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12) |
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73 | #define GR_TMTC_GPIO_TC_BIT_LOCK (1<<11) |
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74 | #define GR_TMTC_GPIO_TC_RF_AVAIL (1<<10) |
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75 | #define GR_TMTC_GPIO_SCID (0x000003ff) |
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76 | |
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77 | /* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be |
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78 | * used by the device drivers controlling the cores on the GR-RASTA-IO target |
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79 | * AMBA bus. |
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80 | * |
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81 | * The array is defined weak, and defaults to no resources. The array must be |
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82 | * terminated with a NULL resource. |
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83 | */ |
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84 | extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[]; |
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85 | |
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86 | /* Options to gr_rasta_io_print function */ |
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87 | #define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ |
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88 | #define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ |
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89 | |
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90 | /* Print information about GR-RASTA-TMTC PCI boards */ |
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91 | void gr_rasta_tmtc_print(int options); |
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92 | |
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93 | /* Print information about a GR-RASTA-TMTC PCI boards */ |
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94 | void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options); |
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95 | |
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96 | /* Register GR-RASTA-TMTC driver */ |
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97 | void gr_rasta_tmtc_register_drv(void); |
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98 | |
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99 | #ifdef __cplusplus |
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100 | } |
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101 | #endif |
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102 | |
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103 | #endif |
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