source: rtems/c/src/lib/libbsp/sparc/shared/include/gr1553b.h @ d745297

5
Last change on this file since d745297 was d745297, checked in by Daniel Hellstrom <daniel@…>, on 01/02/15 at 12:18:33

leon, gr1553b: comment cleanup
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1/* GR1553B driver, used by BC, RT and/or BM driver
2 *
3 * COPYRIGHT (c) 2010.
4 * Cobham Gaisler AB.
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 *
10 * OVERVIEW
11 * ========
12 * This driver controls the GR1553B device regardless of interfaces supported
13 * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an
14 * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM
15 * drivers to use. Since the different interfaces are accessed over the same
16 * register interface on the same core, the other drivers must share a GR1553B
17 * device. Any combination of interface functionality is supported, but the RT
18 * and BC functionality can nnot be used simultaneously due to hardware
19 * limitation.
20 *
21 */
22
23#ifndef __GR1553B_H__
24#define __GR1553B_H__
25
26#include <stdint.h>
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32/* The GR1553B registers */
33struct gr1553b_regs {
34        /* Common Registers */
35        volatile uint32_t irq;          /* 0x00 IRQ register */
36        volatile uint32_t imask;        /* 0x04 IRQ enable mask */
37        int unused0[(0x10-0x08)/4];
38        volatile uint32_t hwcfg;        /* 0x10 HW config register */
39
40        int unused1[(0x40-0x14)/4];     /* Padding */
41
42        /* BC Registers */
43        volatile uint32_t bc_stat;      /* 0x40 BC status */
44        volatile uint32_t bc_ctrl;      /* 0x44 BC Action register */
45        volatile uint32_t bc_bd;        /* 0x48 BC transfer list pointer */
46        volatile uint32_t bc_abd;       /* 0x4c BC async list pointer */
47        volatile uint32_t bc_timer;     /* 0x50 BC timer register */
48        volatile uint32_t bc_wake;      /* 0x54 BC wakeup control register */
49        volatile uint32_t bc_irqptr;    /* 0x58 BC transfer IRQ pointer */
50        volatile uint32_t bc_busmsk;    /* 0x5C BC per-RT bus mask register */
51
52        int unused2[(0x68-0x60)/4];     /* Padding */
53
54        volatile uint32_t bc_slot;      /* 0x68 BC Current BD pointer */
55        volatile uint32_t bc_aslot;     /* 0x6c BC Current async BD pointer */
56
57        int unused3[(0x80-0x70)/4];     /* Padding */
58
59        /* RT Registers */
60        volatile uint32_t rt_stat;      /* 0x80 RT status */
61        volatile uint32_t rt_cfg;       /* 0x84 RT config register */
62        volatile uint32_t rt_stat2;     /* 0x88 RT bus status bits */
63        volatile uint32_t rt_statw;     /* 0x8c RT status words */
64        volatile uint32_t rt_sync;      /* 0x90 RT bus synchronize */
65        volatile uint32_t rt_tab;       /* 0x94 RT subaddress table base */
66        volatile uint32_t rt_mcctrl;    /* 0x98 RT valid mode code mask */
67        int unused4[(0xa4-0x9c)/4];
68        volatile uint32_t rt_ttag;      /* 0xa4 RT time tag register */
69        int unused5;                    /* 0xa8 RESERVED */
70        volatile uint32_t rt_evsz;      /* 0xac RT event log end pointer */
71        volatile uint32_t rt_evlog;     /* 0xb0 RT event log position */
72        volatile uint32_t rt_evirq;     /* 0xb4 RT event log IRQ position */
73
74        int unused6[(0xc0-0xb8)/4];     /* Padding */
75
76        /* BM Registers */
77        volatile uint32_t bm_stat;      /* 0xc0 BM status */
78        volatile uint32_t bm_ctrl;      /* 0xc4 BM control register */
79        volatile uint32_t bm_adr;       /* 0xc8 BM address filter */
80        volatile uint32_t bm_subadr;    /* 0xcc BM subaddress filter */
81        volatile uint32_t bm_mc;        /* 0xd0 BM mode code filter */
82        volatile uint32_t bm_start;     /* 0xd4 BM log start address */
83        volatile uint32_t bm_end;       /* 0xd8 BM log size/alignment mask */
84        volatile uint32_t bm_pos;       /* 0xdc BM log position */
85        volatile uint32_t bm_ttag;      /* 0xe0 BM time tag register */
86};
87
88#define GR1553BC_KEY 0x15520000
89#define GR1553RT_KEY 0x15530000
90
91/* IRQ Definitions */
92#define GR1553BC_IRQLOG_SIZE 64
93#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t))
94
95/*** IRQ Flag Register ***/
96#define GR1553B_IRQ_BCEV_BIT    0
97#define GR1553B_IRQ_BCD_BIT     1
98#define GR1553B_IRQ_BCWK_BIT    2
99#define GR1553B_IRQ_RTEV_BIT    8
100#define GR1553B_IRQ_RTD_BIT     9
101#define GR1553B_IRQ_RTTE_BIT    10
102#define GR1553B_IRQ_BMD_BIT     16
103#define GR1553B_IRQ_BMTOF_BIT   17
104
105#define GR1553B_IRQ_BCEV        (1<<GR1553B_IRQ_BCEV_BIT)
106#define GR1553B_IRQ_BCD         (1<<GR1553B_IRQ_BCD_BIT)
107#define GR1553B_IRQ_BCWK        (1<<GR1553B_IRQ_BCWK_BIT)
108#define GR1553B_IRQ_RTEV        (1<<GR1553B_IRQ_RTEV_BIT)
109#define GR1553B_IRQ_RTD         (1<<GR1553B_IRQ_RTD_BIT)
110#define GR1553B_IRQ_RTTE        (1<<GR1553B_IRQ_RTTE_BIT)
111#define GR1553B_IRQ_BMD         (1<<GR1553B_IRQ_BMD_BIT)
112#define GR1553B_IRQ_BMTOF       (1<<GR1553B_IRQ_BMTOF_BIT)
113
114/*** IRQ Enable Register ***/
115#define GR1553B_IRQEN_BCEVE_BIT 0
116#define GR1553B_IRQEN_BCDE_BIT  1
117#define GR1553B_IRQEN_BCWKE_BIT 2
118#define GR1553B_IRQEN_RTEVE_BIT 8
119#define GR1553B_IRQEN_RTDE_BIT  9
120#define GR1553B_IRQEN_RTTEE_BIT 10
121#define GR1553B_IRQEN_BMDE_BIT  16
122#define GR1553B_IRQEN_BMTOE_BIT 17
123
124#define GR1553B_IRQEN_BCEVE     (1<<GR1553B_IRQEN_BCEVE_BIT)
125#define GR1553B_IRQEN_BCDE      (1<<GR1553B_IRQEN_BCDE_BIT)
126#define GR1553B_IRQEN_BCWKE     (1<<GR1553B_IRQEN_BCWKE_BIT)
127#define GR1553B_IRQEN_RTEVE     (1<<GR1553B_IRQEN_RTEVE_BIT)
128#define GR1553B_IRQEN_RTDE      (1<<GR1553B_IRQEN_RTDE_BIT)
129#define GR1553B_IRQEN_RTTEE     (1<<GR1553B_IRQEN_RTTEE_BIT)
130#define GR1553B_IRQEN_BMDE      (1<<GR1553B_IRQEN_BMDE_BIT)
131#define GR1553B_IRQEN_BMTOE     (1<<GR1553B_IRQEN_BMTOE_BIT)
132
133/*** BC Status Register ***/
134#define GR1553B_BC_STAT_SCST_BIT        0
135#define GR1553B_BC_STAT_SCADL_BIT       3
136#define GR1553B_BC_STAT_ASST_BIT        8
137#define GR1553B_BC_STAT_ASADL_BIT       11
138#define GR1553B_BC_STAT_BCSUP_BIT       31
139
140#define GR1553B_BC_STAT_SCST            (0x3<<GR1553B_BC_STAT_SCST_BIT)
141#define GR1553B_BC_STAT_SCADL           (0x1f<<GR1553B_BC_STAT_SCADL_BIT)
142#define GR1553B_BC_STAT_ASST            (0x3<<GR1553B_BC_STAT_ASST_BIT)
143#define GR1553B_BC_STAT_ASADL           (0x1f<<GR1553B_BC_STAT_ASADL_BIT)
144#define GR1553B_BC_STAT_BCSUP           (1<<GR1553B_BC_STAT_BCSUP_BIT)
145
146/*** BC Action Register ***/
147#define GR1553B_BC_ACT_SCSRT_BIT        0
148#define GR1553B_BC_ACT_SCSUS_BIT        1
149#define GR1553B_BC_ACT_SCSTP_BIT        2
150#define GR1553B_BC_ACT_SETT_BIT         3
151#define GR1553B_BC_ACT_CLRT_BIT         4
152#define GR1553B_BC_ACT_ASSRT_BIT        8
153#define GR1553B_BC_ACT_ASSTP_BIT        9
154#define GR1553B_BC_ACT_BCKEY_BIT        16
155
156#define GR1553B_BC_ACT_SCSRT            (1<<GR1553B_BC_ACT_SCSRT_BIT)
157#define GR1553B_BC_ACT_SCSUS            (1<<GR1553B_BC_ACT_SCSUS_BIT)
158#define GR1553B_BC_ACT_SCSTP            (1<<GR1553B_BC_ACT_SCSTP_BIT)
159#define GR1553B_BC_ACT_SETT             (1<<GR1553B_BC_ACT_SETT_BIT)
160#define GR1553B_BC_ACT_CLRT             (1<<GR1553B_BC_ACT_CLRT_BIT)
161#define GR1553B_BC_ACT_ASSRT            (1<<GR1553B_BC_ACT_ASSRT_BIT)
162#define GR1553B_BC_ACT_ASSTP            (1<<GR1553B_BC_ACT_ASSTP_BIT)
163#define GR1553B_BC_ACT_BCKEY            (0xffff<<GR1553B_BC_ACT_BCKEY_BIT)
164
165/*** BC Timer Register ***/
166#define GR1553B_BC_TIMER_SCTM_BIT       0
167
168#define GR1553B_BC_TIMER_SCTM           (0xffffff<<GR1553B_BC_TIMER_SCTM_BIT)
169
170/*** BC Wake-up control Register ***/
171#define GR1553B_BC_WAKE_TIME_BIT        0
172#define GR1553B_BC_WAKE_WKEN_BIT        31
173
174#define GR1553B_BC_WAKE_TIME            (0xffffff<<GR1553B_BC_WAKE_TIME_BIT)
175#define GR1553B_BC_WAKE_WKEN            (1<GR1553B_BC_WAKE_WKEN_BIT)
176
177/*** RT status Register ***/
178#define GR1553B_RT_STAT_RUN_BIT         0
179#define GR1553B_RT_STAT_SHDB_BIT        1
180#define GR1553B_RT_STAT_SHDA_BIT        2
181#define GR1553B_RT_STAT_ACT_BIT         3
182#define GR1553B_RT_STAT_RTSUP_BIT       31
183
184#define GR1553B_RT_STAT_RUN             (1<<GR1553B_RT_STAT_RUN_BIT)
185#define GR1553B_RT_STAT_SHDB            (1<<GR1553B_RT_STAT_SHDB_BIT)
186#define GR1553B_RT_STAT_SHDA            (1<<GR1553B_RT_STAT_SHDA_BIT)
187#define GR1553B_RT_STAT_ACT             (1<<GR1553B_RT_STAT_ACT_BIT)
188#define GR1553B_RT_STAT_RTSUP           (1<<GR1553B_RT_STAT_RTSUP_BIT)
189
190
191/*** RT Config Register ***/
192#define GR1553B_RT_CFG_RTEN_BIT         0
193#define GR1553B_RT_CFG_RTADDR_BIT       1
194#define GR1553B_RT_CFG_RTKEY_BIT        16
195
196#define GR1553B_RT_CFG_RTEN             (1<<GR1553B_RT_CFG_RTEN_BIT)
197#define GR1553B_RT_CFG_RTADDR           (1<<GR1553B_RT_CFG_RTADDR_BIT)
198#define GR1553B_RT_CFG_RTKEY            (0xffff<<GR1553B_RT_CFG_RTKEY_BIT)
199
200/*** RT Bus Status Register ***/
201#define GR1553B_RT_STAT2_RTEN_BIT       0
202#define GR1553B_RT_STAT2_DBCA_BIT       1
203#define GR1553B_RT_STAT2_SSF_BIT        2
204#define GR1553B_RT_STAT2_BUSY_BIT       3
205#define GR1553B_RT_STAT2_SREQ_BIT       4
206
207#define GR1553B_RT_STAT2_RTEN           (1<<GR1553B_RT_STAT2_RTEN_BIT)
208#define GR1553B_RT_STAT2_DBCA           (1<<GR1553B_RT_STAT2_DBCA_BIT)
209#define GR1553B_RT_STAT2_SSF            (1<<GR1553B_RT_STAT2_SSF_BIT)
210#define GR1553B_RT_STAT2_BUSY           (1<<GR1553B_RT_STAT2_BUSY_BIT)
211#define GR1553B_RT_STAT2_SREQ           (1<<GR1553B_RT_STAT2_RTEN_BIT)
212
213/*** RT Status Words Register ***/
214#define GR1553B_RT_STATW_VECW_BIT       0
215#define GR1553B_RT_STATW_BITW_BIT       16
216
217#define GR1553B_RT_STATW_VECW           (0xffff<<GR1553B_RT_STATW_VECW_BIT)
218#define GR1553B_RT_STATW_BITW           (0xffff<<GR1553B_RT_STATW_BITW_BIT)
219
220/*** RT Sync Register ***/
221#define GR1553B_RT_SYNC_SYD_BIT         0
222#define GR1553B_RT_SYNC_SYTM_BIT        16
223
224#define GR1553B_RT_SYNC_SYD             (0xffff<<GR1553B_RT_SYNC_SYD_BIT)
225#define GR1553B_RT_SYNC_SYTM            (0xffff<<GR1553B_RT_SYNC_SYTM_BIT)
226
227/*** RT Sub adress table Register ***/
228#define GR1553B_RT_TAB_SATB_BIT         0
229
230#define GR1553B_RT_TAB_SATB             (0xffff<<GR1553B_RT_TAB_SATB_BIT)
231
232/*** RT Mode code control Register ***/
233#define GR1553B_RT_MCCTRL_S_BIT         0
234#define GR1553B_RT_MCCTRL_SB_BIT        2
235#define GR1553B_RT_MCCTRL_SD_BIT        4
236#define GR1553B_RT_MCCTRL_SDB_BIT       6
237#define GR1553B_RT_MCCTRL_TS_BIT        8
238#define GR1553B_RT_MCCTRL_TSB_BIT       10
239#define GR1553B_RT_MCCTRL_TVW_BIT       12
240#define GR1553B_RT_MCCTRL_TBW_BIT       14
241#define GR1553B_RT_MCCTRL_DBC_BIT       16
242#define GR1553B_RT_MCCTRL_IST_BIT       18
243#define GR1553B_RT_MCCTRL_ISTB_BIT      20
244#define GR1553B_RT_MCCTRL_ITF_BIT       22
245#define GR1553B_RT_MCCTRL_ITFB_BIT      24
246#define GR1553B_RT_MCCTRL_RRT_BIT       26
247#define GR1553B_RT_MCCTRL_RRTB_BIT      28
248
249#define GR1553B_RT_MCCTRL_S     (1<<GR1553B_RT_MCCTRL_S_BIT)
250#define GR1553B_RT_MCCTRL_SB    (1<<GR1553B_RT_MCCTRL_SB_BIT)
251#define GR1553B_RT_MCCTRL_SD    (1<<GR1553B_RT_MCCTRL_SD_BIT)
252#define GR1553B_RT_MCCTRL_SDB   (1<<GR1553B_RT_MCCTRL_SDB_BIT)
253#define GR1553B_RT_MCCTRL_TS    (1<<GR1553B_RT_MCCTRL_TS_BIT)
254#define GR1553B_RT_MCCTRL_TSB   (1<<GR1553B_RT_MCCTRL_TSB_BIT)
255#define GR1553B_RT_MCCTRL_TVW   (1<<GR1553B_RT_MCCTRL_TVW_BIT)
256#define GR1553B_RT_MCCTRL_TBW   (1<<GR1553B_RT_MCCTRL_TBW_BIT)
257#define GR1553B_RT_MCCTRL_DBC   (1<<GR1553B_RT_MCCTRL_DBC_BIT)
258#define GR1553B_RT_MCCTRL_IST   (1<<GR1553B_RT_MCCTRL_IST_BIT)
259#define GR1553B_RT_MCCTRL_ISTB  (1<<GR1553B_RT_MCCTRL_ISTB_BIT)
260#define GR1553B_RT_MCCTRL_ITF   (1<<GR1553B_RT_MCCTRL_ITF_BIT)
261#define GR1553B_RT_MCCTRL_ITFB  (1<<GR1553B_RT_MCCTRL_ITFB_BIT)
262#define GR1553B_RT_MCCTRL_RRT   (1<<GR1553B_RT_MCCTRL_RRT_BIT)
263#define GR1553B_RT_MCCTRL_RRTB  (1<<GR1553B_RT_MCCTRL_RRTB_BIT)
264
265/*** RT Time Tag control Register ***/
266#define GR1553B_RT_TTAG_TVAL_BIT        0
267#define GR1553B_RT_TTAG_TRES_BIT        16
268
269#define GR1553B_RT_TTAG_TVAL            (0xffff<<GR1553B_RT_TTAG_TVAL_BIT)
270#define GR1553B_RT_TTAG_TRES            (0xffff<<GR1553B_RT_TTAG_TRES_BIT)
271
272/*** BM Control Register ***/
273#define GR1553B_BM_STAT_BMSUP_BIT       31
274
275#define GR1553B_BM_STAT_BMSUP           (1<<GR1553B_BM_STAT_BMSUP_BIT)
276
277/*** BM Control Register ***/
278#define GR1553B_BM_CTRL_BMEN_BIT        0
279#define GR1553B_BM_CTRL_MANL_BIT        1
280#define GR1553B_BM_CTRL_UDWL_BIT        2
281#define GR1553B_BM_CTRL_IMCL_BIT        3
282
283#define GR1553B_BM_CTRL_BMEN    (1<<GR1553B_BM_CTRL_BMEN_BIT)
284#define GR1553B_BM_CTRL_MANL    (1<<GR1553B_BM_CTRL_MANL_BIT)
285#define GR1553B_BM_CTRL_UDWL    (1<<GR1553B_BM_CTRL_UDWL_BIT)
286#define GR1553B_BM_CTRL_IMCL    (1<<GR1553B_BM_CTRL_IMCL_BIT)
287
288/*** BM RT Mode code filter Register ***/
289#define GR1553B_BM_MC_S_BIT     0
290#define GR1553B_BM_MC_SB_BIT    1
291#define GR1553B_BM_MC_SD_BIT    2
292#define GR1553B_BM_MC_SDB_BIT   3
293#define GR1553B_BM_MC_TS_BIT    4
294#define GR1553B_BM_MC_TSB_BIT   5
295#define GR1553B_BM_MC_TVW_BIT   6
296#define GR1553B_BM_MC_TBW_BIT   7
297#define GR1553B_BM_MC_DBC_BIT   8
298#define GR1553B_BM_MC_IST_BIT   9
299#define GR1553B_BM_MC_ISTB_BIT  10
300#define GR1553B_BM_MC_ITF_BIT   11
301#define GR1553B_BM_MC_ITFB_BIT  12
302#define GR1553B_BM_MC_RRT_BIT   13
303#define GR1553B_BM_MC_RRTB_BIT  14
304#define GR1553B_BM_MC_TSW_BIT   15
305#define GR1553B_BM_MC_TLC_BIT   16
306#define GR1553B_BM_MC_STS_BIT   17
307#define GR1553B_BM_MC_STSB_BIT  18
308
309#define GR1553B_BM_MC_S         (1<<GR1553B_BM_MC_S_BIT)
310#define GR1553B_BM_MC_SB        (1<<GR1553B_BM_MC_SB_BIT)
311#define GR1553B_BM_MC_SD        (1<<GR1553B_BM_MC_SD_BIT)
312#define GR1553B_BM_MC_SDB       (1<<GR1553B_BM_MC_SDB_BIT)
313#define GR1553B_BM_MC_TS        (1<<GR1553B_BM_MC_TS_BIT)
314#define GR1553B_BM_MC_TSB       (1<<GR1553B_BM_MC_TSB_BIT)
315#define GR1553B_BM_MC_TVW       (1<<GR1553B_BM_MC_TVW_BIT)
316#define GR1553B_BM_MC_TBW       (1<<GR1553B_BM_MC_TBW_BIT)
317#define GR1553B_BM_MC_DBC       (1<<GR1553B_BM_MC_DBC_BIT)
318#define GR1553B_BM_MC_IST       (1<<GR1553B_BM_MC_IST_BIT)
319#define GR1553B_BM_MC_ISTB      (1<<GR1553B_BM_MC_ISTB_BIT)
320#define GR1553B_BM_MC_ITF       (1<<GR1553B_BM_MC_ITF_BIT)
321#define GR1553B_BM_MC_ITFB      (1<<GR1553B_BM_MC_ITFB_BIT)
322#define GR1553B_BM_MC_RRT       (1<<GR1553B_BM_MC_RRT_BIT)
323#define GR1553B_BM_MC_RRTB      (1<<GR1553B_BM_MC_RRTB_BIT)
324#define GR1553B_BM_MC_TSW       (1<<GR1553B_BM_MC_TSW_BIT)
325#define GR1553B_BM_MC_TLC       (1<<GR1553B_BM_MC_TLC_BIT)
326#define GR1553B_BM_MC_STS       (1<<GR1553B_BM_MC_STS_BIT)
327#define GR1553B_BM_MC_STSB      (1<<GR1553B_BM_MC_STSB_BIT)
328
329/*** BM RT Mode code filter Register ***/
330#define GR1553B_BM_TTAG_VAL_BIT 0
331#define GR1553B_BM_TTAG_RES_BIT 24
332
333#define GR1553B_BM_TTAG_VAL             (0xffffff<<GR1553B_BM_TTAG_VAL_BIT)
334#define GR1553B_BM_TTAG_RES             (0xff<<GR1553B_BM_TTAG_RES_BIT)
335
336/* Register GR1553B driver */
337extern void gr1553_register(void);
338
339/*** BC Device allocation ***/
340/* Allocate a BC device. Minor is assigned to a device in the order
341 * they are registered to the driver.
342 */
343extern struct drvmgr_dev **gr1553_bc_open(int minor);
344/* Free a BC device previously allocated */
345extern void gr1553_bc_close(struct drvmgr_dev **dev);
346
347/*** RT Device allocation ***/
348/* Allocate a BC device. Minor is assigned to a device in the order
349 * they are registered to the driver.
350 */
351extern struct drvmgr_dev **gr1553_rt_open(int minor);
352/* Free a BC device previously allocated */
353extern void gr1553_rt_close(struct drvmgr_dev **dev);
354
355/*** BM Device allocation ***/
356/* Allocate a BC device. Minor is assigned to a device in the order
357 * they are registered to the driver.
358 */
359extern struct drvmgr_dev **gr1553_bm_open(int minor);
360/* Free a BC device previously allocated */
361extern void gr1553_bm_close(struct drvmgr_dev **dev);
362
363#ifdef __cplusplus
364}
365#endif
366
367#endif /* __GR1553B_H__ */
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