source: rtems/c/src/lib/libbsp/sparc/shared/include/gr1553b.h @ 3bb4122

4.115
Last change on this file since 3bb4122 was 3bb4122, checked in by Daniel Hellstrom <daniel@…>, on 02/23/15 at 12:02:39

LEON: added new drivers to the LEON2/LEON3 BSPs

Most drivers use the Driver Manager for device probing, they
work on AMBA-over-PCI systems if PCI is big-endian.

New APIs:

  • GPIO Library, interfaced to GRGPIO
  • GENIRQ, Generic interrupt service implementation helper

New GRLIB Drivers:

  • ACTEL 1553 RT, user interface is similar to 1553 BRM driver
  • GR1553 (1553 BC, RT and BM core)
  • AHBSTAT (AHB error status core)
  • GRADCDAC (Core interfacing to ADC/DAC hardware)
  • GRGPIO (GPIO port accessed from GPIO Library)
  • MCTRL (Memory controller settings configuration)
  • GRETH (10/100/1000 Ethernet driver using Driver manager)
  • GRPWM (Pulse Width Modulation core)
  • SPICTRL (SPI master interface)
  • GRSPW_ROUTER (SpaceWire? Router AMBA configuration interface)
  • GRCTM (SpaceCraft? on-board Time Management core)
  • SPWCUC (Time distribution over SpaceWire?)
  • GRTC (SpaceCraft? up-link Tele core)
  • GRTM (SpaceCraft? down-link Tele Metry core)

GR712RC ASIC specific interfaces:

  • GRASCS
  • CANMUX (select between OCCAN and SATCAN)
  • SATCAN
  • SLINK
  • Property mode set to 100644
File size: 13.6 KB
Line 
1/* GR1553B driver, used by BC, RT and/or BM driver
2 *
3 * COPYRIGHT (c) 2010.
4 * Cobham Gaisler AB.
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.com/license/LICENSE.
9 *
10 * OVERVIEW
11 * ========
12 * This driver controls the GR1553B device regardless of interfaces supported
13 * (BC, RT and/or BM). The device can be located at an on-chip AMBA or an
14 * AMBA-over-PCI bus. This driver provides an interface for the BC, RT and BM
15 * drivers to use. Since the different interfaces are accessed over the same
16 * register interface on the same core, the other drivers must share a GR1553B
17 * device. Any combination of interface functionality is supported, but the RT
18 * and BC functionality can nnot be used simultaneously due to hardware
19 * limitation.
20 *
21 */
22
23#ifndef __GR1553B_H__
24#define __GR1553B_H__
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30/* The GR1553B registers */
31struct gr1553b_regs {
32        /* Common Registers */
33        volatile unsigned int irq; /* 0x00 IRQ register */
34        volatile unsigned int imask;    /* 0x04 IRQ enable mask */
35        int unused0[(0x10-0x08)/4];
36        volatile unsigned int hwcfg;    /* 0x10 HW config register */
37
38        int unused1[(0x40-0x14)/4];     /* Padding */
39
40        /* BC Registers */
41        volatile unsigned int bc_stat;  /* 0x40 BC status */
42        volatile unsigned int bc_ctrl;  /* 0x44 BC Action register */
43        volatile unsigned int bc_bd;    /* 0x48 BC transfer list pointer */
44        volatile unsigned int bc_abd;   /* 0x4c BC async list pointer */
45        volatile unsigned int bc_timer; /* 0x50 BC timer register */
46        volatile unsigned int bc_wake;  /* 0x54 BC wakeup control register */
47        volatile unsigned int bc_irqptr;/* 0x58 BC transfer IRQ pointer */
48        volatile unsigned int bc_busmsk;/* 0x5C BC per-RT bus mask register */
49
50        int unused2[(0x68-0x60)/4];     /* Padding */
51
52        volatile unsigned int bc_slot;  /* 0x48 BC Current BD pointer */
53        volatile unsigned int bc_aslot; /* 0x4c BC Current async BD pointer */
54
55        int unused3[(0x80-0x70)/4];     /* Padding */
56
57        /* RT Registers */
58        volatile unsigned int rt_stat;  /* 0x80 RT status */
59        volatile unsigned int rt_cfg;   /* 0x84 RT config register */
60        volatile unsigned int rt_stat2; /* 0x88 RT bus status bits */
61        volatile unsigned int rt_statw; /* 0x8c RT status words */
62        volatile unsigned int rt_sync;  /* 0x90 RT bus synchronize */
63        volatile unsigned int rt_tab;   /* 0x94 RT subaddress table base */
64        volatile unsigned int rt_mcctrl;/* 0x98 RT valid mode code mask */
65        int unused4[(0xa4-0x9c)/4];
66        volatile unsigned int rt_ttag;  /* 0xa4 RT time tag register */
67        int unused5;                    /* 0xa8 RESERVED */
68        volatile unsigned int rt_evsz;  /* 0xac RT event log end pointer */
69        volatile unsigned int rt_evlog; /* 0xb0 RT event log position */
70        volatile unsigned int rt_evirq; /* 0xb4 RT event log IRQ position */
71
72        int unused6[(0xc0-0xb8)/4];     /* Padding */
73
74        /* BM Registers */
75        volatile unsigned int bm_stat;  /* 0xc0 BM status */
76        volatile unsigned int bm_ctrl;  /* 0xc4 BM control register */
77        volatile unsigned int bm_adr;   /* 0xc8 BM address filter */
78        volatile unsigned int bm_subadr;/* 0xcc BM subaddress filter */
79        volatile unsigned int bm_mc;    /* 0xd0 BM mode code filter */
80        volatile unsigned int bm_start; /* 0xd4 BM log start address */
81        volatile unsigned int bm_end;   /* 0xd8 BM log size/alignment mask */
82        volatile unsigned int bm_pos;   /* 0xdc BM log position */
83        volatile unsigned int bm_ttag;  /* 0xe0 BM time tag register */
84};
85
86#define GR1553BC_KEY 0x15520000
87#define GR1553RT_KEY 0x15530000
88
89/* IRQ Definitions */
90#define GR1553BC_IRQLOG_SIZE 64
91#define GR1553BC_IRQLOG_CNT (GR1553BC_IRQLOG_SIZE/sizeof(uint32_t))
92
93/*** IRQ Flag Register ***/
94#define GR1553B_IRQ_BCEV_BIT    0
95#define GR1553B_IRQ_BCD_BIT     1
96#define GR1553B_IRQ_BCWK_BIT    2
97#define GR1553B_IRQ_RTEV_BIT    8
98#define GR1553B_IRQ_RTD_BIT     9
99#define GR1553B_IRQ_RTTE_BIT    10
100#define GR1553B_IRQ_BMD_BIT     16
101#define GR1553B_IRQ_BMTOF_BIT   17
102
103#define GR1553B_IRQ_BCEV        (1<<GR1553B_IRQ_BCEV_BIT)
104#define GR1553B_IRQ_BCD         (1<<GR1553B_IRQ_BCD_BIT)
105#define GR1553B_IRQ_BCWK        (1<<GR1553B_IRQ_BCWK_BIT)
106#define GR1553B_IRQ_RTEV        (1<<GR1553B_IRQ_RTEV_BIT)
107#define GR1553B_IRQ_RTD         (1<<GR1553B_IRQ_RTD_BIT)
108#define GR1553B_IRQ_RTTE        (1<<GR1553B_IRQ_RTTE_BIT)
109#define GR1553B_IRQ_BMD         (1<<GR1553B_IRQ_BMD_BIT)
110#define GR1553B_IRQ_BMTOF       (1<<GR1553B_IRQ_BMTOF_BIT)
111
112/*** IRQ Enable Register ***/
113#define GR1553B_IRQEN_BCEVE_BIT 0
114#define GR1553B_IRQEN_BCDE_BIT  1
115#define GR1553B_IRQEN_BCWKE_BIT 2
116#define GR1553B_IRQEN_RTEVE_BIT 8
117#define GR1553B_IRQEN_RTDE_BIT  9
118#define GR1553B_IRQEN_RTTEE_BIT 10
119#define GR1553B_IRQEN_BMDE_BIT  16
120#define GR1553B_IRQEN_BMTOE_BIT 17
121
122#define GR1553B_IRQEN_BCEVE     (1<<GR1553B_IRQEN_BCEVE_BIT)
123#define GR1553B_IRQEN_BCDE      (1<<GR1553B_IRQEN_BCDE_BIT)
124#define GR1553B_IRQEN_BCWKE     (1<<GR1553B_IRQEN_BCWKE_BIT)
125#define GR1553B_IRQEN_RTEVE     (1<<GR1553B_IRQEN_RTEVE_BIT)
126#define GR1553B_IRQEN_RTDE      (1<<GR1553B_IRQEN_RTDE_BIT)
127#define GR1553B_IRQEN_RTTEE     (1<<GR1553B_IRQEN_RTTEE_BIT)
128#define GR1553B_IRQEN_BMDE      (1<<GR1553B_IRQEN_BMDE_BIT)
129#define GR1553B_IRQEN_BMTOE     (1<<GR1553B_IRQEN_BMTOE_BIT)
130
131/*** BC Status Register ***/
132#define GR1553B_BC_STAT_SCST_BIT        0
133#define GR1553B_BC_STAT_SCADL_BIT       3
134#define GR1553B_BC_STAT_ASST_BIT        8
135#define GR1553B_BC_STAT_ASADL_BIT       11
136#define GR1553B_BC_STAT_BCSUP_BIT       31
137
138#define GR1553B_BC_STAT_SCST            (0x3<<GR1553B_BC_STAT_SCST_BIT)
139#define GR1553B_BC_STAT_SCADL           (0x1f<<GR1553B_BC_STAT_SCADL_BIT)
140#define GR1553B_BC_STAT_ASST            (0x3<<GR1553B_BC_STAT_ASST_BIT)
141#define GR1553B_BC_STAT_ASADL           (0x1f<<GR1553B_BC_STAT_ASADL_BIT)
142#define GR1553B_BC_STAT_BCSUP           (1<<GR1553B_BC_STAT_BCSUP_BIT)
143
144/*** BC Action Register ***/
145#define GR1553B_BC_ACT_SCSRT_BIT        0
146#define GR1553B_BC_ACT_SCSUS_BIT        1
147#define GR1553B_BC_ACT_SCSTP_BIT        2
148#define GR1553B_BC_ACT_SETT_BIT         3
149#define GR1553B_BC_ACT_CLRT_BIT         4
150#define GR1553B_BC_ACT_ASSRT_BIT        8
151#define GR1553B_BC_ACT_ASSTP_BIT        9
152#define GR1553B_BC_ACT_BCKEY_BIT        16
153
154#define GR1553B_BC_ACT_SCSRT            (1<<GR1553B_BC_ACT_SCSRT_BIT)
155#define GR1553B_BC_ACT_SCSUS            (1<<GR1553B_BC_ACT_SCSUS_BIT)
156#define GR1553B_BC_ACT_SCSTP            (1<<GR1553B_BC_ACT_SCSTP_BIT)
157#define GR1553B_BC_ACT_SETT             (1<<GR1553B_BC_ACT_SETT_BIT)
158#define GR1553B_BC_ACT_CLRT             (1<<GR1553B_BC_ACT_CLRT_BIT)
159#define GR1553B_BC_ACT_ASSRT            (1<<GR1553B_BC_ACT_ASSRT_BIT)
160#define GR1553B_BC_ACT_ASSTP            (1<<GR1553B_BC_ACT_ASSTP_BIT)
161#define GR1553B_BC_ACT_BCKEY            (0xffff<<GR1553B_BC_ACT_BCKEY_BIT)
162
163/*** BC Timer Register ***/
164#define GR1553B_BC_TIMER_SCTM_BIT       0
165
166#define GR1553B_BC_TIMER_SCTM           (0xffffff<<GR1553B_BC_TIMER_SCTM_BIT)
167
168/*** BC Wake-up control Register ***/
169#define GR1553B_BC_WAKE_TIME_BIT        0
170#define GR1553B_BC_WAKE_WKEN_BIT        31
171
172#define GR1553B_BC_WAKE_TIME            (0xffffff<<GR1553B_BC_WAKE_TIME_BIT)
173#define GR1553B_BC_WAKE_WKEN            (1<GR1553B_BC_WAKE_WKEN_BIT)
174
175/*** RT status Register ***/
176#define GR1553B_RT_STAT_RUN_BIT         0
177#define GR1553B_RT_STAT_SHDB_BIT        1
178#define GR1553B_RT_STAT_SHDA_BIT        2
179#define GR1553B_RT_STAT_ACT_BIT         3
180#define GR1553B_RT_STAT_RTSUP_BIT       31
181
182#define GR1553B_RT_STAT_RUN             (1<<GR1553B_RT_STAT_RUN_BIT)
183#define GR1553B_RT_STAT_SHDB            (1<<GR1553B_RT_STAT_SHDB_BIT)
184#define GR1553B_RT_STAT_SHDA            (1<<GR1553B_RT_STAT_SHDA_BIT)
185#define GR1553B_RT_STAT_ACT             (1<<GR1553B_RT_STAT_ACT_BIT)
186#define GR1553B_RT_STAT_RTSUP           (1<<GR1553B_RT_STAT_RTSUP_BIT)
187
188
189/*** RT Config Register ***/
190#define GR1553B_RT_CFG_RTEN_BIT         0
191#define GR1553B_RT_CFG_RTADDR_BIT       1
192#define GR1553B_RT_CFG_RTKEY_BIT        16
193
194#define GR1553B_RT_CFG_RTEN             (1<<GR1553B_RT_CFG_RTEN_BIT)
195#define GR1553B_RT_CFG_RTADDR           (1<<GR1553B_RT_CFG_RTADDR_BIT)
196#define GR1553B_RT_CFG_RTKEY            (0xffff<<GR1553B_RT_CFG_RTKEY_BIT)
197
198/*** RT Bus Status Register ***/
199#define GR1553B_RT_STAT2_RTEN_BIT       0
200#define GR1553B_RT_STAT2_DBCA_BIT       1
201#define GR1553B_RT_STAT2_SSF_BIT        2
202#define GR1553B_RT_STAT2_BUSY_BIT       3
203#define GR1553B_RT_STAT2_SREQ_BIT       4
204
205#define GR1553B_RT_STAT2_RTEN           (1<<GR1553B_RT_STAT2_RTEN_BIT)
206#define GR1553B_RT_STAT2_DBCA           (1<<GR1553B_RT_STAT2_DBCA_BIT)
207#define GR1553B_RT_STAT2_SSF            (1<<GR1553B_RT_STAT2_SSF_BIT)
208#define GR1553B_RT_STAT2_BUSY           (1<<GR1553B_RT_STAT2_BUSY_BIT)
209#define GR1553B_RT_STAT2_SREQ           (1<<GR1553B_RT_STAT2_RTEN_BIT)
210
211/*** RT Status Words Register ***/
212#define GR1553B_RT_STATW_VECW_BIT       0
213#define GR1553B_RT_STATW_BITW_BIT       16
214
215#define GR1553B_RT_STATW_VECW           (0xffff<<GR1553B_RT_STATW_VECW_BIT)
216#define GR1553B_RT_STATW_BITW           (0xffff<<GR1553B_RT_STATW_BITW_BIT)
217
218/*** RT Sync Register ***/
219#define GR1553B_RT_SYNC_SYD_BIT         0
220#define GR1553B_RT_SYNC_SYTM_BIT        16
221
222#define GR1553B_RT_SYNC_SYD             (0xffff<<GR1553B_RT_SYNC_SYD_BIT)
223#define GR1553B_RT_SYNC_SYTM            (0xffff<<GR1553B_RT_SYNC_SYTM_BIT)
224
225/*** RT Sub adress table Register ***/
226#define GR1553B_RT_TAB_SATB_BIT         0
227
228#define GR1553B_RT_TAB_SATB             (0xffff<<GR1553B_RT_TAB_SATB_BIT)
229
230/*** RT Mode code control Register ***/
231#define GR1553B_RT_MCCTRL_S_BIT         0
232#define GR1553B_RT_MCCTRL_SB_BIT        2
233#define GR1553B_RT_MCCTRL_SD_BIT        4
234#define GR1553B_RT_MCCTRL_SDB_BIT       6
235#define GR1553B_RT_MCCTRL_TS_BIT        8
236#define GR1553B_RT_MCCTRL_TSB_BIT       10
237#define GR1553B_RT_MCCTRL_TVW_BIT       12
238#define GR1553B_RT_MCCTRL_TBW_BIT       14
239#define GR1553B_RT_MCCTRL_DBC_BIT       16
240#define GR1553B_RT_MCCTRL_IST_BIT       18
241#define GR1553B_RT_MCCTRL_ISTB_BIT      20
242#define GR1553B_RT_MCCTRL_ITF_BIT       22
243#define GR1553B_RT_MCCTRL_ITFB_BIT      24
244#define GR1553B_RT_MCCTRL_RRT_BIT       26
245#define GR1553B_RT_MCCTRL_RRTB_BIT      28
246
247#define GR1553B_RT_MCCTRL_S     (1<<GR1553B_RT_MCCTRL_S_BIT)
248#define GR1553B_RT_MCCTRL_SB    (1<<GR1553B_RT_MCCTRL_SB_BIT)
249#define GR1553B_RT_MCCTRL_SD    (1<<GR1553B_RT_MCCTRL_SD_BIT)
250#define GR1553B_RT_MCCTRL_SDB   (1<<GR1553B_RT_MCCTRL_SDB_BIT)
251#define GR1553B_RT_MCCTRL_TS    (1<<GR1553B_RT_MCCTRL_TS_BIT)
252#define GR1553B_RT_MCCTRL_TSB   (1<<GR1553B_RT_MCCTRL_TSB_BIT)
253#define GR1553B_RT_MCCTRL_TVW   (1<<GR1553B_RT_MCCTRL_TVW_BIT)
254#define GR1553B_RT_MCCTRL_TBW   (1<<GR1553B_RT_MCCTRL_TBW_BIT)
255#define GR1553B_RT_MCCTRL_DBC   (1<<GR1553B_RT_MCCTRL_DBC_BIT)
256#define GR1553B_RT_MCCTRL_IST   (1<<GR1553B_RT_MCCTRL_IST_BIT)
257#define GR1553B_RT_MCCTRL_ISTB  (1<<GR1553B_RT_MCCTRL_ISTB_BIT)
258#define GR1553B_RT_MCCTRL_ITF   (1<<GR1553B_RT_MCCTRL_ITF_BIT)
259#define GR1553B_RT_MCCTRL_ITFB  (1<<GR1553B_RT_MCCTRL_ITFB_BIT)
260#define GR1553B_RT_MCCTRL_RRT   (1<<GR1553B_RT_MCCTRL_RRT_BIT)
261#define GR1553B_RT_MCCTRL_RRTB  (1<<GR1553B_RT_MCCTRL_RRTB_BIT)
262
263/*** RT Time Tag control Register ***/
264#define GR1553B_RT_TTAG_TVAL_BIT        0
265#define GR1553B_RT_TTAG_TRES_BIT        16
266
267#define GR1553B_RT_TTAG_TVAL            (0xffff<<GR1553B_RT_TTAG_TVAL_BIT)
268#define GR1553B_RT_TTAG_TRES            (0xffff<<GR1553B_RT_TTAG_TRES_BIT)
269
270/*** BM Control Register ***/
271#define GR1553B_BM_STAT_BMSUP_BIT       31
272
273#define GR1553B_BM_STAT_BMSUP           (1<<GR1553B_BM_STAT_BMSUP_BIT)
274
275/*** BM Control Register ***/
276#define GR1553B_BM_CTRL_BMEN_BIT        0
277#define GR1553B_BM_CTRL_MANL_BIT        1
278#define GR1553B_BM_CTRL_UDWL_BIT        2
279#define GR1553B_BM_CTRL_IMCL_BIT        3
280
281#define GR1553B_BM_CTRL_BMEN    (1<<GR1553B_BM_CTRL_BMEN_BIT)
282#define GR1553B_BM_CTRL_MANL    (1<<GR1553B_BM_CTRL_MANL_BIT)
283#define GR1553B_BM_CTRL_UDWL    (1<<GR1553B_BM_CTRL_UDWL_BIT)
284#define GR1553B_BM_CTRL_IMCL    (1<<GR1553B_BM_CTRL_IMCL_BIT)
285
286/*** BM RT Mode code filter Register ***/
287#define GR1553B_BM_MC_S_BIT     0
288#define GR1553B_BM_MC_SB_BIT    1
289#define GR1553B_BM_MC_SD_BIT    2
290#define GR1553B_BM_MC_SDB_BIT   3
291#define GR1553B_BM_MC_TS_BIT    4
292#define GR1553B_BM_MC_TSB_BIT   5
293#define GR1553B_BM_MC_TVW_BIT   6
294#define GR1553B_BM_MC_TBW_BIT   7
295#define GR1553B_BM_MC_DBC_BIT   8
296#define GR1553B_BM_MC_IST_BIT   9
297#define GR1553B_BM_MC_ISTB_BIT  10
298#define GR1553B_BM_MC_ITF_BIT   11
299#define GR1553B_BM_MC_ITFB_BIT  12
300#define GR1553B_BM_MC_RRT_BIT   13
301#define GR1553B_BM_MC_RRTB_BIT  14
302#define GR1553B_BM_MC_TSW_BIT   15
303#define GR1553B_BM_MC_TLC_BIT   16
304#define GR1553B_BM_MC_STS_BIT   17
305#define GR1553B_BM_MC_STSB_BIT  18
306
307#define GR1553B_BM_MC_S         (1<<GR1553B_BM_MC_S_BIT)
308#define GR1553B_BM_MC_SB        (1<<GR1553B_BM_MC_SB_BIT)
309#define GR1553B_BM_MC_SD        (1<<GR1553B_BM_MC_SD_BIT)
310#define GR1553B_BM_MC_SDB       (1<<GR1553B_BM_MC_SDB_BIT)
311#define GR1553B_BM_MC_TS        (1<<GR1553B_BM_MC_TS_BIT)
312#define GR1553B_BM_MC_TSB       (1<<GR1553B_BM_MC_TSB_BIT)
313#define GR1553B_BM_MC_TVW       (1<<GR1553B_BM_MC_TVW_BIT)
314#define GR1553B_BM_MC_TBW       (1<<GR1553B_BM_MC_TBW_BIT)
315#define GR1553B_BM_MC_DBC       (1<<GR1553B_BM_MC_DBC_BIT)
316#define GR1553B_BM_MC_IST       (1<<GR1553B_BM_MC_IST_BIT)
317#define GR1553B_BM_MC_ISTB      (1<<GR1553B_BM_MC_ISTB_BIT)
318#define GR1553B_BM_MC_ITF       (1<<GR1553B_BM_MC_ITF_BIT)
319#define GR1553B_BM_MC_ITFB      (1<<GR1553B_BM_MC_ITFB_BIT)
320#define GR1553B_BM_MC_RRT       (1<<GR1553B_BM_MC_RRT_BIT)
321#define GR1553B_BM_MC_RRTB      (1<<GR1553B_BM_MC_RRTB_BIT)
322#define GR1553B_BM_MC_TSW       (1<<GR1553B_BM_MC_TSW_BIT)
323#define GR1553B_BM_MC_TLC       (1<<GR1553B_BM_MC_TLC_BIT)
324#define GR1553B_BM_MC_STS       (1<<GR1553B_BM_MC_STS_BIT)
325#define GR1553B_BM_MC_STSB      (1<<GR1553B_BM_MC_STSB_BIT)
326
327/*** BM RT Mode code filter Register ***/
328#define GR1553B_BM_TTAG_VAL_BIT 0
329#define GR1553B_BM_TTAG_RES_BIT 24
330
331#define GR1553B_BM_TTAG_VAL             (0xffffff<<GR1553B_BM_TTAG_VAL_BIT)
332#define GR1553B_BM_TTAG_RES             (0xff<<GR1553B_BM_TTAG_RES_BIT)
333
334/* Register GR1553B driver */
335extern void gr1553_register(void);
336
337/*** BC Device allocation ***/
338/* Allocate a BC device. Minor is assigned to a device in the order
339 * they are registered to the driver.
340 */
341extern struct drvmgr_dev **gr1553_bc_open(int minor);
342/* Free a BC device previously allocated */
343extern void gr1553_bc_close(struct drvmgr_dev **dev);
344
345/*** RT Device allocation ***/
346/* Allocate a BC device. Minor is assigned to a device in the order
347 * they are registered to the driver.
348 */
349extern struct drvmgr_dev **gr1553_rt_open(int minor);
350/* Free a BC device previously allocated */
351extern void gr1553_rt_close(struct drvmgr_dev **dev);
352
353/*** BM Device allocation ***/
354/* Allocate a BC device. Minor is assigned to a device in the order
355 * they are registered to the driver.
356 */
357extern struct drvmgr_dev **gr1553_bm_open(int minor);
358/* Free a BC device previously allocated */
359extern void gr1553_bm_close(struct drvmgr_dev **dev);
360
361#ifdef __cplusplus
362}
363#endif
364
365#endif /* __GR1553B_H__ */
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