[3bb4122] | 1 | /* GRGPIO GPIO Driver interface. |
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| 2 | * |
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| 3 | * COPYRIGHT (c) 2009. |
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| 4 | * Cobham Gaisler AB. |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[4a7d1026] | 8 | * http://www.rtems.org/license/LICENSE. |
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[3bb4122] | 9 | */ |
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| 10 | |
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| 11 | #include <bsp.h> |
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| 12 | #include <rtems/libio.h> |
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| 13 | #include <stdlib.h> |
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| 14 | #include <assert.h> |
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| 15 | #include <rtems/bspIo.h> |
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| 16 | #include <string.h> |
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| 17 | #include <stdio.h> |
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| 18 | |
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| 19 | #include <drvmgr/drvmgr.h> |
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| 20 | #include <drvmgr/ambapp_bus.h> |
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[5823bae8] | 21 | #include <bsp/grgpio.h> |
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| 22 | #include <bsp/gpiolib.h> |
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[3bb4122] | 23 | #include <ambapp.h> |
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| 24 | #include <grlib.h> |
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| 25 | |
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| 26 | /*#define DEBUG 1*/ |
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| 27 | |
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| 28 | #ifdef DEBUG |
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| 29 | #define DBG(x...) printk(x) |
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| 30 | #define STATIC |
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| 31 | #else |
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| 32 | #define DBG(x...) |
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| 33 | #define STATIC static |
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| 34 | #endif |
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| 35 | |
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| 36 | struct grgpio_isr { |
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| 37 | drvmgr_isr isr; |
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| 38 | void *arg; |
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| 39 | }; |
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| 40 | |
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| 41 | struct grgpio_priv { |
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| 42 | struct drvmgr_dev *dev; |
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| 43 | struct grgpio_regs *regs; |
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| 44 | int irq; |
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| 45 | int minor; |
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| 46 | |
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| 47 | /* Driver implementation */ |
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| 48 | int port_cnt; |
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| 49 | unsigned char port_handles[32]; |
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| 50 | struct grgpio_isr isrs[32]; |
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| 51 | struct gpiolib_drv gpiolib_desc; |
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| 52 | unsigned int bypass; |
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| 53 | unsigned int imask; |
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| 54 | }; |
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| 55 | |
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| 56 | /******************* Driver Manager Part ***********************/ |
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| 57 | |
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| 58 | int grgpio_device_init(struct grgpio_priv *priv); |
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| 59 | |
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| 60 | int grgpio_init1(struct drvmgr_dev *dev); |
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| 61 | int grgpio_init2(struct drvmgr_dev *dev); |
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| 62 | |
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| 63 | struct drvmgr_drv_ops grgpio_ops = |
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| 64 | { |
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| 65 | .init = {grgpio_init1, NULL, NULL, NULL}, |
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| 66 | .remove = NULL, |
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| 67 | .info = NULL |
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| 68 | }; |
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| 69 | |
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| 70 | struct amba_dev_id grgpio_ids[] = |
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| 71 | { |
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| 72 | {VENDOR_GAISLER, GAISLER_GPIO}, |
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| 73 | {0, 0} /* Mark end of table */ |
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| 74 | }; |
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| 75 | |
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| 76 | struct amba_drv_info grgpio_drv_info = |
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| 77 | { |
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| 78 | { |
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| 79 | DRVMGR_OBJ_DRV, /* Driver */ |
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| 80 | NULL, /* Next driver */ |
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| 81 | NULL, /* Device list */ |
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| 82 | DRIVER_AMBAPP_GAISLER_GRGPIO_ID, /* Driver ID */ |
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| 83 | "GRGPIO_DRV", /* Driver Name */ |
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| 84 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
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| 85 | &grgpio_ops, |
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| 86 | NULL, /* Funcs */ |
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| 87 | 0, /* No devices yet */ |
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| 88 | 0, |
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| 89 | }, |
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| 90 | &grgpio_ids[0] |
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| 91 | }; |
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| 92 | |
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| 93 | void grgpio_register_drv (void) |
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| 94 | { |
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| 95 | DBG("Registering GRGPIO driver\n"); |
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| 96 | drvmgr_drv_register(&grgpio_drv_info.general); |
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| 97 | } |
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| 98 | |
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| 99 | /* Register GRGPIO pins as quick as possible to the GPIO library, |
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| 100 | * other drivers may depend upon them in INIT LEVEL 2. |
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| 101 | * Note that since IRQ may not be available in init1, it is assumed |
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| 102 | * that the GPIOLibrary does not request IRQ routines until LEVEL 2. |
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| 103 | */ |
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| 104 | int grgpio_init1(struct drvmgr_dev *dev) |
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| 105 | { |
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| 106 | struct grgpio_priv *priv; |
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| 107 | int status, port; |
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| 108 | |
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| 109 | DBG("GRGPIO[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
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| 110 | |
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| 111 | /* This core will not find other cores, but other driver may depend upon |
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| 112 | * the GPIO library to function. So, we set up GPIO right away. |
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| 113 | */ |
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| 114 | |
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| 115 | /* Initialize library if not already done */ |
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| 116 | status = gpiolib_initialize(); |
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| 117 | if ( status < 0 ) |
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| 118 | return DRVMGR_FAIL; |
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| 119 | |
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| 120 | priv = dev->priv = malloc(sizeof(struct grgpio_priv)); |
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| 121 | if ( !priv ) |
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| 122 | return DRVMGR_NOMEM; |
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| 123 | memset(priv, 0, sizeof(*priv)); |
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| 124 | priv->dev = dev; |
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| 125 | |
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| 126 | if ( grgpio_device_init(priv) ) { |
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| 127 | free(dev->priv); |
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| 128 | dev->priv = NULL; |
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| 129 | return DRVMGR_FAIL; |
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| 130 | } |
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| 131 | |
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| 132 | /* Register all ports available on this core as GPIO port to |
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| 133 | * upper layer |
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| 134 | */ |
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| 135 | for(port=0; port<priv->port_cnt; port++) { |
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| 136 | priv->port_handles[port] = port; |
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| 137 | gpiolib_drv_register(&priv->gpiolib_desc, |
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| 138 | &priv->port_handles[port]); |
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| 139 | } |
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| 140 | |
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| 141 | return DRVMGR_OK; |
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| 142 | } |
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| 143 | |
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| 144 | /******************* Driver Implementation ***********************/ |
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| 145 | |
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| 146 | /* Find port from handle, returns -1 if not found */ |
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[cb64b862] | 147 | static int grgpio_find_port(void *handle, struct grgpio_priv **priv) |
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[3bb4122] | 148 | { |
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| 149 | unsigned char portnr; |
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| 150 | |
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| 151 | portnr = *(unsigned char *)handle; |
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| 152 | if ( portnr > 31 ) |
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| 153 | return -1; |
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| 154 | *priv = (struct grgpio_priv *) |
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| 155 | (((unsigned int)handle - portnr*sizeof(unsigned char)) - |
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| 156 | offsetof(struct grgpio_priv, port_handles)); |
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| 157 | return portnr; |
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| 158 | } |
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| 159 | |
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[cb64b862] | 160 | static int grgpio_gpiolib_open(void *handle) |
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[3bb4122] | 161 | { |
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| 162 | struct grgpio_priv *priv; |
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| 163 | int portnr; |
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| 164 | |
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| 165 | portnr = grgpio_find_port(handle, &priv); |
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| 166 | if ( portnr < 0 ) { |
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| 167 | DBG("GRGPIO: FAILED OPENING HANDLE 0x%08x\n", handle); |
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| 168 | return -1; |
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| 169 | } |
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| 170 | DBG("GRGPIO[0x%08x][%d]: OPENING\n", priv->regs, portnr); |
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| 171 | |
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| 172 | /* Open the device, nothing to be done... */ |
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| 173 | |
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| 174 | return 0; |
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| 175 | } |
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| 176 | |
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[cb64b862] | 177 | static int grgpio_grpiolib_config(void *handle, struct gpiolib_config *cfg) |
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[3bb4122] | 178 | { |
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| 179 | struct grgpio_priv *priv; |
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| 180 | int portnr; |
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| 181 | unsigned int mask; |
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| 182 | |
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| 183 | portnr = grgpio_find_port(handle, &priv); |
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| 184 | if ( portnr < 0 ) { |
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| 185 | return -1; |
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| 186 | } |
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| 187 | DBG("GRGPIO[0x%08x][%d]: CONFIG\n", priv->regs, portnr); |
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| 188 | |
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| 189 | /* Configure the device. And check that operation is supported, |
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| 190 | * not all I/O Pins have IRQ support. |
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| 191 | */ |
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| 192 | mask = (1<<portnr); |
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| 193 | |
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| 194 | /* Return error when IRQ not supported by this I/O Line and it |
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| 195 | * is beeing enabled by user. |
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| 196 | */ |
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| 197 | if ( ((mask & priv->imask) == 0) && cfg->mask ) |
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| 198 | return -1; |
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| 199 | |
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| 200 | priv->regs->imask &= ~mask; /* Disable interrupt temporarily */ |
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| 201 | |
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| 202 | /* Configure settings before enabling interrupt */ |
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| 203 | priv->regs->ipol = (priv->regs->ipol & ~mask) | (cfg->irq_polarity ? mask : 0); |
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| 204 | priv->regs->iedge = (priv->regs->iedge & ~mask) | (cfg->irq_level ? 0 : mask); |
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| 205 | priv->regs->imask |= cfg->mask ? mask : 0; |
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| 206 | |
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| 207 | return 0; |
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| 208 | } |
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| 209 | |
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[cb64b862] | 210 | static int grgpio_grpiolib_get(void *handle, int *inval) |
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[3bb4122] | 211 | { |
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| 212 | struct grgpio_priv *priv; |
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| 213 | int portnr; |
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| 214 | |
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| 215 | portnr = grgpio_find_port(handle, &priv); |
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| 216 | if ( portnr < 0 ) { |
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| 217 | return -1; |
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| 218 | } |
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| 219 | DBG("GRGPIO[0x%08x][%d]: GET\n", priv->regs, portnr); |
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| 220 | |
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| 221 | /* Get current status of the port */ |
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| 222 | if ( inval ) |
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| 223 | *inval = (priv->regs->data >> portnr) & 0x1; |
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| 224 | |
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| 225 | return 0; |
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| 226 | } |
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| 227 | |
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[cb64b862] | 228 | static int grgpio_grpiolib_irq_opts(void *handle, unsigned int options) |
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[3bb4122] | 229 | { |
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| 230 | struct grgpio_priv *priv; |
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| 231 | int portnr; |
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| 232 | drvmgr_isr isr; |
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| 233 | void *arg; |
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| 234 | |
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| 235 | portnr = grgpio_find_port(handle, &priv); |
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| 236 | if ( portnr < 0 ) { |
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| 237 | return -1; |
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| 238 | } |
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| 239 | DBG("GRGPIO[0x%08x][%d]: IRQ OPTS 0x%x\n", priv->regs, portnr, options); |
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| 240 | |
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| 241 | if ( options & GPIOLIB_IRQ_FORCE ) |
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| 242 | return -1; |
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| 243 | |
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| 244 | isr = priv->isrs[portnr].isr; |
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| 245 | arg = priv->isrs[portnr].arg; |
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| 246 | |
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| 247 | if ( options & GPIOLIB_IRQ_DISABLE ) { |
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| 248 | /* Disable interrupt at interrupt controller */ |
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| 249 | if ( drvmgr_interrupt_unregister(priv->dev, portnr, isr, arg) ) { |
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| 250 | return -1; |
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| 251 | } |
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| 252 | } |
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| 253 | if ( options & GPIOLIB_IRQ_CLEAR ) { |
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| 254 | /* Clear interrupt at interrupt controller */ |
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| 255 | if ( drvmgr_interrupt_clear(priv->dev, portnr) ) { |
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| 256 | return -1; |
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| 257 | } |
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| 258 | } |
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| 259 | if ( options & GPIOLIB_IRQ_ENABLE ) { |
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| 260 | /* Enable interrupt at interrupt controller */ |
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| 261 | if ( drvmgr_interrupt_register(priv->dev, portnr, "grgpio", isr, arg) ) { |
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| 262 | return -1; |
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| 263 | } |
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| 264 | } |
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[b583cc5f] | 265 | if ( options & GPIOLIB_IRQ_MASK ) { |
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| 266 | /* Mask (disable) interrupt at interrupt controller */ |
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| 267 | if ( drvmgr_interrupt_mask(priv->dev, portnr) ) { |
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| 268 | return -1; |
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| 269 | } |
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| 270 | } |
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| 271 | if ( options & GPIOLIB_IRQ_UNMASK ) { |
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| 272 | /* Unmask (enable) interrupt at interrupt controller */ |
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| 273 | if ( drvmgr_interrupt_unmask(priv->dev, portnr) ) { |
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| 274 | return -1; |
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| 275 | } |
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| 276 | } |
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[3bb4122] | 277 | |
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| 278 | return 0; |
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| 279 | } |
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| 280 | |
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[cb64b862] | 281 | static int grgpio_grpiolib_irq_register(void *handle, void *func, void *arg) |
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[3bb4122] | 282 | { |
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| 283 | struct grgpio_priv *priv; |
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| 284 | int portnr; |
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| 285 | |
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| 286 | portnr = grgpio_find_port(handle, &priv); |
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| 287 | if ( portnr < 0 ) { |
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| 288 | DBG("GRGPIO: FAILED OPENING HANDLE 0x%08x\n", handle); |
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| 289 | return -1; |
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| 290 | } |
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| 291 | DBG("GRGPIO: OPENING %d at [0x%08x]\n", portnr, priv->regs); |
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| 292 | |
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| 293 | /* Since the user doesn't provide the ISR and argument, we must... */ |
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| 294 | priv->isrs[portnr].isr = func; |
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| 295 | priv->isrs[portnr].arg = arg; |
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| 296 | |
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| 297 | return 0; |
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| 298 | } |
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| 299 | |
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[cb64b862] | 300 | static int grgpio_grpiolib_set(void *handle, int dir, int outval) |
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[3bb4122] | 301 | { |
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| 302 | struct grgpio_priv *priv; |
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| 303 | int portnr; |
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| 304 | unsigned int mask; |
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| 305 | |
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| 306 | portnr = grgpio_find_port(handle, &priv); |
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| 307 | if ( portnr < 0 ) { |
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| 308 | DBG("GRGPIO: FAILED OPENING HANDLE 0x%08x\n", handle); |
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| 309 | return -1; |
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| 310 | } |
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| 311 | DBG("GRGPIO: OPENING %d at [0x%08x]\n", portnr, priv->regs); |
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| 312 | |
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| 313 | /* Set Direction and Output */ |
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| 314 | mask = 1<<portnr; |
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| 315 | priv->regs->dir = (priv->regs->dir & ~mask) | (dir ? mask : 0); |
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| 316 | priv->regs->output = (priv->regs->output & ~mask) | (outval ? mask : 0); |
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| 317 | |
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| 318 | return 0; |
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| 319 | } |
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| 320 | |
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[cb64b862] | 321 | static int grgpio_gpiolib_show(void *handle) |
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[3bb4122] | 322 | { |
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| 323 | struct grgpio_priv *priv; |
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| 324 | int portnr, i, regs[7]; |
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| 325 | volatile unsigned int *reg; |
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| 326 | |
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| 327 | portnr = grgpio_find_port(handle, &priv); |
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| 328 | if ( portnr < 0 ) { |
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| 329 | DBG("GRGPIO: FAILED SHOWING HANDLE 0x%08x\n", handle); |
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| 330 | return -1; |
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| 331 | } |
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| 332 | for (i=0, reg=&priv->regs->data; i<7; i++, reg++) { |
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| 333 | regs[i] = ( *reg >> portnr) & 1; |
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| 334 | } |
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| 335 | printf("GRGPIO[%p] PORT[%d]: IN/OUT/DIR: [%d,%d,%d], MASK/POL/EDGE: [%d,%d,%d], BYPASS: %d\n", |
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| 336 | priv->regs, portnr, regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6]); |
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| 337 | return 0; |
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| 338 | } |
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| 339 | |
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[cb64b862] | 340 | static int grgpio_gpiolib_get_info(void *handle, struct gpiolib_info *pinfo) |
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[3bb4122] | 341 | { |
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| 342 | struct grgpio_priv *priv; |
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| 343 | int portnr; |
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| 344 | char prefix[48]; |
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| 345 | struct drvmgr_dev *dev; |
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| 346 | |
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| 347 | if ( !pinfo ) |
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| 348 | return -1; |
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| 349 | |
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| 350 | portnr = grgpio_find_port(handle, &priv); |
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| 351 | if ( portnr < 0 ) { |
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| 352 | DBG("GRGPIO: FAILED GET_INFO HANDLE 0x%08x\n", handle); |
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| 353 | return -1; |
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| 354 | } |
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| 355 | |
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| 356 | /* Get Filesystem name prefix */ |
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| 357 | dev = priv->dev; |
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| 358 | prefix[0] = '\0'; |
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| 359 | if ( drvmgr_get_dev_prefix(dev, prefix) ) { |
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| 360 | /* Failed to get prefix, make sure of a unique FS name |
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| 361 | * by using the driver minor. |
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| 362 | */ |
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| 363 | snprintf(pinfo->devName, 64, "/dev/grgpio%d/%d", dev->minor_drv, portnr); |
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| 364 | } else { |
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| 365 | /* Got special prefix, this means we have a bus prefix |
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| 366 | * And we should use our "bus minor" |
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| 367 | */ |
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| 368 | snprintf(pinfo->devName, 64, "/dev/%sgrgpio%d/%d", prefix, dev->minor_bus, portnr); |
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| 369 | } |
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| 370 | |
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| 371 | return 0; |
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| 372 | } |
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| 373 | |
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| 374 | static struct gpiolib_drv_ops grgpio_gpiolib_ops = |
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| 375 | { |
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| 376 | .config = grgpio_grpiolib_config, |
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| 377 | .get = grgpio_grpiolib_get, |
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| 378 | .irq_opts = grgpio_grpiolib_irq_opts, |
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| 379 | .irq_register = grgpio_grpiolib_irq_register, |
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| 380 | .open = grgpio_gpiolib_open, |
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| 381 | .set = grgpio_grpiolib_set, |
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| 382 | .show = grgpio_gpiolib_show, |
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| 383 | .get_info = grgpio_gpiolib_get_info, |
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| 384 | }; |
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| 385 | |
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| 386 | int grgpio_device_init(struct grgpio_priv *priv) |
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| 387 | { |
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| 388 | struct amba_dev_info *ambadev; |
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| 389 | struct ambapp_core *pnpinfo; |
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| 390 | union drvmgr_key_value *value; |
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| 391 | unsigned int mask; |
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| 392 | int port_cnt; |
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| 393 | |
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| 394 | /* Get device information from AMBA PnP information */ |
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| 395 | ambadev = (struct amba_dev_info *)priv->dev->businfo; |
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| 396 | if ( ambadev == NULL ) { |
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| 397 | return -1; |
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| 398 | } |
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| 399 | pnpinfo = &ambadev->info; |
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| 400 | priv->irq = pnpinfo->irq; |
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| 401 | priv->regs = (struct grgpio_regs *)pnpinfo->apb_slv->start; |
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| 402 | |
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| 403 | DBG("GRGPIO: 0x%08x irq %d\n", (unsigned int)priv->regs, priv->irq); |
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| 404 | |
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| 405 | /* Mask all Interrupts */ |
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| 406 | priv->regs->imask = 0; |
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| 407 | |
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| 408 | /* Make IRQ Rising edge triggered default */ |
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| 409 | priv->regs->ipol = 0xfffffffe; |
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| 410 | priv->regs->iedge = 0xfffffffe; |
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| 411 | |
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| 412 | /* Read what I/O lines have IRQ support */ |
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| 413 | priv->imask = priv->regs->ipol; |
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| 414 | |
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| 415 | /* Let the user configure the port count, this might be needed |
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| 416 | * when the GPIO lines must not be changed (assigned during bootup) |
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| 417 | */ |
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[4d3e70f4] | 418 | value = drvmgr_dev_key_get(priv->dev, "nBits", DRVMGR_KT_INT); |
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[3bb4122] | 419 | if ( value ) { |
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| 420 | priv->port_cnt = value->i; |
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| 421 | } else { |
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| 422 | /* Auto detect number of GPIO ports */ |
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| 423 | priv->regs->dir = 0; |
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| 424 | priv->regs->output = 0xffffffff; |
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| 425 | mask = priv->regs->output; |
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| 426 | priv->regs->output = 0; |
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| 427 | |
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| 428 | for(port_cnt=0; port_cnt<32; port_cnt++) |
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| 429 | if ( (mask & (1<<port_cnt)) == 0 ) |
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| 430 | break; |
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| 431 | priv->port_cnt = port_cnt; |
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| 432 | } |
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| 433 | |
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| 434 | /* Let the user configure the BYPASS register, this might be needed |
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| 435 | * to select which cores can do I/O on a pin. |
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| 436 | */ |
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[4d3e70f4] | 437 | value = drvmgr_dev_key_get(priv->dev, "bypass", DRVMGR_KT_INT); |
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[3bb4122] | 438 | if ( value ) { |
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| 439 | priv->bypass = value->i; |
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| 440 | } else { |
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| 441 | priv->bypass = 0; |
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| 442 | } |
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| 443 | priv->regs->bypass = priv->bypass; |
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| 444 | |
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| 445 | /* Prepare GPIOLIB layer */ |
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| 446 | priv->gpiolib_desc.ops = &grgpio_gpiolib_ops; |
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| 447 | |
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| 448 | return 0; |
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| 449 | } |
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