[226455f] | 1 | /* OC_CAN driver |
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| 2 | * |
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| 3 | * COPYRIGHT (c) 2007. |
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[3681925] | 4 | * Cobham Gaisler AB. |
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[226455f] | 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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[c499856] | 8 | * http://www.rtems.org/license/LICENSE. |
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[226455f] | 9 | */ |
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| 10 | |
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[a8595605] | 11 | #include <rtems.h> |
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[226455f] | 12 | #include <rtems/libio.h> |
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| 13 | #include <stdlib.h> |
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| 14 | #include <stdio.h> |
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| 15 | #include <string.h> |
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| 16 | #include <bsp.h> |
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| 17 | #include <rtems/bspIo.h> /* printk */ |
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| 18 | |
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[3681925] | 19 | #include <drvmgr/drvmgr.h> |
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| 20 | #include <drvmgr/ambapp_bus.h> |
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[5823bae8] | 21 | #include <bsp/occan.h> |
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[226455f] | 22 | |
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| 23 | /* RTEMS -> ERRNO decoding table |
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[44b06ca] | 24 | |
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[226455f] | 25 | rtems_assoc_t errno_assoc[] = { |
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| 26 | { "OK", RTEMS_SUCCESSFUL, 0 }, |
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| 27 | { "BUSY", RTEMS_RESOURCE_IN_USE, EBUSY }, |
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| 28 | { "INVALID NAME", RTEMS_INVALID_NAME, EINVAL }, |
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| 29 | { "NOT IMPLEMENTED", RTEMS_NOT_IMPLEMENTED, ENOSYS }, |
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| 30 | { "TIMEOUT", RTEMS_TIMEOUT, ETIMEDOUT }, |
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| 31 | { "NO MEMORY", RTEMS_NO_MEMORY, ENOMEM }, |
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| 32 | { "NO DEVICE", RTEMS_UNSATISFIED, ENODEV }, |
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| 33 | { "INVALID NUMBER", RTEMS_INVALID_NUMBER, EBADF}, |
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| 34 | { "NOT RESOURCE OWNER", RTEMS_NOT_OWNER_OF_RESOURCE, EPERM}, |
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| 35 | { "IO ERROR", RTEMS_IO_ERROR, EIO}, |
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| 36 | { 0, 0, 0 }, |
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| 37 | }; |
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| 38 | |
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| 39 | */ |
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| 40 | |
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| 41 | /* |
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| 42 | #undef DEBUG |
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| 43 | #undef DEBUG_EXTRA |
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| 44 | #undef DEBUG_PRINT_REGMAP |
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| 45 | */ |
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| 46 | |
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| 47 | /* default to byte regs */ |
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| 48 | #ifndef OCCAN_WORD_REGS |
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| 49 | #define OCCAN_BYTE_REGS |
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| 50 | #else |
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| 51 | #undef OCCAN_BYTE_REGS |
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| 52 | #endif |
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| 53 | |
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[3681925] | 54 | /* Enable Fixup code older OCCAN with a TX IRQ-FLAG bug */ |
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| 55 | #define OCCAN_TX_IRQ_FLAG_FIXUP 1 |
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[226455f] | 56 | |
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| 57 | #define OCCAN_WORD_REG_OFS 0x80 |
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| 58 | #define OCCAN_NCORE_OFS 0x100 |
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| 59 | #define DEFAULT_CLKDIV 0x7 |
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| 60 | #define DEFAULT_EXTENDED_MODE 1 |
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| 61 | #define DEFAULT_RX_FIFO_LEN 64 |
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| 62 | #define DEFAULT_TX_FIFO_LEN 64 |
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| 63 | |
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| 64 | /* not implemented yet */ |
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| 65 | #undef REDUNDANT_CHANNELS |
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| 66 | |
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| 67 | /* Define common debug macros */ |
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| 68 | #ifdef DEBUG |
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| 69 | #define DBG(fmt, vargs...) printk(fmt, ## vargs ) |
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| 70 | #else |
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[44b06ca] | 71 | #define DBG(fmt, vargs...) |
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[226455f] | 72 | #endif |
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| 73 | |
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[a8595605] | 74 | /* Spin locks mapped via rtems_interrupt_lock_* API: */ |
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| 75 | #define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock) |
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| 76 | #define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name) |
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| 77 | #define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level) |
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| 78 | #define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level) |
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| 79 | #define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level) |
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| 80 | #define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level) |
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| 81 | #define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k |
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| 82 | #define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k) |
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| 83 | |
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[226455f] | 84 | /* fifo interface */ |
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| 85 | typedef struct { |
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| 86 | int cnt; |
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| 87 | int ovcnt; /* overwrite count */ |
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| 88 | int full; /* 1 = base contain cnt CANMsgs, tail==head */ |
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| 89 | CANMsg *tail, *head; |
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| 90 | CANMsg *base; |
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| 91 | char fifoarea[0]; |
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| 92 | } occan_fifo; |
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| 93 | |
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| 94 | /* PELICAN */ |
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[3681925] | 95 | |
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[226455f] | 96 | typedef struct { |
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[44b06ca] | 97 | unsigned char |
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[226455f] | 98 | mode, |
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| 99 | cmd, |
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| 100 | status, |
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| 101 | intflags, |
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| 102 | inten, |
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| 103 | resv0, |
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| 104 | bustim0, |
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| 105 | bustim1, |
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| 106 | unused0[2], |
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| 107 | resv1, |
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| 108 | arbcode, |
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| 109 | errcode, |
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| 110 | errwarn, |
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| 111 | rx_err_cnt, |
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| 112 | tx_err_cnt, |
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[44b06ca] | 113 | rx_fi_xff; /* this is also acceptance code 0 in reset mode */ |
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[226455f] | 114 | union{ |
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| 115 | struct { |
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| 116 | unsigned char id[2]; |
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| 117 | unsigned char data[8]; |
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| 118 | unsigned char next_in_fifo[2]; |
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| 119 | } rx_sff; |
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| 120 | struct { |
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| 121 | unsigned char id[4]; |
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| 122 | unsigned char data[8]; |
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| 123 | } rx_eff; |
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| 124 | struct { |
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| 125 | unsigned char id[2]; |
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| 126 | unsigned char data[8]; |
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| 127 | unsigned char unused[2]; |
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| 128 | } tx_sff; |
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| 129 | struct { |
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| 130 | unsigned char id[4]; |
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| 131 | unsigned char data[8]; |
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| 132 | } tx_eff; |
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| 133 | struct { |
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| 134 | unsigned char code[3]; |
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| 135 | unsigned char mask[4]; |
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| 136 | } rst_accept; |
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| 137 | } msg; |
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| 138 | unsigned char rx_msg_cnt; |
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| 139 | unsigned char unused1; |
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| 140 | unsigned char clkdiv; |
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[3681925] | 141 | } pelican8_regs; |
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| 142 | |
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[226455f] | 143 | typedef struct { |
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[44b06ca] | 144 | unsigned char |
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[226455f] | 145 | mode, unused0[3], |
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| 146 | cmd, unused1[3], |
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| 147 | status, unused2[3], |
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| 148 | intflags, unused3[3], |
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| 149 | inten, unused4[3], |
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| 150 | resv0, unused5[3], |
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| 151 | bustim0, unused6[3], |
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| 152 | bustim1, unused7[3], |
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| 153 | unused8[8], |
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| 154 | resv1,unused9[3], |
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| 155 | arbcode,unused10[3], |
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| 156 | errcode,unused11[3], |
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| 157 | errwarn,unused12[3], |
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| 158 | rx_err_cnt,unused13[3], |
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| 159 | tx_err_cnt,unused14[3], |
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[44b06ca] | 160 | rx_fi_xff, unused15[3]; /* this is also acceptance code 0 in reset mode */ |
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[226455f] | 161 | /* make sure to use pointers when writing (byte access) to these registers */ |
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| 162 | union{ |
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| 163 | struct { |
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| 164 | unsigned int id[2]; |
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| 165 | unsigned int data[8]; |
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| 166 | unsigned int next_in_fifo[2]; |
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| 167 | } rx_sff; |
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| 168 | struct { |
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| 169 | unsigned int id[4]; |
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| 170 | unsigned int data[8]; |
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| 171 | } rx_eff; |
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| 172 | struct { |
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| 173 | unsigned int id[2]; |
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| 174 | unsigned int data[8]; |
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| 175 | } tx_sff; |
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| 176 | struct { |
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| 177 | unsigned int id[4]; |
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| 178 | unsigned int data[8]; |
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| 179 | } tx_eff; |
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| 180 | struct { |
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| 181 | unsigned int code[3]; |
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| 182 | unsigned int mask[4]; |
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| 183 | } rst_accept; |
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| 184 | } msg; |
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| 185 | unsigned char rx_msg_cnt,unused16[3]; |
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| 186 | unsigned char unused17[4]; |
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| 187 | unsigned char clkdiv,unused18[3]; |
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[3681925] | 188 | } pelican32_regs; |
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| 189 | |
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| 190 | #ifdef OCCAN_BYTE_REGS |
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| 191 | #define pelican_regs pelican8_regs |
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| 192 | #else |
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| 193 | #define pelican_regs pelican32_regs |
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[226455f] | 194 | #endif |
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| 195 | |
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[3681925] | 196 | |
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[0743eae] | 197 | #define MAX_TSEG2 7 |
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| 198 | #define MAX_TSEG1 15 |
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[226455f] | 199 | |
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| 200 | #if 0 |
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| 201 | typedef struct { |
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| 202 | unsigned char brp; |
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| 203 | unsigned char sjw; |
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| 204 | unsigned char tseg1; |
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| 205 | unsigned char tseg2; |
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| 206 | unsigned char sam; |
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| 207 | } occan_speed_regs; |
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| 208 | #endif |
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| 209 | typedef struct { |
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| 210 | unsigned char btr0; |
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| 211 | unsigned char btr1; |
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| 212 | } occan_speed_regs; |
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| 213 | |
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| 214 | typedef struct { |
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[3681925] | 215 | struct drvmgr_dev *dev; |
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| 216 | char devName[32]; |
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[a8595605] | 217 | SPIN_DECLARE(devlock); |
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[3681925] | 218 | |
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[44b06ca] | 219 | /* hardware shortcuts */ |
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[226455f] | 220 | pelican_regs *regs; |
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[3681925] | 221 | int byte_regs; |
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[226455f] | 222 | int irq; |
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| 223 | occan_speed_regs timing; |
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| 224 | int channel; /* 0=default, 1=second bus */ |
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| 225 | int single_mode; |
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[3681925] | 226 | unsigned int sys_freq_hz; |
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[44b06ca] | 227 | |
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[226455f] | 228 | /* driver state */ |
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| 229 | rtems_id devsem; |
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| 230 | rtems_id txsem; |
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| 231 | rtems_id rxsem; |
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| 232 | int open; |
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| 233 | int started; |
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| 234 | int rxblk; |
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| 235 | int txblk; |
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[3681925] | 236 | int sending; |
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[226455f] | 237 | unsigned int status; |
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| 238 | occan_stats stats; |
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[44b06ca] | 239 | |
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[226455f] | 240 | /* rx&tx fifos */ |
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| 241 | occan_fifo *rxfifo; |
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| 242 | occan_fifo *txfifo; |
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[44b06ca] | 243 | |
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[226455f] | 244 | /* Config */ |
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| 245 | unsigned int speed; /* speed in HZ */ |
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| 246 | unsigned char acode[4]; |
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| 247 | unsigned char amask[4]; |
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| 248 | } occan_priv; |
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| 249 | |
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| 250 | /********** FIFO INTERFACE **********/ |
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| 251 | static void occan_fifo_put(occan_fifo *fifo); |
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| 252 | static CANMsg *occan_fifo_put_claim(occan_fifo *fifo, int force); |
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| 253 | static occan_fifo *occan_fifo_create(int cnt); |
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| 254 | static void occan_fifo_free(occan_fifo *fifo); |
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| 255 | static int occan_fifo_full(occan_fifo *fifo); |
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| 256 | static int occan_fifo_empty(occan_fifo *fifo); |
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| 257 | static void occan_fifo_get(occan_fifo *fifo); |
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| 258 | static CANMsg *occan_fifo_claim_get(occan_fifo *fifo); |
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[5b42368a] | 259 | static void occan_fifo_clr(occan_fifo *fifo); |
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[226455f] | 260 | |
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| 261 | /**** Hardware related Interface ****/ |
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| 262 | static int occan_calc_speedregs(unsigned int clock_hz, unsigned int rate, occan_speed_regs *result); |
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| 263 | static int occan_set_speedregs(occan_priv *priv, occan_speed_regs *timing); |
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| 264 | static void pelican_init(occan_priv *priv); |
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| 265 | static void pelican_open(occan_priv *priv); |
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| 266 | static int pelican_start(occan_priv *priv); |
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| 267 | static void pelican_stop(occan_priv *priv); |
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| 268 | static int pelican_send(occan_priv *can, CANMsg *msg); |
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| 269 | static void pelican_set_accept(occan_priv *priv, unsigned char *acode, unsigned char *amask); |
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[3681925] | 270 | void occan_interrupt(void *arg); |
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[13279f5d] | 271 | #ifdef DEBUG_PRINT_REGMAP |
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[226455f] | 272 | static void pelican_regadr_print(pelican_regs *regs); |
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[13279f5d] | 273 | #endif |
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[226455f] | 274 | |
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| 275 | /***** Driver related interface *****/ |
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| 276 | static rtems_device_driver occan_ioctl(rtems_device_major_number major, rtems_device_minor_number minor, void *arg); |
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| 277 | static rtems_device_driver occan_write(rtems_device_major_number major, rtems_device_minor_number minor, void *arg); |
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| 278 | static rtems_device_driver occan_read(rtems_device_major_number major, rtems_device_minor_number minor, void *arg); |
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| 279 | static rtems_device_driver occan_close(rtems_device_major_number major, rtems_device_minor_number minor, void *arg); |
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| 280 | static rtems_device_driver occan_open(rtems_device_major_number major, rtems_device_minor_number minor, void *arg); |
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| 281 | static rtems_device_driver occan_initialize(rtems_device_major_number major, rtems_device_minor_number unused, void *arg); |
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[3681925] | 282 | |
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| 283 | #define OCCAN_DRIVER_TABLE_ENTRY { occan_initialize, occan_open, occan_close, occan_read, occan_write, occan_ioctl } |
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| 284 | static rtems_driver_address_table occan_driver = OCCAN_DRIVER_TABLE_ENTRY; |
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[226455f] | 285 | |
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| 286 | |
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| 287 | /* Read byte bypassing */ |
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| 288 | |
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[3681925] | 289 | |
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| 290 | /* Bypass cache */ |
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| 291 | #define READ_REG(priv, address) occan_reg_read(priv, (unsigned int)address) |
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| 292 | #define WRITE_REG(priv, address, data) occan_reg_write(priv, (unsigned int)address, data) |
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| 293 | |
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[c9f75435] | 294 | static unsigned int occan_reg_read(occan_priv *priv, unsigned int address) |
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[3681925] | 295 | { |
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| 296 | unsigned int adr; |
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| 297 | if ( priv->byte_regs ) { |
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| 298 | adr = address; |
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| 299 | } else { |
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| 300 | /* Word accessed registers */ |
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| 301 | adr = (address & (~0x7f)) | ((address & 0x7f)<<2); |
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[226455f] | 302 | } |
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[3681925] | 303 | return *(volatile unsigned char *)adr; |
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| 304 | } |
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[226455f] | 305 | |
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[c9f75435] | 306 | static void occan_reg_write( |
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| 307 | occan_priv *priv, |
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| 308 | unsigned int address, |
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| 309 | unsigned char value) |
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[3681925] | 310 | { |
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| 311 | unsigned int adr; |
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| 312 | if ( priv->byte_regs ) { |
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| 313 | adr = address; |
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| 314 | } else { |
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| 315 | /* Word accessed registers */ |
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| 316 | adr = (address & (~0x7f)) | ((address & 0x7f)<<2); |
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| 317 | } |
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| 318 | *(volatile unsigned char *)adr = value;; |
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| 319 | } |
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[226455f] | 320 | |
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| 321 | /* Mode register bit definitions */ |
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| 322 | #define PELICAN_MOD_RESET 0x1 |
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| 323 | #define PELICAN_MOD_LISTEN 0x2 |
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| 324 | #define PELICAN_MOD_SELFTEST 0x4 |
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| 325 | #define PELICAN_MOD_ACCEPT 0x8 |
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| 326 | |
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| 327 | /* Command register bit definitions */ |
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| 328 | #define PELICAN_CMD_TXREQ 0x1 |
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| 329 | #define PELICAN_CMD_ABORT 0x2 |
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| 330 | #define PELICAN_CMD_RELRXBUF 0x4 |
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| 331 | #define PELICAN_CMD_CLRDOVR 0x8 |
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| 332 | #define PELICAN_CMD_SELFRXRQ 0x10 |
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| 333 | |
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| 334 | /* Status register bit definitions */ |
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| 335 | #define PELICAN_STAT_RXBUF 0x1 |
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| 336 | #define PELICAN_STAT_DOVR 0x2 |
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| 337 | #define PELICAN_STAT_TXBUF 0x4 |
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| 338 | #define PELICAN_STAT_TXOK 0x8 |
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| 339 | #define PELICAN_STAT_RX 0x10 |
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| 340 | #define PELICAN_STAT_TX 0x20 |
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| 341 | #define PELICAN_STAT_ERR 0x40 |
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| 342 | #define PELICAN_STAT_BUS 0x80 |
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| 343 | |
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| 344 | /* Interrupt register bit definitions */ |
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| 345 | #define PELICAN_IF_RX 0x1 |
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| 346 | #define PELICAN_IF_TX 0x2 |
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| 347 | #define PELICAN_IF_ERRW 0x4 |
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| 348 | #define PELICAN_IF_DOVR 0x8 |
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| 349 | #define PELICAN_IF_ERRP 0x20 |
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| 350 | #define PELICAN_IF_ARB 0x40 |
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| 351 | #define PELICAN_IF_BUS 0x80 |
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| 352 | |
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| 353 | /* Interrupt Enable register bit definitions */ |
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| 354 | #define PELICAN_IE_RX 0x1 |
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| 355 | #define PELICAN_IE_TX 0x2 |
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| 356 | #define PELICAN_IE_ERRW 0x4 |
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| 357 | #define PELICAN_IE_DOVR 0x8 |
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| 358 | #define PELICAN_IE_ERRP 0x20 |
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| 359 | #define PELICAN_IE_ARB 0x40 |
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| 360 | #define PELICAN_IE_BUS 0x80 |
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| 361 | |
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| 362 | /* Arbitration lost capture register bit definitions */ |
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| 363 | #define PELICAN_ARB_BITS 0x1f |
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| 364 | |
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| 365 | /* register bit definitions */ |
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| 366 | #define PELICAN_ECC_CODE_BIT 0x00 |
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| 367 | #define PELICAN_ECC_CODE_FORM 0x40 |
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| 368 | #define PELICAN_ECC_CODE_STUFF 0x80 |
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| 369 | #define PELICAN_ECC_CODE_OTHER 0xc0 |
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| 370 | #define PELICAN_ECC_CODE 0xc0 |
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| 371 | |
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| 372 | #define PELICAN_ECC_DIR 0x20 |
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| 373 | #define PELICAN_ECC_SEG 0x1f |
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| 374 | |
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| 375 | /* Clock divider register bit definitions */ |
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| 376 | #define PELICAN_CDR_DIV 0x7 |
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| 377 | #define PELICAN_CDR_OFF 0x8 |
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| 378 | #define PELICAN_CDR_MODE 0x80 |
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| 379 | #define PELICAN_CDR_MODE_PELICAN 0x80 |
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| 380 | #define PELICAN_CDR_MODE_BITS 7 |
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| 381 | #define PELICAN_CDR_MODE_BASICAN 0x00 |
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| 382 | |
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| 383 | |
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| 384 | /* register bit definitions */ |
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| 385 | #define OCCAN_BUSTIM_SJW 0xc0 |
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| 386 | #define OCCAN_BUSTIM_BRP 0x3f |
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| 387 | #define OCCAN_BUSTIM_SJW_BIT 6 |
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| 388 | |
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| 389 | #define OCCAN_BUSTIM_SAM 0x80 |
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| 390 | #define OCCAN_BUSTIM_TSEG2 0x70 |
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| 391 | #define OCCAN_BUSTIM_TSEG2_BIT 4 |
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| 392 | #define OCCAN_BUSTIM_TSEG1 0x0f |
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| 393 | |
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| 394 | /* register bit definitions */ |
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| 395 | /* |
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| 396 | #define PELICAN_S_ 0x1 |
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| 397 | #define PELICAN_S_ 0x2 |
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| 398 | #define PELICAN_S_ 0x4 |
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| 399 | #define PELICAN_S_ 0x8 |
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| 400 | #define PELICAN_S_ 0x10 |
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| 401 | #define PELICAN_S_ 0x20 |
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| 402 | #define PELICAN_S_ 0x40 |
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| 403 | #define PELICAN_S_ 0x80 |
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| 404 | */ |
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| 405 | |
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[3681925] | 406 | static int occan_driver_io_registered = 0; |
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| 407 | static rtems_device_major_number occan_driver_io_major = 0; |
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| 408 | |
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| 409 | /******************* Driver manager interface ***********************/ |
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| 410 | |
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| 411 | /* Driver prototypes */ |
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| 412 | int occan_register_io(rtems_device_major_number *m); |
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| 413 | int occan_device_init(occan_priv *pDev); |
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| 414 | |
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| 415 | int occan_init2(struct drvmgr_dev *dev); |
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| 416 | int occan_init3(struct drvmgr_dev *dev); |
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| 417 | |
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| 418 | struct drvmgr_drv_ops occan_ops = |
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| 419 | { |
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| 420 | .init = {NULL, occan_init2, occan_init3, NULL}, |
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| 421 | .remove = NULL, |
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| 422 | .info = NULL |
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| 423 | }; |
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| 424 | |
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| 425 | struct amba_dev_id occan_ids[] = |
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| 426 | { |
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| 427 | {VENDOR_GAISLER, GAISLER_CANAHB}, |
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| 428 | {0, 0} /* Mark end of table */ |
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| 429 | }; |
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| 430 | |
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| 431 | struct amba_drv_info occan_drv_info = |
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| 432 | { |
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| 433 | { |
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| 434 | DRVMGR_OBJ_DRV, /* Driver */ |
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| 435 | NULL, /* Next driver */ |
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| 436 | NULL, /* Device list */ |
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| 437 | DRIVER_AMBAPP_GAISLER_OCCAN_ID, /* Driver ID */ |
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| 438 | "OCCAN_DRV", /* Driver Name */ |
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| 439 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
---|
| 440 | &occan_ops, |
---|
| 441 | NULL, /* Funcs */ |
---|
| 442 | 0, /* No devices yet */ |
---|
| 443 | 0, |
---|
| 444 | }, |
---|
| 445 | &occan_ids[0] |
---|
| 446 | }; |
---|
| 447 | |
---|
| 448 | void occan_register_drv (void) |
---|
| 449 | { |
---|
| 450 | DBG("Registering OCCAN driver\n"); |
---|
| 451 | drvmgr_drv_register(&occan_drv_info.general); |
---|
| 452 | } |
---|
| 453 | |
---|
| 454 | int occan_init2(struct drvmgr_dev *dev) |
---|
| 455 | { |
---|
| 456 | occan_priv *priv; |
---|
| 457 | |
---|
| 458 | DBG("OCCAN[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
---|
| 459 | priv = dev->priv = malloc(sizeof(occan_priv)); |
---|
| 460 | if ( !priv ) |
---|
| 461 | return DRVMGR_NOMEM; |
---|
| 462 | memset(priv, 0, sizeof(*priv)); |
---|
| 463 | priv->dev = dev; |
---|
| 464 | |
---|
| 465 | return DRVMGR_OK; |
---|
| 466 | } |
---|
| 467 | |
---|
| 468 | int occan_init3(struct drvmgr_dev *dev) |
---|
| 469 | { |
---|
| 470 | occan_priv *priv; |
---|
| 471 | char prefix[32]; |
---|
| 472 | rtems_status_code status; |
---|
| 473 | |
---|
| 474 | priv = dev->priv; |
---|
| 475 | |
---|
| 476 | /* Do initialization */ |
---|
| 477 | |
---|
| 478 | if ( occan_driver_io_registered == 0) { |
---|
| 479 | /* Register the I/O driver only once for all cores */ |
---|
| 480 | if ( occan_register_io(&occan_driver_io_major) ) { |
---|
| 481 | /* Failed to register I/O driver */ |
---|
| 482 | dev->priv = NULL; |
---|
| 483 | return DRVMGR_FAIL; |
---|
| 484 | } |
---|
| 485 | |
---|
| 486 | occan_driver_io_registered = 1; |
---|
| 487 | } |
---|
| 488 | |
---|
| 489 | /* I/O system registered and initialized |
---|
| 490 | * Now we take care of device initialization. |
---|
| 491 | */ |
---|
| 492 | |
---|
| 493 | if ( occan_device_init(priv) ) { |
---|
| 494 | return DRVMGR_FAIL; |
---|
| 495 | } |
---|
| 496 | |
---|
| 497 | /* Get Filesystem name prefix */ |
---|
| 498 | prefix[0] = '\0'; |
---|
| 499 | if ( drvmgr_get_dev_prefix(dev, prefix) ) { |
---|
| 500 | /* Failed to get prefix, make sure of a unique FS name |
---|
| 501 | * by using the driver minor. |
---|
| 502 | */ |
---|
| 503 | sprintf(priv->devName, "/dev/occan%d", dev->minor_drv); |
---|
| 504 | } else { |
---|
| 505 | /* Got special prefix, this means we have a bus prefix |
---|
| 506 | * And we should use our "bus minor" |
---|
| 507 | */ |
---|
| 508 | sprintf(priv->devName, "/dev/%soccan%d", prefix, dev->minor_bus); |
---|
| 509 | } |
---|
| 510 | |
---|
| 511 | /* Register Device */ |
---|
| 512 | DBG("OCCAN[%d]: Registering %s\n", dev->minor_drv, priv->devName); |
---|
| 513 | status = rtems_io_register_name(priv->devName, occan_driver_io_major, dev->minor_drv); |
---|
| 514 | if (status != RTEMS_SUCCESSFUL) { |
---|
| 515 | return DRVMGR_FAIL; |
---|
| 516 | } |
---|
| 517 | |
---|
| 518 | return DRVMGR_OK; |
---|
| 519 | } |
---|
| 520 | |
---|
| 521 | /******************* Driver Implementation ***********************/ |
---|
| 522 | |
---|
| 523 | int occan_register_io(rtems_device_major_number *m) |
---|
| 524 | { |
---|
| 525 | rtems_status_code r; |
---|
| 526 | |
---|
| 527 | if ((r = rtems_io_register_driver(0, &occan_driver, m)) == RTEMS_SUCCESSFUL) { |
---|
| 528 | DBG("OCCAN driver successfully registered, major: %d\n", *m); |
---|
| 529 | } else { |
---|
| 530 | switch(r) { |
---|
| 531 | case RTEMS_TOO_MANY: |
---|
| 532 | printk("OCCAN rtems_io_register_driver failed: RTEMS_TOO_MANY\n"); |
---|
| 533 | return -1; |
---|
| 534 | case RTEMS_INVALID_NUMBER: |
---|
| 535 | printk("OCCAN rtems_io_register_driver failed: RTEMS_INVALID_NUMBER\n"); |
---|
| 536 | return -1; |
---|
| 537 | case RTEMS_RESOURCE_IN_USE: |
---|
| 538 | printk("OCCAN rtems_io_register_driver failed: RTEMS_RESOURCE_IN_USE\n"); |
---|
| 539 | return -1; |
---|
| 540 | default: |
---|
| 541 | printk("OCCAN rtems_io_register_driver failed\n"); |
---|
| 542 | return -1; |
---|
| 543 | } |
---|
| 544 | } |
---|
| 545 | return 0; |
---|
| 546 | } |
---|
| 547 | |
---|
| 548 | int occan_device_init(occan_priv *pDev) |
---|
| 549 | { |
---|
| 550 | struct amba_dev_info *ambadev; |
---|
| 551 | struct ambapp_core *pnpinfo; |
---|
| 552 | rtems_status_code status; |
---|
| 553 | int minor; |
---|
| 554 | |
---|
| 555 | /* Get device information from AMBA PnP information */ |
---|
| 556 | ambadev = (struct amba_dev_info *)pDev->dev->businfo; |
---|
| 557 | if ( ambadev == NULL ) { |
---|
| 558 | return -1; |
---|
| 559 | } |
---|
| 560 | pnpinfo = &ambadev->info; |
---|
| 561 | pDev->irq = pnpinfo->irq; |
---|
| 562 | pDev->regs = (pelican_regs *)(pnpinfo->ahb_slv->start[0] + OCCAN_NCORE_OFS*pnpinfo->index); |
---|
| 563 | pDev->byte_regs = 1; |
---|
| 564 | minor = pDev->dev->minor_drv; |
---|
| 565 | |
---|
| 566 | /* Get frequency in Hz */ |
---|
| 567 | if ( drvmgr_freq_get(pDev->dev, DEV_AHB_SLV, &pDev->sys_freq_hz) ) { |
---|
| 568 | return -1; |
---|
| 569 | } |
---|
| 570 | |
---|
| 571 | DBG("OCCAN frequency: %d Hz\n", pDev->sys_freq_hz); |
---|
| 572 | |
---|
| 573 | /* initialize software */ |
---|
| 574 | pDev->open = 0; |
---|
| 575 | pDev->started = 0; /* Needed for spurious interrupts */ |
---|
| 576 | pDev->rxfifo = NULL; |
---|
| 577 | pDev->txfifo = NULL; |
---|
| 578 | status = rtems_semaphore_create( |
---|
| 579 | rtems_build_name('C', 'd', 'v', '0'+minor), |
---|
| 580 | 1, |
---|
| 581 | RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_NO_INHERIT_PRIORITY | \ |
---|
| 582 | RTEMS_NO_PRIORITY_CEILING, |
---|
| 583 | 0, |
---|
| 584 | &pDev->devsem); |
---|
| 585 | if ( status != RTEMS_SUCCESSFUL ){ |
---|
| 586 | printk("OCCAN[%d]: Failed to create dev semaphore, (%d)\n\r",minor, status); |
---|
| 587 | return RTEMS_UNSATISFIED; |
---|
| 588 | } |
---|
| 589 | status = rtems_semaphore_create( |
---|
| 590 | rtems_build_name('C', 't', 'x', '0'+minor), |
---|
| 591 | 0, |
---|
| 592 | RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_NO_INHERIT_PRIORITY | \ |
---|
| 593 | RTEMS_NO_PRIORITY_CEILING, |
---|
| 594 | 0, |
---|
| 595 | &pDev->txsem); |
---|
| 596 | if ( status != RTEMS_SUCCESSFUL ){ |
---|
| 597 | printk("OCCAN[%d]: Failed to create tx semaphore, (%d)\n\r",minor, status); |
---|
| 598 | return RTEMS_UNSATISFIED; |
---|
| 599 | } |
---|
| 600 | status = rtems_semaphore_create( |
---|
| 601 | rtems_build_name('C', 'r', 'x', '0'+minor), |
---|
| 602 | 0, |
---|
| 603 | RTEMS_FIFO | RTEMS_SIMPLE_BINARY_SEMAPHORE | RTEMS_NO_INHERIT_PRIORITY | \ |
---|
| 604 | RTEMS_NO_PRIORITY_CEILING, |
---|
| 605 | 0, |
---|
| 606 | &pDev->rxsem); |
---|
| 607 | if ( status != RTEMS_SUCCESSFUL ){ |
---|
| 608 | printk("OCCAN[%d]: Failed to create rx semaphore, (%d)\n\r",minor, status); |
---|
| 609 | return RTEMS_UNSATISFIED; |
---|
| 610 | } |
---|
| 611 | |
---|
| 612 | /* hardware init/reset */ |
---|
| 613 | pelican_init(pDev); |
---|
| 614 | |
---|
| 615 | #ifdef DEBUG_PRINT_REGMAP |
---|
| 616 | pelican_regadr_print(pDev->regs); |
---|
| 617 | #endif |
---|
| 618 | |
---|
| 619 | return 0; |
---|
| 620 | } |
---|
| 621 | |
---|
| 622 | |
---|
| 623 | #ifdef DEBUG |
---|
| 624 | static void pelican_regs_print(occan_priv *pDev){ |
---|
| 625 | pelican_regs *regs = pDev->regs; |
---|
| 626 | printk("--- PELICAN 0x%lx ---\n\r",(unsigned int)regs); |
---|
| 627 | printk(" MODE: 0x%02x\n\r",READ_REG(pDev, ®s->mode)); |
---|
| 628 | printk(" CMD: 0x%02x\n\r",READ_REG(pDev, ®s->cmd)); |
---|
| 629 | printk(" STATUS: 0x%02x\n\r",READ_REG(pDev, ®s->status)); |
---|
| 630 | /*printk(" INTFLG: 0x%02x\n\r",READ_REG(pDev, ®s->intflags));*/ |
---|
| 631 | printk(" INTEN: 0x%02x\n\r",READ_REG(pDev, ®s->inten)); |
---|
| 632 | printk(" BTR0: 0x%02x\n\r",READ_REG(pDev, ®s->bustim0)); |
---|
| 633 | printk(" BTR1: 0x%02x\n\r",READ_REG(pDev, ®s->bustim1)); |
---|
| 634 | printk(" ARBCODE: 0x%02x\n\r",READ_REG(pDev, ®s->arbcode)); |
---|
| 635 | printk(" ERRCODE: 0x%02x\n\r",READ_REG(pDev, ®s->errcode)); |
---|
| 636 | printk(" ERRWARN: 0x%02x\n\r",READ_REG(pDev, ®s->errwarn)); |
---|
| 637 | printk(" RX_ERR_CNT: 0x%02x\n\r",READ_REG(pDev, ®s->rx_err_cnt)); |
---|
| 638 | printk(" TX_ERR_CNT: 0x%02x\n\r",READ_REG(pDev, ®s->tx_err_cnt)); |
---|
| 639 | if ( READ_REG(pDev, ®s->mode) & PELICAN_MOD_RESET ){ |
---|
| 640 | /* in reset mode it is possible to read acceptance filters */ |
---|
| 641 | printk(" ACR0: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->rx_fi_xff),®s->rx_fi_xff); |
---|
| 642 | printk(" ACR1: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.code[0]),(unsigned int)®s->msg.rst_accept.code[0]); |
---|
| 643 | printk(" ACR1: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.code[1]),(unsigned int)®s->msg.rst_accept.code[1]); |
---|
| 644 | printk(" ACR1: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.code[2]),(unsigned int)®s->msg.rst_accept.code[2]); |
---|
| 645 | printk(" AMR0: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.mask[0]),(unsigned int)®s->msg.rst_accept.mask[0]); |
---|
| 646 | printk(" AMR1: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.mask[1]),(unsigned int)®s->msg.rst_accept.mask[1]); |
---|
| 647 | printk(" AMR2: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.mask[2]),(unsigned int)®s->msg.rst_accept.mask[2]); |
---|
| 648 | printk(" AMR3: 0x%02x (0x%lx)\n\r",READ_REG(pDev, ®s->msg.rst_accept.mask[3]),(unsigned int)®s->msg.rst_accept.mask[3]); |
---|
| 649 | |
---|
| 650 | }else{ |
---|
| 651 | printk(" RXFI_XFF: 0x%02x\n\r",READ_REG(pDev, ®s->rx_fi_xff)); |
---|
| 652 | } |
---|
| 653 | printk(" RX_MSG_CNT: 0x%02x\n\r",READ_REG(pDev, ®s->rx_msg_cnt)); |
---|
| 654 | printk(" CLKDIV: 0x%02x\n\r",READ_REG(pDev, ®s->clkdiv)); |
---|
| 655 | printk("-------------------\n\r"); |
---|
| 656 | } |
---|
| 657 | #endif |
---|
| 658 | |
---|
| 659 | #ifdef DEBUG_PRINT_REGMAP |
---|
| 660 | static void pelican_regadr_print(pelican_regs *regs){ |
---|
| 661 | printk("--- PELICAN 0x%lx ---\n\r",(unsigned int)regs); |
---|
| 662 | printk(" MODE: 0x%lx\n\r",(unsigned int)®s->mode); |
---|
| 663 | printk(" CMD: 0x%lx\n\r",(unsigned int)®s->cmd); |
---|
| 664 | printk(" STATUS: 0x%lx\n\r",(unsigned int)®s->status); |
---|
| 665 | /*printk(" INTFLG: 0x%lx\n\r",®s->intflags);*/ |
---|
| 666 | printk(" INTEN: 0x%lx\n\r",(unsigned int)®s->inten); |
---|
| 667 | printk(" BTR0: 0x%lx\n\r",(unsigned int)®s->bustim0); |
---|
| 668 | printk(" BTR1: 0x%lx\n\r",(unsigned int)®s->bustim1); |
---|
| 669 | printk(" ARBCODE: 0x%lx\n\r",(unsigned int)®s->arbcode); |
---|
| 670 | printk(" ERRCODE: 0x%lx\n\r",(unsigned int)®s->errcode); |
---|
| 671 | printk(" ERRWARN: 0x%lx\n\r",(unsigned int)®s->errwarn); |
---|
| 672 | printk(" RX_ERR_CNT: 0x%lx\n\r",(unsigned int)®s->rx_err_cnt); |
---|
| 673 | printk(" TX_ERR_CNT: 0x%lx\n\r",(unsigned int)®s->tx_err_cnt); |
---|
| 674 | |
---|
| 675 | /* in reset mode it is possible to read acceptance filters */ |
---|
| 676 | printk(" RXFI_XFF: 0x%lx\n\r",(unsigned int)®s->rx_fi_xff); |
---|
| 677 | |
---|
| 678 | /* reset registers */ |
---|
| 679 | printk(" ACR0: 0x%lx\n\r",(unsigned int)®s->rx_fi_xff); |
---|
| 680 | printk(" ACR1: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.code[0]); |
---|
| 681 | printk(" ACR2: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.code[1]); |
---|
| 682 | printk(" ACR3: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.code[2]); |
---|
| 683 | printk(" AMR0: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.mask[0]); |
---|
| 684 | printk(" AMR1: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.mask[1]); |
---|
| 685 | printk(" AMR2: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.mask[2]); |
---|
| 686 | printk(" AMR3: 0x%lx\n\r",(unsigned int)®s->msg.rst_accept.mask[3]); |
---|
| 687 | |
---|
| 688 | /* TX Extended */ |
---|
| 689 | printk(" EFFTX_ID[0]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.id[0]); |
---|
| 690 | printk(" EFFTX_ID[1]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.id[1]); |
---|
| 691 | printk(" EFFTX_ID[2]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.id[2]); |
---|
| 692 | printk(" EFFTX_ID[3]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.id[3]); |
---|
| 693 | |
---|
| 694 | printk(" EFFTX_DATA[0]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[0]); |
---|
| 695 | printk(" EFFTX_DATA[1]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[1]); |
---|
| 696 | printk(" EFFTX_DATA[2]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[2]); |
---|
| 697 | printk(" EFFTX_DATA[3]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[3]); |
---|
| 698 | printk(" EFFTX_DATA[4]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[4]); |
---|
| 699 | printk(" EFFTX_DATA[5]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[5]); |
---|
| 700 | printk(" EFFTX_DATA[6]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[6]); |
---|
| 701 | printk(" EFFTX_DATA[7]: 0x%lx\n\r",(unsigned int)®s->msg.tx_eff.data[7]); |
---|
| 702 | |
---|
| 703 | /* RX Extended */ |
---|
| 704 | printk(" EFFRX_ID[0]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.id[0]); |
---|
| 705 | printk(" EFFRX_ID[1]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.id[1]); |
---|
| 706 | printk(" EFFRX_ID[2]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.id[2]); |
---|
| 707 | printk(" EFFRX_ID[3]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.id[3]); |
---|
| 708 | |
---|
| 709 | printk(" EFFRX_DATA[0]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[0]); |
---|
| 710 | printk(" EFFRX_DATA[1]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[1]); |
---|
| 711 | printk(" EFFRX_DATA[2]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[2]); |
---|
| 712 | printk(" EFFRX_DATA[3]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[3]); |
---|
| 713 | printk(" EFFRX_DATA[4]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[4]); |
---|
| 714 | printk(" EFFRX_DATA[5]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[5]); |
---|
| 715 | printk(" EFFRX_DATA[6]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[6]); |
---|
| 716 | printk(" EFFRX_DATA[7]: 0x%lx\n\r",(unsigned int)®s->msg.rx_eff.data[7]); |
---|
| 717 | |
---|
| 718 | |
---|
| 719 | /* RX Extended */ |
---|
| 720 | printk(" SFFRX_ID[0]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.id[0]); |
---|
| 721 | printk(" SFFRX_ID[1]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.id[1]); |
---|
| 722 | |
---|
| 723 | printk(" SFFRX_DATA[0]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[0]); |
---|
| 724 | printk(" SFFRX_DATA[1]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[1]); |
---|
| 725 | printk(" SFFRX_DATA[2]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[2]); |
---|
| 726 | printk(" SFFRX_DATA[3]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[3]); |
---|
| 727 | printk(" SFFRX_DATA[4]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[4]); |
---|
| 728 | printk(" SFFRX_DATA[5]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[5]); |
---|
| 729 | printk(" SFFRX_DATA[6]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[6]); |
---|
| 730 | printk(" SFFRX_DATA[7]: 0x%lx\n\r",(unsigned int)®s->msg.rx_sff.data[7]); |
---|
| 731 | |
---|
| 732 | /* TX Extended */ |
---|
| 733 | printk(" SFFTX_ID[0]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.id[0]); |
---|
| 734 | printk(" SFFTX_ID[1]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.id[1]); |
---|
| 735 | |
---|
| 736 | printk(" SFFTX_DATA[0]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[0]); |
---|
| 737 | printk(" SFFTX_DATA[1]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[1]); |
---|
| 738 | printk(" SFFTX_DATA[2]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[2]); |
---|
| 739 | printk(" SFFTX_DATA[3]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[3]); |
---|
| 740 | printk(" SFFTX_DATA[4]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[4]); |
---|
| 741 | printk(" SFFTX_DATA[5]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[5]); |
---|
| 742 | printk(" SFFTX_DATA[6]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[6]); |
---|
| 743 | printk(" SFFTX_DATA[7]: 0x%lx\n\r",(unsigned int)®s->msg.tx_sff.data[7]); |
---|
| 744 | |
---|
| 745 | printk(" RX_MSG_CNT: 0x%lx\n\r",(unsigned int)®s->rx_msg_cnt); |
---|
| 746 | printk(" CLKDIV: 0x%lx\n\r",(unsigned int)®s->clkdiv); |
---|
| 747 | printk("-------------------\n\r"); |
---|
| 748 | } |
---|
| 749 | #endif |
---|
| 750 | |
---|
| 751 | #ifdef DEBUG |
---|
| 752 | static void occan_stat_print(occan_stats *stats){ |
---|
| 753 | printk("----Stats----\n\r"); |
---|
| 754 | printk("rx_msgs: %d\n\r",stats->rx_msgs); |
---|
| 755 | printk("tx_msgs: %d\n\r",stats->tx_msgs); |
---|
| 756 | printk("err_warn: %d\n\r",stats->err_warn); |
---|
| 757 | printk("err_dovr: %d\n\r",stats->err_dovr); |
---|
| 758 | printk("err_errp: %d\n\r",stats->err_errp); |
---|
| 759 | printk("err_arb: %d\n\r",stats->err_arb); |
---|
| 760 | printk("err_bus: %d\n\r",stats->err_bus); |
---|
| 761 | printk("Int cnt: %d\n\r",stats->ints); |
---|
| 762 | printk("tx_buf_err: %d\n\r",stats->tx_buf_error); |
---|
| 763 | printk("-------------\n\r"); |
---|
| 764 | } |
---|
| 765 | #endif |
---|
| 766 | |
---|
[226455f] | 767 | static void pelican_init(occan_priv *priv){ |
---|
| 768 | /* Reset core */ |
---|
[3681925] | 769 | WRITE_REG(priv, &priv->regs->mode, PELICAN_MOD_RESET); |
---|
[44b06ca] | 770 | |
---|
[226455f] | 771 | /* wait for core to reset complete */ |
---|
| 772 | /*usleep(1);*/ |
---|
| 773 | } |
---|
| 774 | |
---|
| 775 | static void pelican_open(occan_priv *priv){ |
---|
| 776 | int ret; |
---|
| 777 | |
---|
| 778 | /* Set defaults */ |
---|
| 779 | priv->speed = OCCAN_SPEED_250K; |
---|
| 780 | |
---|
| 781 | /* set acceptance filters to accept all messages */ |
---|
| 782 | priv->acode[0] = 0; |
---|
| 783 | priv->acode[1] = 0; |
---|
| 784 | priv->acode[2] = 0; |
---|
| 785 | priv->acode[3] = 0; |
---|
| 786 | priv->amask[0] = 0xff; |
---|
| 787 | priv->amask[1] = 0xff; |
---|
| 788 | priv->amask[2] = 0xff; |
---|
| 789 | priv->amask[3] = 0xff; |
---|
[44b06ca] | 790 | |
---|
[226455f] | 791 | /* Set clock divider to extended mode, clkdiv not connected |
---|
| 792 | */ |
---|
[3681925] | 793 | WRITE_REG(priv, &priv->regs->clkdiv, (1<<PELICAN_CDR_MODE_BITS) | (DEFAULT_CLKDIV & PELICAN_CDR_DIV)); |
---|
[44b06ca] | 794 | |
---|
[3681925] | 795 | ret = occan_calc_speedregs(priv->sys_freq_hz,priv->speed,&priv->timing); |
---|
[226455f] | 796 | if ( ret ){ |
---|
| 797 | /* failed to set speed for this system freq, try with 50K instead */ |
---|
| 798 | priv->speed = OCCAN_SPEED_50K; |
---|
[3681925] | 799 | occan_calc_speedregs(priv->sys_freq_hz, priv->speed, |
---|
| 800 | &priv->timing); |
---|
[226455f] | 801 | } |
---|
[44b06ca] | 802 | |
---|
[226455f] | 803 | /* disable all interrupts */ |
---|
[3681925] | 804 | WRITE_REG(priv, &priv->regs->inten, 0); |
---|
[44b06ca] | 805 | |
---|
[226455f] | 806 | /* clear pending interrupts by reading */ |
---|
[3681925] | 807 | READ_REG(priv, &priv->regs->intflags); |
---|
[226455f] | 808 | } |
---|
| 809 | |
---|
| 810 | static int pelican_start(occan_priv *priv){ |
---|
| 811 | /* Start HW communication */ |
---|
[44b06ca] | 812 | |
---|
[226455f] | 813 | if ( !priv->rxfifo || !priv->txfifo ) |
---|
| 814 | return -1; |
---|
| 815 | |
---|
[3681925] | 816 | /* In case we were started before and stopped we |
---|
| 817 | * should empty the TX fifo or try to resend those |
---|
| 818 | * messages. We make it simple... |
---|
| 819 | */ |
---|
| 820 | occan_fifo_clr(priv->txfifo); |
---|
[44b06ca] | 821 | |
---|
[226455f] | 822 | /* Clear status bits */ |
---|
| 823 | priv->status = 0; |
---|
[3681925] | 824 | priv->sending = 0; |
---|
[44b06ca] | 825 | |
---|
[226455f] | 826 | /* clear pending interrupts */ |
---|
[3681925] | 827 | READ_REG(priv, &priv->regs->intflags); |
---|
[44b06ca] | 828 | |
---|
[226455f] | 829 | /* clear error counters */ |
---|
[3681925] | 830 | WRITE_REG(priv, &priv->regs->rx_err_cnt, 0); |
---|
| 831 | WRITE_REG(priv, &priv->regs->tx_err_cnt, 0); |
---|
[226455f] | 832 | |
---|
| 833 | #ifdef REDUNDANT_CHANNELS |
---|
| 834 | if ( (priv->channel == 0) || (priv->channel >= REDUNDANT_CHANNELS) ){ |
---|
| 835 | /* Select the first (default) channel */ |
---|
| 836 | OCCAN_SET_CHANNEL(priv,0); |
---|
| 837 | }else{ |
---|
| 838 | /* set gpio bit, or something */ |
---|
| 839 | OCCAN_SET_CHANNEL(priv,priv->channel); |
---|
| 840 | } |
---|
| 841 | #endif |
---|
| 842 | /* set the speed regs of the CAN core */ |
---|
| 843 | occan_set_speedregs(priv,&priv->timing); |
---|
[44b06ca] | 844 | |
---|
[3681925] | 845 | DBG("OCCAN: start: set timing regs btr0: 0x%x, btr1: 0x%x\n\r", |
---|
| 846 | READ_REG(priv, &priv->regs->bustim0), |
---|
| 847 | READ_REG(priv, &priv->regs->bustim1)); |
---|
[44b06ca] | 848 | |
---|
[226455f] | 849 | /* Set default acceptance filter */ |
---|
| 850 | pelican_set_accept(priv,priv->acode,priv->amask); |
---|
| 851 | |
---|
[3681925] | 852 | /* Nothing can fail from here, this must be set before interrupts are |
---|
| 853 | * enabled */ |
---|
| 854 | priv->started = 1; |
---|
[44b06ca] | 855 | |
---|
[3681925] | 856 | /* turn on interrupts */ |
---|
| 857 | WRITE_REG(priv, &priv->regs->inten, |
---|
| 858 | PELICAN_IE_RX | PELICAN_IE_TX | PELICAN_IE_ERRW | |
---|
| 859 | PELICAN_IE_ERRP | PELICAN_IE_BUS); |
---|
[226455f] | 860 | #ifdef DEBUG |
---|
| 861 | /* print setup before starting */ |
---|
| 862 | pelican_regs_print(priv->regs); |
---|
| 863 | occan_stat_print(&priv->stats); |
---|
| 864 | #endif |
---|
[44b06ca] | 865 | |
---|
| 866 | /* core already in reset mode, |
---|
[3681925] | 867 | * € Exit reset mode |
---|
[226455f] | 868 | * € Enter Single/Dual mode filtering. |
---|
| 869 | */ |
---|
[3681925] | 870 | WRITE_REG(priv, &priv->regs->mode, (priv->single_mode << 3)); |
---|
| 871 | |
---|
| 872 | /* Register interrupt routine and unmask IRQ at IRQ controller */ |
---|
| 873 | drvmgr_interrupt_register(priv->dev, 0, "occan", occan_interrupt, priv); |
---|
[44b06ca] | 874 | |
---|
[226455f] | 875 | return 0; |
---|
| 876 | } |
---|
| 877 | |
---|
[3681925] | 878 | static void pelican_stop(occan_priv *priv) |
---|
| 879 | { |
---|
[226455f] | 880 | /* stop HW */ |
---|
| 881 | |
---|
[3681925] | 882 | drvmgr_interrupt_unregister(priv->dev, 0, occan_interrupt, priv); |
---|
| 883 | |
---|
[226455f] | 884 | #ifdef DEBUG |
---|
| 885 | /* print setup before stopping */ |
---|
| 886 | pelican_regs_print(priv->regs); |
---|
| 887 | occan_stat_print(&priv->stats); |
---|
| 888 | #endif |
---|
[44b06ca] | 889 | |
---|
[226455f] | 890 | /* put core in reset mode */ |
---|
[3681925] | 891 | WRITE_REG(priv, &priv->regs->mode, PELICAN_MOD_RESET); |
---|
[226455f] | 892 | |
---|
| 893 | /* turn off interrupts */ |
---|
[3681925] | 894 | WRITE_REG(priv, &priv->regs->inten, 0); |
---|
[44b06ca] | 895 | |
---|
[226455f] | 896 | priv->status |= OCCAN_STATUS_RESET; |
---|
| 897 | } |
---|
| 898 | |
---|
[3681925] | 899 | static inline int pelican_tx_ready(occan_priv *can) |
---|
| 900 | { |
---|
| 901 | unsigned char status; |
---|
| 902 | pelican_regs *regs = can->regs; |
---|
| 903 | |
---|
| 904 | /* is there room in send buffer? */ |
---|
| 905 | status = READ_REG(can, ®s->status); |
---|
| 906 | if ( !(status & PELICAN_STAT_TXBUF) ) { |
---|
| 907 | /* tx fifo taken, we have to wait */ |
---|
| 908 | return 0; |
---|
| 909 | } |
---|
| 910 | |
---|
| 911 | return 1; |
---|
| 912 | } |
---|
[226455f] | 913 | |
---|
[44b06ca] | 914 | /* Try to send message "msg", if hardware txfifo is |
---|
[226455f] | 915 | * full, then -1 is returned. |
---|
| 916 | * |
---|
[44b06ca] | 917 | * Be sure to have disabled CAN interrupts when |
---|
[226455f] | 918 | * entering this function. |
---|
| 919 | */ |
---|
| 920 | static int pelican_send(occan_priv *can, CANMsg *msg){ |
---|
[3681925] | 921 | unsigned char tmp; |
---|
[226455f] | 922 | pelican_regs *regs = can->regs; |
---|
[44b06ca] | 923 | |
---|
[226455f] | 924 | /* is there room in send buffer? */ |
---|
[3681925] | 925 | if ( !pelican_tx_ready(can) ) { |
---|
[226455f] | 926 | /* tx fifo taken, we have to wait */ |
---|
| 927 | return -1; |
---|
| 928 | } |
---|
[44b06ca] | 929 | |
---|
[226455f] | 930 | tmp = msg->len & 0xf; |
---|
| 931 | if ( msg->rtr ) |
---|
| 932 | tmp |= 0x40; |
---|
[44b06ca] | 933 | |
---|
[226455f] | 934 | if ( msg->extended ){ |
---|
| 935 | /* Extended Frame */ |
---|
[3681925] | 936 | WRITE_REG(can, ®s->rx_fi_xff, 0x80 | tmp); |
---|
| 937 | WRITE_REG(can, ®s->msg.tx_eff.id[0],(msg->id >> (5+8+8)) & 0xff); |
---|
| 938 | WRITE_REG(can, ®s->msg.tx_eff.id[1],(msg->id >> (5+8)) & 0xff); |
---|
| 939 | WRITE_REG(can, ®s->msg.tx_eff.id[2],(msg->id >> (5)) & 0xff); |
---|
| 940 | WRITE_REG(can, ®s->msg.tx_eff.id[3],(msg->id << 3) & 0xf8); |
---|
[226455f] | 941 | tmp = msg->len; |
---|
| 942 | while(tmp--){ |
---|
[3681925] | 943 | WRITE_REG(can, ®s->msg.tx_eff.data[tmp], msg->data[tmp]); |
---|
[226455f] | 944 | } |
---|
| 945 | }else{ |
---|
| 946 | /* Standard Frame */ |
---|
[3681925] | 947 | WRITE_REG(can, ®s->rx_fi_xff, tmp); |
---|
| 948 | WRITE_REG(can, ®s->msg.tx_sff.id[0],(msg->id >> 3) & 0xff); |
---|
| 949 | WRITE_REG(can, ®s->msg.tx_sff.id[1],(msg->id << 5) & 0xe0); |
---|
[226455f] | 950 | tmp = msg->len; |
---|
| 951 | while(tmp--){ |
---|
[3681925] | 952 | WRITE_REG(can, ®s->msg.tx_sff.data[tmp],msg->data[tmp]); |
---|
[226455f] | 953 | } |
---|
| 954 | } |
---|
[44b06ca] | 955 | |
---|
[226455f] | 956 | /* let HW know of new message */ |
---|
| 957 | if ( msg->sshot ){ |
---|
[3681925] | 958 | WRITE_REG(can, ®s->cmd, PELICAN_CMD_TXREQ | PELICAN_CMD_ABORT); |
---|
[226455f] | 959 | }else{ |
---|
| 960 | /* normal case -- try resend until sent */ |
---|
[3681925] | 961 | WRITE_REG(can, ®s->cmd, PELICAN_CMD_TXREQ); |
---|
[226455f] | 962 | } |
---|
[44b06ca] | 963 | |
---|
[226455f] | 964 | return 0; |
---|
| 965 | } |
---|
| 966 | |
---|
| 967 | |
---|
[3681925] | 968 | static void pelican_set_accept(occan_priv *priv, unsigned char *acode, unsigned char *amask) |
---|
| 969 | { |
---|
[226455f] | 970 | unsigned char *acode0, *acode1, *acode2, *acode3; |
---|
| 971 | unsigned char *amask0, *amask1, *amask2, *amask3; |
---|
[44b06ca] | 972 | |
---|
[226455f] | 973 | acode0 = &priv->regs->rx_fi_xff; |
---|
| 974 | acode1 = (unsigned char *)&priv->regs->msg.rst_accept.code[0]; |
---|
| 975 | acode2 = (unsigned char *)&priv->regs->msg.rst_accept.code[1]; |
---|
| 976 | acode3 = (unsigned char *)&priv->regs->msg.rst_accept.code[2]; |
---|
[44b06ca] | 977 | |
---|
[226455f] | 978 | amask0 = (unsigned char *)&priv->regs->msg.rst_accept.mask[0]; |
---|
| 979 | amask1 = (unsigned char *)&priv->regs->msg.rst_accept.mask[1]; |
---|
| 980 | amask2 = (unsigned char *)&priv->regs->msg.rst_accept.mask[2]; |
---|
| 981 | amask3 = (unsigned char *)&priv->regs->msg.rst_accept.mask[3]; |
---|
[44b06ca] | 982 | |
---|
[226455f] | 983 | /* Set new mask & code */ |
---|
[3681925] | 984 | WRITE_REG(priv, acode0, acode[0]); |
---|
| 985 | WRITE_REG(priv, acode1, acode[1]); |
---|
| 986 | WRITE_REG(priv, acode2, acode[2]); |
---|
| 987 | WRITE_REG(priv, acode3, acode[3]); |
---|
| 988 | |
---|
| 989 | WRITE_REG(priv, amask0, amask[0]); |
---|
| 990 | WRITE_REG(priv, amask1, amask[1]); |
---|
| 991 | WRITE_REG(priv, amask2, amask[2]); |
---|
| 992 | WRITE_REG(priv, amask3, amask[3]); |
---|
[226455f] | 993 | } |
---|
| 994 | |
---|
| 995 | |
---|
[0743eae] | 996 | /* This function calculates BTR0 and BTR1 values for a given bitrate. |
---|
[226455f] | 997 | * |
---|
| 998 | * Set communication parameters. |
---|
[0743eae] | 999 | * \param clock_hz OC_CAN Core frequency in Hz. |
---|
| 1000 | * \param rate Requested baud rate in bits/second. |
---|
| 1001 | * \param result Pointer to where resulting BTRs will be stored. |
---|
| 1002 | * \return zero if successful to calculate a baud rate. |
---|
[226455f] | 1003 | */ |
---|
[3681925] | 1004 | static int occan_calc_speedregs(unsigned int clock_hz, unsigned int rate, occan_speed_regs *result) |
---|
| 1005 | { |
---|
[226455f] | 1006 | int best_error = 1000000000; |
---|
| 1007 | int error; |
---|
[946c391] | 1008 | int best_tseg=0, best_brp=0, brp=0; |
---|
[226455f] | 1009 | int tseg=0, tseg1=0, tseg2=0; |
---|
| 1010 | int sjw = 0; |
---|
| 1011 | int clock = clock_hz / 2; |
---|
| 1012 | int sampl_pt = 90; |
---|
| 1013 | |
---|
[0743eae] | 1014 | if ( (rate<5000) || (rate>1000000) ){ |
---|
[226455f] | 1015 | /* invalid speed mode */ |
---|
| 1016 | return -1; |
---|
| 1017 | } |
---|
[44b06ca] | 1018 | |
---|
| 1019 | /* find best match, return -2 if no good reg |
---|
[226455f] | 1020 | * combination is available for this frequency */ |
---|
| 1021 | |
---|
| 1022 | /* some heuristic specials */ |
---|
| 1023 | if (rate > ((1000000 + 500000) / 2)) |
---|
| 1024 | sampl_pt = 75; |
---|
| 1025 | |
---|
| 1026 | if (rate < ((12500 + 10000) / 2)) |
---|
| 1027 | sampl_pt = 75; |
---|
| 1028 | |
---|
| 1029 | if (rate < ((100000 + 125000) / 2)) |
---|
| 1030 | sjw = 1; |
---|
| 1031 | |
---|
| 1032 | /* tseg even = round down, odd = round up */ |
---|
| 1033 | for (tseg = (0 + 0 + 2) * 2; |
---|
| 1034 | tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1; |
---|
| 1035 | tseg++) |
---|
| 1036 | { |
---|
| 1037 | brp = clock / ((1 + tseg / 2) * rate) + tseg % 2; |
---|
| 1038 | if ((brp == 0) || (brp > 64)) |
---|
| 1039 | continue; |
---|
| 1040 | |
---|
| 1041 | error = rate - clock / (brp * (1 + tseg / 2)); |
---|
| 1042 | if (error < 0) |
---|
| 1043 | { |
---|
| 1044 | error = -error; |
---|
| 1045 | } |
---|
| 1046 | |
---|
| 1047 | if (error <= best_error) |
---|
| 1048 | { |
---|
| 1049 | best_error = error; |
---|
| 1050 | best_tseg = tseg/2; |
---|
| 1051 | best_brp = brp-1; |
---|
| 1052 | } |
---|
| 1053 | } |
---|
| 1054 | |
---|
| 1055 | if (best_error && (rate / best_error < 10)) |
---|
| 1056 | { |
---|
| 1057 | printk("OCCAN: bitrate %d is not possible with %d Hz clock\n\r",rate, clock); |
---|
| 1058 | return -2; |
---|
| 1059 | }else if ( !result ) |
---|
| 1060 | return 0; /* nothing to store result in, but a valid bitrate can be calculated */ |
---|
| 1061 | |
---|
| 1062 | tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100; |
---|
| 1063 | |
---|
| 1064 | if (tseg2 < 0) |
---|
| 1065 | { |
---|
| 1066 | tseg2 = 0; |
---|
| 1067 | } |
---|
| 1068 | |
---|
| 1069 | if (tseg2 > MAX_TSEG2) |
---|
| 1070 | { |
---|
| 1071 | tseg2 = MAX_TSEG2; |
---|
| 1072 | } |
---|
| 1073 | |
---|
| 1074 | tseg1 = best_tseg - tseg2 - 2; |
---|
| 1075 | |
---|
| 1076 | if (tseg1 > MAX_TSEG1) |
---|
| 1077 | { |
---|
| 1078 | tseg1 = MAX_TSEG1; |
---|
| 1079 | tseg2 = best_tseg - tseg1 - 2; |
---|
| 1080 | } |
---|
[0743eae] | 1081 | |
---|
[226455f] | 1082 | result->btr0 = (sjw<<OCCAN_BUSTIM_SJW_BIT) | (best_brp&OCCAN_BUSTIM_BRP); |
---|
| 1083 | result->btr1 = (0<<7) | (tseg2<<OCCAN_BUSTIM_TSEG2_BIT) | tseg1; |
---|
[44b06ca] | 1084 | |
---|
[226455f] | 1085 | return 0; |
---|
| 1086 | } |
---|
| 1087 | |
---|
[3681925] | 1088 | static int occan_set_speedregs(occan_priv *priv, occan_speed_regs *timing) |
---|
| 1089 | { |
---|
[226455f] | 1090 | if ( !timing || !priv || !priv->regs) |
---|
| 1091 | return -1; |
---|
[44b06ca] | 1092 | |
---|
[3681925] | 1093 | WRITE_REG(priv, &priv->regs->bustim0, timing->btr0); |
---|
| 1094 | WRITE_REG(priv, &priv->regs->bustim1, timing->btr1); |
---|
| 1095 | |
---|
[226455f] | 1096 | return 0; |
---|
| 1097 | } |
---|
| 1098 | |
---|
[3681925] | 1099 | static rtems_device_driver occan_initialize(rtems_device_major_number major, rtems_device_minor_number unused, void *arg) |
---|
| 1100 | { |
---|
[226455f] | 1101 | return RTEMS_SUCCESSFUL; |
---|
| 1102 | } |
---|
| 1103 | |
---|
[a8595605] | 1104 | static rtems_device_driver occan_open(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) |
---|
| 1105 | { |
---|
[226455f] | 1106 | occan_priv *can; |
---|
[3681925] | 1107 | struct drvmgr_dev *dev; |
---|
[44b06ca] | 1108 | |
---|
[226455f] | 1109 | DBG("OCCAN: Opening %d\n\r",minor); |
---|
[44b06ca] | 1110 | |
---|
[3681925] | 1111 | /* get can device */ |
---|
| 1112 | if ( drvmgr_get_dev(&occan_drv_info.general, minor, &dev) ) { |
---|
| 1113 | DBG("Wrong minor %d\n", minor); |
---|
[226455f] | 1114 | return RTEMS_UNSATISFIED; /* NODEV */ |
---|
[3681925] | 1115 | } |
---|
| 1116 | can = (occan_priv *)dev->priv; |
---|
[44b06ca] | 1117 | |
---|
[226455f] | 1118 | /* already opened? */ |
---|
[a8595605] | 1119 | rtems_semaphore_obtain(can->devsem, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
---|
[226455f] | 1120 | if ( can->open ){ |
---|
| 1121 | rtems_semaphore_release(can->devsem); |
---|
| 1122 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
| 1123 | } |
---|
| 1124 | can->open = 1; |
---|
| 1125 | rtems_semaphore_release(can->devsem); |
---|
| 1126 | |
---|
[a8595605] | 1127 | SPIN_INIT(&can->devlock, can->devName); |
---|
| 1128 | |
---|
[226455f] | 1129 | /* allocate fifos */ |
---|
| 1130 | can->rxfifo = occan_fifo_create(DEFAULT_RX_FIFO_LEN); |
---|
| 1131 | if ( !can->rxfifo ){ |
---|
| 1132 | can->open = 0; |
---|
| 1133 | return RTEMS_NO_MEMORY; /* ENOMEM */ |
---|
| 1134 | } |
---|
[44b06ca] | 1135 | |
---|
[226455f] | 1136 | can->txfifo = occan_fifo_create(DEFAULT_TX_FIFO_LEN); |
---|
| 1137 | if ( !can->txfifo ){ |
---|
| 1138 | occan_fifo_free(can->rxfifo); |
---|
| 1139 | can->rxfifo= NULL; |
---|
| 1140 | can->open = 0; |
---|
| 1141 | return RTEMS_NO_MEMORY; /* ENOMEM */ |
---|
| 1142 | } |
---|
[44b06ca] | 1143 | |
---|
[226455f] | 1144 | DBG("OCCAN: Opening %d success\n\r",minor); |
---|
| 1145 | |
---|
| 1146 | can->started = 0; |
---|
| 1147 | can->channel = 0; /* Default to first can link */ |
---|
| 1148 | can->txblk = 1; /* Default to Blocking mode */ |
---|
| 1149 | can->rxblk = 1; /* Default to Blocking mode */ |
---|
| 1150 | can->single_mode = 1; /* single mode acceptance filter */ |
---|
[44b06ca] | 1151 | |
---|
[226455f] | 1152 | /* reset stat counters */ |
---|
| 1153 | memset(&can->stats,0,sizeof(occan_stats)); |
---|
[44b06ca] | 1154 | |
---|
[226455f] | 1155 | /* HW must be in reset mode here (close and initializes resets core...) |
---|
| 1156 | * |
---|
| 1157 | * 1. set default modes/speeds |
---|
| 1158 | */ |
---|
| 1159 | pelican_open(can); |
---|
| 1160 | |
---|
| 1161 | return RTEMS_SUCCESSFUL; |
---|
| 1162 | } |
---|
| 1163 | |
---|
[3681925] | 1164 | static rtems_device_driver occan_close(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) |
---|
| 1165 | { |
---|
| 1166 | occan_priv *can; |
---|
| 1167 | struct drvmgr_dev *dev; |
---|
[44b06ca] | 1168 | |
---|
[226455f] | 1169 | DBG("OCCAN: Closing %d\n\r",minor); |
---|
[44b06ca] | 1170 | |
---|
[3681925] | 1171 | if ( drvmgr_get_dev(&occan_drv_info.general, minor, &dev) ) { |
---|
| 1172 | return RTEMS_INVALID_NAME; |
---|
| 1173 | } |
---|
| 1174 | can = (occan_priv *)dev->priv; |
---|
| 1175 | |
---|
[226455f] | 1176 | /* stop if running */ |
---|
| 1177 | if ( can->started ) |
---|
| 1178 | pelican_stop(can); |
---|
[44b06ca] | 1179 | |
---|
[226455f] | 1180 | /* Enter Reset Mode */ |
---|
[3681925] | 1181 | WRITE_REG(can, &can->regs->mode, PELICAN_MOD_RESET); |
---|
[44b06ca] | 1182 | |
---|
[226455f] | 1183 | /* free fifo memory */ |
---|
| 1184 | occan_fifo_free(can->rxfifo); |
---|
| 1185 | occan_fifo_free(can->txfifo); |
---|
[44b06ca] | 1186 | |
---|
[226455f] | 1187 | can->rxfifo = NULL; |
---|
| 1188 | can->txfifo = NULL; |
---|
[44b06ca] | 1189 | |
---|
[3681925] | 1190 | can->open = 0; |
---|
| 1191 | |
---|
[226455f] | 1192 | return RTEMS_SUCCESSFUL; |
---|
| 1193 | } |
---|
| 1194 | |
---|
[a8595605] | 1195 | static rtems_device_driver occan_read(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) |
---|
| 1196 | { |
---|
[3681925] | 1197 | occan_priv *can; |
---|
| 1198 | struct drvmgr_dev *dev; |
---|
[226455f] | 1199 | rtems_libio_rw_args_t *rw_args=(rtems_libio_rw_args_t *) arg; |
---|
| 1200 | CANMsg *dstmsg, *srcmsg; |
---|
[a8595605] | 1201 | SPIN_IRQFLAGS(oldLevel); |
---|
[226455f] | 1202 | int left; |
---|
[44b06ca] | 1203 | |
---|
[3681925] | 1204 | if ( drvmgr_get_dev(&occan_drv_info.general, minor, &dev) ) { |
---|
| 1205 | return RTEMS_INVALID_NAME; |
---|
| 1206 | } |
---|
| 1207 | can = (occan_priv *)dev->priv; |
---|
| 1208 | |
---|
[226455f] | 1209 | if ( !can->started ){ |
---|
| 1210 | DBG("OCCAN: cannot read from minor %d when not started\n\r",minor); |
---|
| 1211 | return RTEMS_RESOURCE_IN_USE; /* -EBUSY*/ |
---|
| 1212 | } |
---|
[44b06ca] | 1213 | |
---|
[226455f] | 1214 | /* does at least one message fit */ |
---|
| 1215 | left = rw_args->count; |
---|
| 1216 | if ( left < sizeof(CANMsg) ){ |
---|
| 1217 | DBG("OCCAN: minor %d length of buffer must be at least %d, our is %d\n\r",minor,sizeof(CANMsg),left); |
---|
| 1218 | return RTEMS_INVALID_NAME; /* -EINVAL */ |
---|
| 1219 | } |
---|
[44b06ca] | 1220 | |
---|
[226455f] | 1221 | /* get pointer to start where to put CAN messages */ |
---|
| 1222 | dstmsg = (CANMsg *)rw_args->buffer; |
---|
| 1223 | if ( !dstmsg ){ |
---|
| 1224 | DBG("OCCAN: minor %d read: input buffer is NULL\n\r",minor); |
---|
| 1225 | return RTEMS_INVALID_NAME; /* -EINVAL */ |
---|
[44b06ca] | 1226 | } |
---|
[226455f] | 1227 | |
---|
| 1228 | while (left >= sizeof(CANMsg) ){ |
---|
[44b06ca] | 1229 | |
---|
[226455f] | 1230 | /* turn off interrupts */ |
---|
[a8595605] | 1231 | SPIN_LOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1232 | |
---|
[226455f] | 1233 | /* A bus off interrupt may have occured after checking can->started */ |
---|
[2b985e79] | 1234 | if ( can->status & (OCCAN_STATUS_ERR_BUSOFF|OCCAN_STATUS_RESET) ){ |
---|
[a8595605] | 1235 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[226455f] | 1236 | DBG("OCCAN: read is cancelled due to a BUS OFF error\n\r"); |
---|
| 1237 | rw_args->bytes_moved = rw_args->count-left; |
---|
| 1238 | return RTEMS_IO_ERROR; /* EIO */ |
---|
| 1239 | } |
---|
[44b06ca] | 1240 | |
---|
[226455f] | 1241 | srcmsg = occan_fifo_claim_get(can->rxfifo); |
---|
| 1242 | if ( !srcmsg ){ |
---|
| 1243 | /* no more messages in reception fifo. |
---|
| 1244 | * Wait for incoming packets only if in |
---|
| 1245 | * blocking mode AND no messages been |
---|
| 1246 | * read before. |
---|
| 1247 | */ |
---|
| 1248 | if ( !can->rxblk || (left != rw_args->count) ){ |
---|
| 1249 | /* turn on interrupts again */ |
---|
[a8595605] | 1250 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[226455f] | 1251 | break; |
---|
| 1252 | } |
---|
[44b06ca] | 1253 | |
---|
[226455f] | 1254 | /* turn on interrupts again */ |
---|
[a8595605] | 1255 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1256 | |
---|
[226455f] | 1257 | DBG("OCCAN: Waiting for RX int\n\r"); |
---|
[44b06ca] | 1258 | |
---|
[3681925] | 1259 | /* wait for incoming messages */ |
---|
| 1260 | rtems_semaphore_obtain(can->rxsem, RTEMS_WAIT, |
---|
| 1261 | RTEMS_NO_TIMEOUT); |
---|
[44b06ca] | 1262 | |
---|
[226455f] | 1263 | /* did we get woken up by a BUS OFF error? */ |
---|
[2b985e79] | 1264 | if ( can->status & (OCCAN_STATUS_ERR_BUSOFF|OCCAN_STATUS_RESET) ){ |
---|
[226455f] | 1265 | DBG("OCCAN: Blocking read got woken up by BUS OFF error\n\r"); |
---|
| 1266 | /* At this point it should not matter how many messages we handled */ |
---|
[44b06ca] | 1267 | rw_args->bytes_moved = rw_args->count-left; |
---|
[226455f] | 1268 | return RTEMS_IO_ERROR; /* EIO */ |
---|
| 1269 | } |
---|
[44b06ca] | 1270 | |
---|
[226455f] | 1271 | /* no errors detected, it must be a message */ |
---|
| 1272 | continue; |
---|
| 1273 | } |
---|
[44b06ca] | 1274 | |
---|
[226455f] | 1275 | /* got message, copy it to userspace buffer */ |
---|
| 1276 | *dstmsg = *srcmsg; |
---|
[44b06ca] | 1277 | |
---|
[226455f] | 1278 | /* Return borrowed message, RX interrupt can use it again */ |
---|
| 1279 | occan_fifo_get(can->rxfifo); |
---|
[44b06ca] | 1280 | |
---|
[226455f] | 1281 | /* turn on interrupts again */ |
---|
[a8595605] | 1282 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1283 | |
---|
[226455f] | 1284 | /* increase pointers */ |
---|
| 1285 | left -= sizeof(CANMsg); |
---|
| 1286 | dstmsg++; |
---|
| 1287 | } |
---|
[44b06ca] | 1288 | |
---|
[226455f] | 1289 | /* save number of read bytes. */ |
---|
| 1290 | rw_args->bytes_moved = rw_args->count-left; |
---|
| 1291 | if ( rw_args->bytes_moved == 0 ){ |
---|
| 1292 | DBG("OCCAN: minor %d read would block, returning\n\r",minor); |
---|
| 1293 | return RTEMS_TIMEOUT; /* ETIMEDOUT should be EAGAIN/EWOULDBLOCK */ |
---|
| 1294 | } |
---|
| 1295 | return RTEMS_SUCCESSFUL; |
---|
| 1296 | } |
---|
| 1297 | |
---|
[a8595605] | 1298 | static rtems_device_driver occan_write(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) |
---|
| 1299 | { |
---|
[3681925] | 1300 | occan_priv *can; |
---|
| 1301 | struct drvmgr_dev *dev; |
---|
[226455f] | 1302 | rtems_libio_rw_args_t *rw_args=(rtems_libio_rw_args_t *) arg; |
---|
| 1303 | CANMsg *msg,*fifo_msg; |
---|
[a8595605] | 1304 | SPIN_IRQFLAGS(oldLevel); |
---|
[226455f] | 1305 | int left; |
---|
[44b06ca] | 1306 | |
---|
[226455f] | 1307 | DBG("OCCAN: Writing %d bytes from 0x%lx (%d)\n\r",rw_args->count,rw_args->buffer,sizeof(CANMsg)); |
---|
[44b06ca] | 1308 | |
---|
[3681925] | 1309 | if ( drvmgr_get_dev(&occan_drv_info.general, minor, &dev) ) { |
---|
| 1310 | return RTEMS_INVALID_NAME; |
---|
| 1311 | } |
---|
| 1312 | can = (occan_priv *)dev->priv; |
---|
| 1313 | |
---|
[226455f] | 1314 | if ( !can->started ) |
---|
| 1315 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
[44b06ca] | 1316 | |
---|
| 1317 | left = rw_args->count; |
---|
[226455f] | 1318 | if ( (left < sizeof(CANMsg)) || (!rw_args->buffer) ){ |
---|
| 1319 | return RTEMS_INVALID_NAME; /* EINVAL */ |
---|
| 1320 | } |
---|
[44b06ca] | 1321 | |
---|
[226455f] | 1322 | msg = (CANMsg *)rw_args->buffer; |
---|
[44b06ca] | 1323 | |
---|
[226455f] | 1324 | /* limit CAN message length to 8 */ |
---|
| 1325 | msg->len = (msg->len > 8) ? 8 : msg->len; |
---|
[44b06ca] | 1326 | |
---|
[226455f] | 1327 | #ifdef DEBUG_VERBOSE |
---|
| 1328 | pelican_regs_print(can->regs); |
---|
| 1329 | occan_stat_print(&can->stats); |
---|
| 1330 | #endif |
---|
| 1331 | |
---|
| 1332 | /* turn off interrupts */ |
---|
[a8595605] | 1333 | SPIN_LOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1334 | |
---|
[226455f] | 1335 | /* A bus off interrupt may have occured after checking can->started */ |
---|
[2b985e79] | 1336 | if ( can->status & (OCCAN_STATUS_ERR_BUSOFF|OCCAN_STATUS_RESET) ){ |
---|
[a8595605] | 1337 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[226455f] | 1338 | rw_args->bytes_moved = 0; |
---|
| 1339 | return RTEMS_IO_ERROR; /* EIO */ |
---|
| 1340 | } |
---|
| 1341 | |
---|
| 1342 | /* If no messages in software tx fifo, we will |
---|
| 1343 | * try to send first message by putting it directly |
---|
| 1344 | * into the HW TX fifo. |
---|
| 1345 | */ |
---|
| 1346 | if ( occan_fifo_empty(can->txfifo) ){ |
---|
| 1347 | /*pelican_regs_print(cans[minor+1].regs);*/ |
---|
| 1348 | if ( !pelican_send(can,msg) ) { |
---|
[44b06ca] | 1349 | /* First message put directly into HW TX fifo |
---|
[226455f] | 1350 | * This will turn TX interrupt on. |
---|
| 1351 | */ |
---|
| 1352 | left -= sizeof(CANMsg); |
---|
| 1353 | msg++; |
---|
[44b06ca] | 1354 | |
---|
[3681925] | 1355 | #ifdef OCCAN_TX_IRQ_FLAG_FIXUP |
---|
| 1356 | /* Mark that we have put at least one msg in TX FIFO */ |
---|
| 1357 | can->sending = 1; |
---|
| 1358 | #endif |
---|
| 1359 | |
---|
[226455f] | 1360 | /* bump stat counters */ |
---|
| 1361 | can->stats.tx_msgs++; |
---|
[44b06ca] | 1362 | |
---|
[226455f] | 1363 | DBG("OCCAN: Sending direct via HW\n\r"); |
---|
| 1364 | } |
---|
| 1365 | } |
---|
| 1366 | |
---|
| 1367 | /* Put messages into software fifo */ |
---|
| 1368 | while ( left >= sizeof(CANMsg) ){ |
---|
[44b06ca] | 1369 | |
---|
[226455f] | 1370 | /* limit CAN message length to 8 */ |
---|
| 1371 | msg->len = (msg->len > 8) ? 8 : msg->len; |
---|
[44b06ca] | 1372 | |
---|
[226455f] | 1373 | fifo_msg = occan_fifo_put_claim(can->txfifo,0); |
---|
| 1374 | if ( !fifo_msg ){ |
---|
[44b06ca] | 1375 | |
---|
[226455f] | 1376 | DBG("OCCAN: FIFO is full\n\r"); |
---|
| 1377 | /* Block only if no messages previously sent |
---|
| 1378 | * and no in blocking mode |
---|
| 1379 | */ |
---|
| 1380 | if ( !can->txblk || (left != rw_args->count) ) |
---|
| 1381 | break; |
---|
[44b06ca] | 1382 | |
---|
[226455f] | 1383 | /* turn on interupts again and wait |
---|
| 1384 | INT_ON |
---|
| 1385 | WAIT FOR FREE BUF; |
---|
| 1386 | INT_OFF; |
---|
| 1387 | CHECK_IF_FIFO_EMPTY ==> SEND DIRECT VIA HW; |
---|
| 1388 | */ |
---|
[a8595605] | 1389 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1390 | |
---|
[226455f] | 1391 | DBG("OCCAN: Waiting for tx int\n\r"); |
---|
[44b06ca] | 1392 | |
---|
[226455f] | 1393 | rtems_semaphore_obtain(can->txsem, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
---|
[44b06ca] | 1394 | |
---|
[226455f] | 1395 | /* did we get woken up by a BUS OFF error? */ |
---|
[2b985e79] | 1396 | if ( can->status & (OCCAN_STATUS_ERR_BUSOFF|OCCAN_STATUS_RESET) ){ |
---|
| 1397 | DBG("OCCAN: Blocking write got woken up by BUS OFF error or RESET event\n\r"); |
---|
[226455f] | 1398 | /* At this point it should not matter how many messages we handled */ |
---|
| 1399 | rw_args->bytes_moved = rw_args->count-left; |
---|
| 1400 | return RTEMS_IO_ERROR; /* EIO */ |
---|
| 1401 | } |
---|
[44b06ca] | 1402 | |
---|
[a8595605] | 1403 | SPIN_LOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1404 | |
---|
[226455f] | 1405 | if ( occan_fifo_empty(can->txfifo) ){ |
---|
| 1406 | if ( !pelican_send(can,msg) ) { |
---|
[44b06ca] | 1407 | /* First message put directly into HW TX fifo |
---|
[3681925] | 1408 | * This will turn TX interrupt on. |
---|
| 1409 | */ |
---|
[226455f] | 1410 | left -= sizeof(CANMsg); |
---|
| 1411 | msg++; |
---|
[44b06ca] | 1412 | |
---|
[3681925] | 1413 | #ifdef OCCAN_TX_IRQ_FLAG_FIXUP |
---|
| 1414 | /* Mark that we have put at least one msg in TX FIFO */ |
---|
| 1415 | can->sending = 1; |
---|
| 1416 | #endif |
---|
| 1417 | |
---|
[226455f] | 1418 | /* bump stat counters */ |
---|
| 1419 | can->stats.tx_msgs++; |
---|
[44b06ca] | 1420 | |
---|
[226455f] | 1421 | DBG("OCCAN: Sending direct2 via HW\n\r"); |
---|
| 1422 | } |
---|
| 1423 | } |
---|
| 1424 | continue; |
---|
| 1425 | } |
---|
[44b06ca] | 1426 | |
---|
[226455f] | 1427 | /* copy message into fifo area */ |
---|
| 1428 | *fifo_msg = *msg; |
---|
[44b06ca] | 1429 | |
---|
[226455f] | 1430 | /* tell interrupt handler about the message */ |
---|
| 1431 | occan_fifo_put(can->txfifo); |
---|
[44b06ca] | 1432 | |
---|
[226455f] | 1433 | DBG("OCCAN: Put info fifo SW\n\r"); |
---|
[44b06ca] | 1434 | |
---|
[226455f] | 1435 | /* Prepare insert of next message */ |
---|
| 1436 | msg++; |
---|
| 1437 | left-=sizeof(CANMsg); |
---|
| 1438 | } |
---|
[44b06ca] | 1439 | |
---|
[a8595605] | 1440 | SPIN_UNLOCK_IRQ(&can->devlock, oldLevel); |
---|
[44b06ca] | 1441 | |
---|
[226455f] | 1442 | rw_args->bytes_moved = rw_args->count-left; |
---|
| 1443 | DBG("OCCAN: Sent %d\n\r",rw_args->bytes_moved); |
---|
[44b06ca] | 1444 | |
---|
[226455f] | 1445 | if ( left == rw_args->count ) |
---|
| 1446 | return RTEMS_TIMEOUT; /* ETIMEDOUT should be EAGAIN/EWOULDBLOCK */ |
---|
| 1447 | return RTEMS_SUCCESSFUL; |
---|
| 1448 | } |
---|
| 1449 | |
---|
[a8595605] | 1450 | static rtems_device_driver occan_ioctl(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) |
---|
| 1451 | { |
---|
[226455f] | 1452 | int ret; |
---|
| 1453 | occan_speed_regs timing; |
---|
[3681925] | 1454 | occan_priv *can; |
---|
| 1455 | struct drvmgr_dev *dev; |
---|
[226455f] | 1456 | unsigned int speed; |
---|
[3681925] | 1457 | rtems_libio_ioctl_args_t *ioarg = (rtems_libio_ioctl_args_t *) arg; |
---|
[226455f] | 1458 | struct occan_afilter *afilter; |
---|
| 1459 | occan_stats *dststats; |
---|
| 1460 | unsigned int rxcnt,txcnt; |
---|
[44b06ca] | 1461 | |
---|
[226455f] | 1462 | DBG("OCCAN: IOCTL %d\n\r",ioarg->command); |
---|
[44b06ca] | 1463 | |
---|
[3681925] | 1464 | if ( drvmgr_get_dev(&occan_drv_info.general, minor, &dev) ) { |
---|
| 1465 | return RTEMS_INVALID_NAME; |
---|
| 1466 | } |
---|
| 1467 | can = (occan_priv *)dev->priv; |
---|
| 1468 | |
---|
[226455f] | 1469 | ioarg->ioctl_return = 0; |
---|
| 1470 | switch(ioarg->command){ |
---|
| 1471 | case OCCAN_IOC_SET_SPEED: |
---|
[44b06ca] | 1472 | |
---|
[226455f] | 1473 | /* cannot change speed during run mode */ |
---|
| 1474 | if ( can->started ) |
---|
| 1475 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
[44b06ca] | 1476 | |
---|
[226455f] | 1477 | /* get speed rate from argument */ |
---|
| 1478 | speed = (unsigned int)ioarg->buffer; |
---|
[3681925] | 1479 | ret = occan_calc_speedregs(can->sys_freq_hz,speed,&timing); |
---|
[226455f] | 1480 | if ( ret ) |
---|
| 1481 | return RTEMS_INVALID_NAME; /* EINVAL */ |
---|
[44b06ca] | 1482 | |
---|
[226455f] | 1483 | /* set the speed regs of the CAN core */ |
---|
| 1484 | /* occan_set_speedregs(can,timing); */ |
---|
[44b06ca] | 1485 | |
---|
[226455f] | 1486 | /* save timing/speed */ |
---|
| 1487 | can->speed = speed; |
---|
| 1488 | can->timing = timing; |
---|
| 1489 | break; |
---|
[44b06ca] | 1490 | |
---|
[226455f] | 1491 | case OCCAN_IOC_SET_BTRS: |
---|
[44b06ca] | 1492 | /* Set BTR registers manually |
---|
[226455f] | 1493 | * Read OCCAN Manual. |
---|
| 1494 | */ |
---|
| 1495 | if ( can->started ) |
---|
| 1496 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
[44b06ca] | 1497 | |
---|
[226455f] | 1498 | can->speed = 0; /* custom */ |
---|
| 1499 | can->timing.btr1 = (unsigned int)ioarg->buffer & 0xff; |
---|
| 1500 | can->timing.btr0 = ((unsigned int)ioarg->buffer>>8) & 0xff; |
---|
| 1501 | /* |
---|
| 1502 | can->timing.sjw = (btr0 >> OCCAN_BUSTIM_SJW_BIT) & 0x3; |
---|
| 1503 | can->timing.brp = btr0 & OCCAN_BUSTIM_BRP; |
---|
| 1504 | can->timing.tseg1 = btr1 & 0xf; |
---|
| 1505 | can->timing.tseg2 = (btr1 >> OCCAN_BUSTIM_TSEG2_BIT) & 0x7; |
---|
| 1506 | can->timing.sam = (btr1 >> 7) & 0x1; |
---|
| 1507 | */ |
---|
| 1508 | break; |
---|
[44b06ca] | 1509 | |
---|
[226455f] | 1510 | case OCCAN_IOC_SPEED_AUTO: |
---|
| 1511 | return RTEMS_NOT_IMPLEMENTED; |
---|
[44b06ca] | 1512 | |
---|
[226455f] | 1513 | case OCCAN_IOC_SET_BUFLEN: |
---|
| 1514 | /* set rx & tx fifo buffer length */ |
---|
| 1515 | if ( can->started ) |
---|
| 1516 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
[44b06ca] | 1517 | |
---|
[226455f] | 1518 | rxcnt = (unsigned int)ioarg->buffer & 0x0000ffff; |
---|
| 1519 | txcnt = (unsigned int)ioarg->buffer >> 16; |
---|
[44b06ca] | 1520 | |
---|
[226455f] | 1521 | occan_fifo_free(can->rxfifo); |
---|
| 1522 | occan_fifo_free(can->txfifo); |
---|
[44b06ca] | 1523 | |
---|
[226455f] | 1524 | /* allocate new buffers */ |
---|
| 1525 | can->rxfifo = occan_fifo_create(rxcnt); |
---|
| 1526 | can->txfifo = occan_fifo_create(txcnt); |
---|
[44b06ca] | 1527 | |
---|
[226455f] | 1528 | if ( !can->rxfifo || !can->txfifo ) |
---|
| 1529 | return RTEMS_NO_MEMORY; /* ENOMEM */ |
---|
| 1530 | break; |
---|
[44b06ca] | 1531 | |
---|
[226455f] | 1532 | case OCCAN_IOC_GET_CONF: |
---|
| 1533 | return RTEMS_NOT_IMPLEMENTED; |
---|
| 1534 | break; |
---|
[44b06ca] | 1535 | |
---|
[226455f] | 1536 | case OCCAN_IOC_GET_STATS: |
---|
| 1537 | dststats = (occan_stats *)ioarg->buffer; |
---|
| 1538 | if ( !dststats ) |
---|
| 1539 | return RTEMS_INVALID_NAME; /* EINVAL */ |
---|
[44b06ca] | 1540 | |
---|
[226455f] | 1541 | /* copy data stats into userspace buffer */ |
---|
[3681925] | 1542 | if ( can->rxfifo ) |
---|
| 1543 | can->stats.rx_sw_dovr = can->rxfifo->ovcnt; |
---|
[226455f] | 1544 | *dststats = can->stats; |
---|
| 1545 | break; |
---|
[44b06ca] | 1546 | |
---|
[226455f] | 1547 | case OCCAN_IOC_GET_STATUS: |
---|
| 1548 | /* return the status of the */ |
---|
| 1549 | if ( !ioarg->buffer ) |
---|
| 1550 | return RTEMS_INVALID_NAME; |
---|
[44b06ca] | 1551 | |
---|
[226455f] | 1552 | *(unsigned int *)ioarg->buffer = can->status; |
---|
| 1553 | break; |
---|
[44b06ca] | 1554 | |
---|
[226455f] | 1555 | /* Set physical link */ |
---|
| 1556 | case OCCAN_IOC_SET_LINK: |
---|
| 1557 | #ifdef REDUNDANT_CHANNELS |
---|
| 1558 | if ( can->started ) |
---|
| 1559 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
[44b06ca] | 1560 | |
---|
[226455f] | 1561 | /* switch HW channel */ |
---|
| 1562 | can->channel = (unsigned int)ioargs->buffer; |
---|
| 1563 | #else |
---|
| 1564 | return RTEMS_NOT_IMPLEMENTED; |
---|
| 1565 | #endif |
---|
| 1566 | break; |
---|
[44b06ca] | 1567 | |
---|
[226455f] | 1568 | case OCCAN_IOC_SET_FILTER: |
---|
| 1569 | if ( can->started ) |
---|
| 1570 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
[44b06ca] | 1571 | |
---|
[226455f] | 1572 | afilter = (struct occan_afilter *)ioarg->buffer; |
---|
[44b06ca] | 1573 | |
---|
[226455f] | 1574 | if ( !afilter ) |
---|
| 1575 | return RTEMS_INVALID_NAME; /* EINVAL */ |
---|
[44b06ca] | 1576 | |
---|
[226455f] | 1577 | /* copy acceptance filter */ |
---|
| 1578 | can->acode[0] = afilter->code[0]; |
---|
| 1579 | can->acode[1] = afilter->code[1]; |
---|
| 1580 | can->acode[2] = afilter->code[2]; |
---|
| 1581 | can->acode[3] = afilter->code[3]; |
---|
[44b06ca] | 1582 | |
---|
[226455f] | 1583 | can->amask[0] = afilter->mask[0]; |
---|
| 1584 | can->amask[1] = afilter->mask[1]; |
---|
| 1585 | can->amask[2] = afilter->mask[2]; |
---|
[44b06ca] | 1586 | can->amask[3] = afilter->mask[3]; |
---|
| 1587 | |
---|
[226455f] | 1588 | can->single_mode = ( afilter->single_mode ) ? 1 : 0; |
---|
[44b06ca] | 1589 | |
---|
| 1590 | /* Acceptance filter is written to hardware |
---|
[226455f] | 1591 | * when starting. |
---|
| 1592 | */ |
---|
| 1593 | /* pelican_set_accept(can,can->acode,can->amask);*/ |
---|
| 1594 | break; |
---|
[44b06ca] | 1595 | |
---|
[226455f] | 1596 | case OCCAN_IOC_SET_BLK_MODE: |
---|
| 1597 | can->rxblk = (unsigned int)ioarg->buffer & OCCAN_BLK_MODE_RX; |
---|
| 1598 | can->txblk = ((unsigned int)ioarg->buffer & OCCAN_BLK_MODE_TX) >> 1; |
---|
| 1599 | break; |
---|
[44b06ca] | 1600 | |
---|
[226455f] | 1601 | case OCCAN_IOC_START: |
---|
| 1602 | if ( can->started ) |
---|
| 1603 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
| 1604 | if ( pelican_start(can) ) |
---|
| 1605 | return RTEMS_NO_MEMORY; /* failed because of no memory, can happen if SET_BUFLEN failed */ |
---|
[3681925] | 1606 | /* can->started = 1; -- Is set in pelican_start due to interrupt may occur before we |
---|
| 1607 | * get here. |
---|
| 1608 | */ |
---|
[226455f] | 1609 | break; |
---|
[44b06ca] | 1610 | |
---|
[226455f] | 1611 | case OCCAN_IOC_STOP: |
---|
| 1612 | if ( !can->started ) |
---|
| 1613 | return RTEMS_RESOURCE_IN_USE; /* EBUSY */ |
---|
| 1614 | pelican_stop(can); |
---|
| 1615 | can->started = 0; |
---|
| 1616 | break; |
---|
| 1617 | |
---|
| 1618 | default: |
---|
| 1619 | return RTEMS_NOT_DEFINED; |
---|
| 1620 | } |
---|
| 1621 | return RTEMS_SUCCESSFUL; |
---|
| 1622 | } |
---|
| 1623 | |
---|
[3681925] | 1624 | void occan_interrupt(void *arg) |
---|
| 1625 | { |
---|
| 1626 | occan_priv *can = arg; |
---|
[226455f] | 1627 | unsigned char iflags; |
---|
| 1628 | pelican_regs *regs = can->regs; |
---|
| 1629 | CANMsg *msg; |
---|
| 1630 | int signal_rx=0, signal_tx=0; |
---|
| 1631 | unsigned char tmp, errcode, arbcode; |
---|
| 1632 | int tx_error_cnt,rx_error_cnt; |
---|
[a8595605] | 1633 | SPIN_ISR_IRQFLAGS(irqflags); |
---|
[44b06ca] | 1634 | |
---|
[3681925] | 1635 | if ( !can->started ) |
---|
| 1636 | return; /* Spurious Interrupt, do nothing */ |
---|
| 1637 | |
---|
[a8595605] | 1638 | SPIN_LOCK(&can->devlock, irqflags); |
---|
[3681925] | 1639 | while (1) { |
---|
| 1640 | |
---|
| 1641 | iflags = READ_REG(can, &can->regs->intflags); |
---|
| 1642 | |
---|
| 1643 | #ifdef OCCAN_TX_IRQ_FLAG_FIXUP |
---|
| 1644 | /* TX IRQ may be cleared when reading regs->intflags due |
---|
| 1645 | * to a bug in some chips. Instead of looking at the TX_IRQ_FLAG |
---|
| 1646 | * the TX-fifo emoty register is looked at when something has |
---|
| 1647 | * been scheduled for transmission. |
---|
| 1648 | */ |
---|
| 1649 | if ((iflags & PELICAN_IF_TX) == 0) { |
---|
| 1650 | if (can->sending && pelican_tx_ready(can)) { |
---|
| 1651 | can->sending = 0; |
---|
| 1652 | iflags |= PELICAN_IF_TX; |
---|
| 1653 | } |
---|
| 1654 | } |
---|
| 1655 | #endif |
---|
[44b06ca] | 1656 | |
---|
[3681925] | 1657 | if (iflags == 0) |
---|
| 1658 | break; |
---|
[226455f] | 1659 | /* still interrupts to handle */ |
---|
[44b06ca] | 1660 | |
---|
[3681925] | 1661 | can->stats.ints++; |
---|
| 1662 | |
---|
[226455f] | 1663 | if ( iflags & PELICAN_IF_RX ){ |
---|
| 1664 | /* the rx fifo is not empty |
---|
[44b06ca] | 1665 | * put 1 message into rxfifo for later use |
---|
[226455f] | 1666 | */ |
---|
[44b06ca] | 1667 | |
---|
[226455f] | 1668 | /* get empty (or make room) message */ |
---|
| 1669 | msg = occan_fifo_put_claim(can->rxfifo,1); |
---|
[3681925] | 1670 | tmp = READ_REG(can, ®s->rx_fi_xff); |
---|
[226455f] | 1671 | msg->extended = tmp >> 7; |
---|
| 1672 | msg->rtr = (tmp >> 6) & 1; |
---|
| 1673 | msg->len = tmp = tmp & 0x0f; |
---|
[44b06ca] | 1674 | |
---|
[226455f] | 1675 | if ( msg->extended ){ |
---|
| 1676 | /* extended message */ |
---|
[3681925] | 1677 | msg->id = READ_REG(can, ®s->msg.rx_eff.id[0])<<(5+8+8) | |
---|
| 1678 | READ_REG(can, ®s->msg.rx_eff.id[1])<<(5+8) | |
---|
| 1679 | READ_REG(can, ®s->msg.rx_eff.id[2])<<5 | |
---|
| 1680 | READ_REG(can, ®s->msg.rx_eff.id[3])>>3; |
---|
| 1681 | |
---|
[226455f] | 1682 | while(tmp--){ |
---|
[3681925] | 1683 | msg->data[tmp] = READ_REG(can, ®s->msg.rx_eff.data[tmp]); |
---|
[226455f] | 1684 | } |
---|
| 1685 | /* |
---|
[3681925] | 1686 | msg->data[0] = READ_REG(can, ®s->msg.rx_eff.data[0]); |
---|
| 1687 | msg->data[1] = READ_REG(can, ®s->msg.rx_eff.data[1]); |
---|
| 1688 | msg->data[2] = READ_REG(can, ®s->msg.rx_eff.data[2]); |
---|
| 1689 | msg->data[3] = READ_REG(can, ®s->msg.rx_eff.data[3]); |
---|
| 1690 | msg->data[4] = READ_REG(can, ®s->msg.rx_eff.data[4]); |
---|
| 1691 | msg->data[5] = READ_REG(can, ®s->msg.rx_eff.data[5]); |
---|
| 1692 | msg->data[6] = READ_REG(can, ®s->msg.rx_eff.data[6]); |
---|
| 1693 | msg->data[7] = READ_REG(can, ®s->msg.rx_eff.data[7]); |
---|
[226455f] | 1694 | */ |
---|
| 1695 | }else{ |
---|
| 1696 | /* standard message */ |
---|
[3681925] | 1697 | msg->id = READ_REG(can, ®s->msg.rx_sff.id[0])<<3 | |
---|
| 1698 | READ_REG(can, ®s->msg.rx_sff.id[1])>>5; |
---|
[44b06ca] | 1699 | |
---|
[226455f] | 1700 | while(tmp--){ |
---|
[3681925] | 1701 | msg->data[tmp] = READ_REG(can, ®s->msg.rx_sff.data[tmp]); |
---|
[226455f] | 1702 | } |
---|
| 1703 | /* |
---|
[3681925] | 1704 | msg->data[0] = READ_REG(can, ®s->msg.rx_sff.data[0]); |
---|
| 1705 | msg->data[1] = READ_REG(can, ®s->msg.rx_sff.data[1]); |
---|
| 1706 | msg->data[2] = READ_REG(can, ®s->msg.rx_sff.data[2]); |
---|
| 1707 | msg->data[3] = READ_REG(can, ®s->msg.rx_sff.data[3]); |
---|
| 1708 | msg->data[4] = READ_REG(can, ®s->msg.rx_sff.data[4]); |
---|
| 1709 | msg->data[5] = READ_REG(can, ®s->msg.rx_sff.data[5]); |
---|
| 1710 | msg->data[6] = READ_REG(can, ®s->msg.rx_sff.data[6]); |
---|
| 1711 | msg->data[7] = READ_REG(can, ®s->msg.rx_sff.data[7]); |
---|
[226455f] | 1712 | */ |
---|
| 1713 | } |
---|
[44b06ca] | 1714 | |
---|
[226455f] | 1715 | /* Re-Enable RX buffer for a new message */ |
---|
[3681925] | 1716 | WRITE_REG(can, ®s->cmd, PELICAN_CMD_RELRXBUF); |
---|
[44b06ca] | 1717 | |
---|
[226455f] | 1718 | /* make message available to the user */ |
---|
| 1719 | occan_fifo_put(can->rxfifo); |
---|
[44b06ca] | 1720 | |
---|
[226455f] | 1721 | /* bump stat counters */ |
---|
| 1722 | can->stats.rx_msgs++; |
---|
[44b06ca] | 1723 | |
---|
[226455f] | 1724 | /* signal the semaphore only once */ |
---|
| 1725 | signal_rx = 1; |
---|
| 1726 | } |
---|
[44b06ca] | 1727 | |
---|
[3681925] | 1728 | if ( iflags & PELICAN_IF_TX ) { |
---|
| 1729 | |
---|
[226455f] | 1730 | /* there is room in tx fifo of HW */ |
---|
[44b06ca] | 1731 | |
---|
[226455f] | 1732 | if ( !occan_fifo_empty(can->txfifo) ){ |
---|
| 1733 | /* send 1 more messages */ |
---|
| 1734 | msg = occan_fifo_claim_get(can->txfifo); |
---|
[44b06ca] | 1735 | |
---|
[226455f] | 1736 | if ( pelican_send(can,msg) ){ |
---|
[44b06ca] | 1737 | /* ERROR! We got an TX interrupt telling us |
---|
[226455f] | 1738 | * tx fifo is empty, yet it is not. |
---|
| 1739 | * |
---|
| 1740 | * Complain about this max 10 times |
---|
| 1741 | */ |
---|
| 1742 | if ( can->stats.tx_buf_error < 10 ){ |
---|
| 1743 | printk("OCCAN: got TX interrupt but TX fifo in not empty (%d)\n\r",can->stats.tx_buf_error); |
---|
| 1744 | } |
---|
| 1745 | can->status |= OCCAN_STATUS_QUEUE_ERROR; |
---|
| 1746 | can->stats.tx_buf_error++; |
---|
| 1747 | } |
---|
[3681925] | 1748 | #ifdef OCCAN_TX_IRQ_FLAG_FIXUP |
---|
| 1749 | can->sending = 1; |
---|
| 1750 | #endif |
---|
[44b06ca] | 1751 | |
---|
[226455f] | 1752 | /* free software-fifo space taken by sent message */ |
---|
| 1753 | occan_fifo_get(can->txfifo); |
---|
[44b06ca] | 1754 | |
---|
[226455f] | 1755 | /* bump stat counters */ |
---|
| 1756 | can->stats.tx_msgs++; |
---|
[44b06ca] | 1757 | |
---|
[226455f] | 1758 | /* wake any sleeping thread waiting for "fifo not full" */ |
---|
| 1759 | signal_tx = 1; |
---|
| 1760 | } |
---|
| 1761 | } |
---|
[44b06ca] | 1762 | |
---|
[226455f] | 1763 | if ( iflags & PELICAN_IF_ERRW ){ |
---|
[3681925] | 1764 | tx_error_cnt = READ_REG(can, ®s->tx_err_cnt); |
---|
| 1765 | rx_error_cnt = READ_REG(can, ®s->rx_err_cnt); |
---|
[44b06ca] | 1766 | |
---|
[226455f] | 1767 | /* 1. if bus off tx error counter = 127 */ |
---|
| 1768 | if ( (tx_error_cnt > 96) || (rx_error_cnt > 96) ){ |
---|
| 1769 | /* in Error Active Warning area or BUS OFF */ |
---|
| 1770 | can->status |= OCCAN_STATUS_WARN; |
---|
[44b06ca] | 1771 | |
---|
[226455f] | 1772 | /* check reset bit for reset mode */ |
---|
[3681925] | 1773 | if ( READ_REG(can, ®s->mode) & PELICAN_MOD_RESET ){ |
---|
[226455f] | 1774 | /* in reset mode ==> bus off */ |
---|
| 1775 | can->status |= OCCAN_STATUS_ERR_BUSOFF | OCCAN_STATUS_RESET; |
---|
[44b06ca] | 1776 | |
---|
[226455f] | 1777 | /***** pelican_stop(can) ****** |
---|
| 1778 | * turn off interrupts |
---|
| 1779 | * enter reset mode (HW already done that for us) |
---|
| 1780 | */ |
---|
[3681925] | 1781 | WRITE_REG(can, ®s->inten,0); |
---|
[44b06ca] | 1782 | |
---|
[226455f] | 1783 | /* Indicate that we are not started any more. |
---|
[44b06ca] | 1784 | * This will make write/read return with EBUSY |
---|
[226455f] | 1785 | * on read/write attempts. |
---|
| 1786 | * |
---|
| 1787 | * User must issue a ioctl(START) to get going again. |
---|
| 1788 | */ |
---|
| 1789 | can->started = 0; |
---|
[44b06ca] | 1790 | |
---|
| 1791 | /* signal any waiting read/write threads, so that they |
---|
[226455f] | 1792 | * can handle the bus error. |
---|
| 1793 | */ |
---|
| 1794 | signal_rx = 1; |
---|
| 1795 | signal_tx = 1; |
---|
[44b06ca] | 1796 | |
---|
[226455f] | 1797 | /* ingnore any old pending interrupt */ |
---|
| 1798 | break; |
---|
| 1799 | } |
---|
[44b06ca] | 1800 | |
---|
[226455f] | 1801 | }else{ |
---|
| 1802 | /* not in Upper Error Active area any more */ |
---|
| 1803 | can->status &= ~(OCCAN_STATUS_WARN); |
---|
| 1804 | } |
---|
| 1805 | can->stats.err_warn++; |
---|
| 1806 | } |
---|
[44b06ca] | 1807 | |
---|
[226455f] | 1808 | if ( iflags & PELICAN_IF_DOVR){ |
---|
| 1809 | can->status |= OCCAN_STATUS_OVERRUN; |
---|
| 1810 | can->stats.err_dovr++; |
---|
| 1811 | DBG("OCCAN_INT: DOVR\n\r"); |
---|
| 1812 | } |
---|
[44b06ca] | 1813 | |
---|
[226455f] | 1814 | if ( iflags & PELICAN_IF_ERRP){ |
---|
[44b06ca] | 1815 | /* Let the error counters decide what kind of |
---|
[226455f] | 1816 | * interrupt it was. In/Out of EPassive area. |
---|
| 1817 | */ |
---|
[3681925] | 1818 | tx_error_cnt = READ_REG(can, ®s->tx_err_cnt); |
---|
| 1819 | rx_error_cnt = READ_REG(can, ®s->rx_err_cnt); |
---|
[44b06ca] | 1820 | |
---|
[b151f5b] | 1821 | if ( (tx_error_cnt > 127) || (rx_error_cnt > 127) ){ |
---|
[226455f] | 1822 | can->status |= OCCAN_STATUS_ERR_PASSIVE; |
---|
| 1823 | }else{ |
---|
| 1824 | can->status &= ~(OCCAN_STATUS_ERR_PASSIVE); |
---|
| 1825 | } |
---|
[44b06ca] | 1826 | |
---|
[226455f] | 1827 | /* increase Error Passive In/out interrupt counter */ |
---|
| 1828 | can->stats.err_errp++; |
---|
| 1829 | } |
---|
[44b06ca] | 1830 | |
---|
[226455f] | 1831 | if ( iflags & PELICAN_IF_ARB){ |
---|
[3681925] | 1832 | arbcode = READ_REG(can, ®s->arbcode); |
---|
[226455f] | 1833 | can->stats.err_arb_bitnum[arbcode & PELICAN_ARB_BITS]++; |
---|
| 1834 | can->stats.err_arb++; |
---|
| 1835 | DBG("OCCAN_INT: ARB (0x%x)\n\r",arbcode & PELICAN_ARB_BITS); |
---|
| 1836 | } |
---|
| 1837 | |
---|
| 1838 | if ( iflags & PELICAN_IF_BUS){ |
---|
[44b06ca] | 1839 | /* Some kind of BUS error, only used for |
---|
[226455f] | 1840 | * statistics. Error Register is decoded |
---|
| 1841 | * and put into can->stats. |
---|
| 1842 | */ |
---|
[3681925] | 1843 | errcode = READ_REG(can, ®s->errcode); |
---|
[226455f] | 1844 | switch( errcode & PELICAN_ECC_CODE ){ |
---|
| 1845 | case PELICAN_ECC_CODE_BIT: |
---|
| 1846 | can->stats.err_bus_bit++; |
---|
| 1847 | break; |
---|
| 1848 | case PELICAN_ECC_CODE_FORM: |
---|
| 1849 | can->stats.err_bus_form++; |
---|
| 1850 | break; |
---|
| 1851 | case PELICAN_ECC_CODE_STUFF: |
---|
| 1852 | can->stats.err_bus_stuff++; |
---|
| 1853 | break; |
---|
| 1854 | case PELICAN_ECC_CODE_OTHER: |
---|
| 1855 | can->stats.err_bus_other++; |
---|
| 1856 | break; |
---|
| 1857 | } |
---|
[44b06ca] | 1858 | |
---|
[226455f] | 1859 | /* Get Direction (TX/RX) */ |
---|
| 1860 | if ( errcode & PELICAN_ECC_DIR ){ |
---|
| 1861 | can->stats.err_bus_rx++; |
---|
| 1862 | }else{ |
---|
| 1863 | can->stats.err_bus_tx++; |
---|
| 1864 | } |
---|
[44b06ca] | 1865 | |
---|
[226455f] | 1866 | /* Get Segment in frame that went wrong */ |
---|
| 1867 | can->stats.err_bus_segs[errcode & PELICAN_ECC_SEG]++; |
---|
[44b06ca] | 1868 | |
---|
[226455f] | 1869 | /* total number of bus errors */ |
---|
| 1870 | can->stats.err_bus++; |
---|
| 1871 | } |
---|
| 1872 | } |
---|
[a8595605] | 1873 | SPIN_UNLOCK(&can->devlock, irqflags); |
---|
[44b06ca] | 1874 | |
---|
[226455f] | 1875 | /* signal Binary semaphore, messages available! */ |
---|
| 1876 | if ( signal_rx ){ |
---|
| 1877 | rtems_semaphore_release(can->rxsem); |
---|
| 1878 | } |
---|
[44b06ca] | 1879 | |
---|
[226455f] | 1880 | if ( signal_tx ){ |
---|
| 1881 | rtems_semaphore_release(can->txsem); |
---|
| 1882 | } |
---|
| 1883 | } |
---|
| 1884 | |
---|
| 1885 | /******************************************************************************* |
---|
[44b06ca] | 1886 | * FIFO IMPLEMENTATION |
---|
[226455f] | 1887 | */ |
---|
| 1888 | |
---|
[3681925] | 1889 | static occan_fifo *occan_fifo_create(int cnt) |
---|
| 1890 | { |
---|
[226455f] | 1891 | occan_fifo *fifo; |
---|
| 1892 | fifo = malloc(sizeof(occan_fifo)+cnt*sizeof(CANMsg)); |
---|
| 1893 | if ( fifo ){ |
---|
| 1894 | fifo->cnt = cnt; |
---|
| 1895 | fifo->full = 0; |
---|
| 1896 | fifo->ovcnt = 0; |
---|
| 1897 | fifo->base = (CANMsg *)&fifo->fifoarea[0]; |
---|
| 1898 | fifo->tail = fifo->head = fifo->base; |
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| 1899 | /* clear CAN Messages */ |
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| 1900 | memset(fifo->base,0,cnt * sizeof(CANMsg)); |
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| 1901 | } |
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| 1902 | return fifo; |
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| 1903 | } |
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| 1904 | |
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[3681925] | 1905 | static void occan_fifo_free(occan_fifo *fifo) |
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| 1906 | { |
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[226455f] | 1907 | if ( fifo ) |
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| 1908 | free(fifo); |
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| 1909 | } |
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| 1910 | |
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[3681925] | 1911 | static int occan_fifo_full(occan_fifo *fifo) |
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| 1912 | { |
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[226455f] | 1913 | return fifo->full; |
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| 1914 | } |
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| 1915 | |
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[3681925] | 1916 | static int occan_fifo_empty(occan_fifo *fifo) |
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| 1917 | { |
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[226455f] | 1918 | return (!fifo->full) && (fifo->head == fifo->tail); |
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| 1919 | } |
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| 1920 | |
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| 1921 | /* Stage 1 - get buffer to fill (never fails if force!=0) */ |
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[3681925] | 1922 | static CANMsg *occan_fifo_put_claim(occan_fifo *fifo, int force) |
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| 1923 | { |
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[226455f] | 1924 | if ( !fifo ) |
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| 1925 | return NULL; |
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[44b06ca] | 1926 | |
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[226455f] | 1927 | if ( occan_fifo_full(fifo) ){ |
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[44b06ca] | 1928 | |
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[226455f] | 1929 | if ( !force ) |
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| 1930 | return NULL; |
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[44b06ca] | 1931 | |
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[226455f] | 1932 | /* all buffers already used ==> overwrite the oldest */ |
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| 1933 | fifo->ovcnt++; |
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| 1934 | occan_fifo_get(fifo); |
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| 1935 | } |
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[44b06ca] | 1936 | |
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[226455f] | 1937 | return fifo->head; |
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| 1938 | } |
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| 1939 | |
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| 1940 | /* Stage 2 - increment indexes */ |
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[3681925] | 1941 | static void occan_fifo_put(occan_fifo *fifo) |
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| 1942 | { |
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[226455f] | 1943 | if ( occan_fifo_full(fifo) ) |
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| 1944 | return; |
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[44b06ca] | 1945 | |
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[226455f] | 1946 | /* wrap around */ |
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| 1947 | fifo->head = (fifo->head >= &fifo->base[fifo->cnt-1])? fifo->base : fifo->head+1; |
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[44b06ca] | 1948 | |
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[226455f] | 1949 | if ( fifo->head == fifo->tail ) |
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| 1950 | fifo->full = 1; |
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| 1951 | } |
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| 1952 | |
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[3681925] | 1953 | static CANMsg *occan_fifo_claim_get(occan_fifo *fifo) |
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| 1954 | { |
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[226455f] | 1955 | if ( occan_fifo_empty(fifo) ) |
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| 1956 | return NULL; |
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[44b06ca] | 1957 | |
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[226455f] | 1958 | /* return oldest message */ |
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| 1959 | return fifo->tail; |
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| 1960 | } |
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| 1961 | |
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| 1962 | |
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[3681925] | 1963 | static void occan_fifo_get(occan_fifo *fifo) |
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| 1964 | { |
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[226455f] | 1965 | if ( !fifo ) |
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| 1966 | return; |
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| 1967 | |
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| 1968 | if ( occan_fifo_empty(fifo) ) |
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| 1969 | return; |
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[44b06ca] | 1970 | |
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[226455f] | 1971 | /* increment indexes */ |
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[3681925] | 1972 | fifo->tail = (fifo->tail >= &fifo->base[fifo->cnt-1]) ? |
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| 1973 | fifo->base : fifo->tail+1; |
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[226455f] | 1974 | fifo->full = 0; |
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| 1975 | } |
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[5b42368a] | 1976 | |
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[3681925] | 1977 | static void occan_fifo_clr(occan_fifo *fifo) |
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| 1978 | { |
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| 1979 | fifo->full = 0; |
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| 1980 | fifo->ovcnt = 0; |
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| 1981 | fifo->head = fifo->tail = fifo->base; |
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[5b42368a] | 1982 | } |
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| 1983 | |
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[3681925] | 1984 | /******************************************************************************/ |
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