1 | |
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2 | #include <rasta.h> |
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3 | |
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4 | /* PCI frequency */ |
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5 | #define SYS_FREQ_HZ 30000000 |
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6 | |
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7 | /*#define USE_AT697_RAM 1 */ |
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8 | |
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9 | /* memarea_to_hw(x) |
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10 | * |
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11 | * x: address in AT697 address space |
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12 | * |
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13 | * returns the address in the RASTA address space that can be used to access x with dma. |
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14 | * |
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15 | */ |
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16 | #ifdef USE_AT697_RAM |
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17 | static inline unsigned int memarea_to_hw(unsigned int addr) { |
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18 | return ((addr & 0x0fffffff) | RASTA_PCI_BASE); |
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19 | } |
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20 | #else |
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21 | static inline unsigned int memarea_to_hw(unsigned int addr) { |
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22 | return ((addr & 0x0fffffff) | RASTA_LOCAL_SRAM); |
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23 | } |
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24 | #endif |
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25 | |
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26 | #define MEMAREA_TO_HW(x) memarea_to_hw(x) |
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27 | |
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28 | #define IRQ_CLEAR_PENDING(irqno) |
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29 | #define IRQ_UNMASK(irqno) |
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30 | #define IRQ_MASK(irqno) |
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31 | |
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32 | #define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level |
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33 | #define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level) |
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34 | #define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level) |
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35 | |
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36 | #define GRCAN_REG_INT(handler,irqno,arg) \ |
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37 | if ( grcan_rasta_int_reg ) \ |
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38 | grcan_rasta_int_reg(handler,irqno,arg); |
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39 | |
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40 | void (*grcan_rasta_int_reg)(void *handler, int irq, void *arg) = 0; |
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41 | |
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42 | #define GRCAN_PREFIX(name) grcan_rasta##name |
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43 | |
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44 | /* We provide our own handler */ |
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45 | #define GRCAN_DONT_DECLARE_IRQ_HANDLER |
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46 | |
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47 | #define GRCAN_REG_BYPASS_CACHE |
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48 | #define GRCAN_DMA_BYPASS_CACHE |
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49 | |
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50 | #define GRCAN_MAX_CORES 1 |
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51 | |
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52 | /* Custom Statically allocated memory */ |
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53 | #undef STATICALLY_ALLOCATED_TX_BUFFER |
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54 | #undef STATICALLY_ALLOCATED_RX_BUFFER |
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55 | |
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56 | #define STATIC_TX_BUF_SIZE 4096 |
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57 | #define STATIC_RX_BUF_SIZE 4096 |
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58 | #define TX_BUF_SIZE 4096 |
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59 | #define RX_BUF_SIZE 4096 |
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60 | |
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61 | #define STATIC_TX_BUF_ADDR(core) \ |
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62 | ((unsigned int *)\ |
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63 | (grcan_rasta_rambase+(core)*(STATIC_TX_BUF_SIZE+STATIC_RX_BUF_SIZE))) |
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64 | |
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65 | #define STATIC_RX_BUF_ADDR(core) \ |
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66 | ((unsigned int *) \ |
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67 | (grcan_rasta_rambase+(core)*(STATIC_TX_BUF_SIZE+STATIC_RX_BUF_SIZE)+STATIC_RX_BUF_SIZE)) |
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68 | |
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69 | |
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70 | #define GRCAN_DEVNAME "/dev/grcan0" |
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71 | #define GRCAN_DEVNAME_NO(devstr,no) ((devstr)[10]='0'+(no)) |
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72 | |
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73 | void grcan_rasta_interrupt_handler(int irq, void *pDev); |
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74 | |
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75 | unsigned int grcan_rasta_rambase; |
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76 | |
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77 | #include "grcan.c" |
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78 | |
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79 | |
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80 | int grcan_rasta_ram_register(amba_confarea_type *abus, int rambase) |
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81 | { |
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82 | grcan_rasta_rambase = rambase; |
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83 | |
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84 | return GRCAN_PREFIX(_register)(abus); |
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85 | } |
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86 | #if 0 |
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87 | static void grcan_rasta_interrupt_handler(int v) |
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88 | { |
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89 | /* We know there is always only one GRCAN core in a RASTA chip... */ |
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90 | grcan_interrupt(&grcans[0]); |
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91 | /* |
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92 | struct grcan_priv *pDev = arg; |
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93 | grcan_interrupt(pDev); |
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94 | */ |
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95 | } |
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96 | #endif |
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97 | void GRCAN_PREFIX(_interrupt_handler)(int irq, void *pDev) |
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98 | { |
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99 | grcan_interrupt(pDev); |
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100 | } |
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