source: rtems/c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c @ aacb7e6

4.115
Last change on this file since aacb7e6 was 54f3476e, checked in by Daniel Cederman <cederman@…>, on 07/03/14 at 09:18:55

bsp/sparc: Flush icache before first time enabling interrupts

A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/**
2 * @file
3 * @ingroup sparc_leon3
4 * @brief LEON3 SMP BSP Support
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2011.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#include <bsp.h>
17#include <bsp/bootcard.h>
18#include <cache_.h>
19#include <leon.h>
20#include <rtems/bspIo.h>
21#include <rtems/score/smpimpl.h>
22#include <stdlib.h>
23
24#if !defined(__leon__) || defined(RTEMS_PARAVIRT)
25uint32_t _CPU_SMP_Get_current_processor( void )
26{
27  return _LEON3_Get_current_processor();
28}
29#endif
30
31static rtems_isr bsp_inter_processor_interrupt(
32  rtems_vector_number vector
33)
34{
35  _SMP_Inter_processor_interrupt_handler();
36}
37
38void bsp_start_on_secondary_processor()
39{
40  uint32_t cpu_index_self = _CPU_SMP_Get_current_processor();
41
42  leon3_set_cache_control_register(0x80000F);
43  /* Unmask IPI interrupts at Interrupt controller for this CPU */
44  LEON3_IrqCtrl_Regs->mask[cpu_index_self] |= 1U << LEON3_MP_IRQ;
45
46  _SMP_Start_multitasking_on_secondary_processor();
47}
48
49uint32_t _CPU_SMP_Initialize( void )
50{
51  leon3_set_cache_control_register(0x80000F);
52
53  if ( rtems_configuration_get_maximum_processors() > 1 ) {
54    LEON_Unmask_interrupt(LEON3_MP_IRQ);
55    set_vector(bsp_inter_processor_interrupt, LEON_TRAP_TYPE(LEON3_MP_IRQ), 1);
56  }
57
58  return leon3_get_cpu_count(LEON3_IrqCtrl_Regs);
59}
60
61bool _CPU_SMP_Start_processor( uint32_t cpu_index )
62{
63  #if defined(RTEMS_DEBUG)
64    printk( "Waking CPU %d\n", cpu_index );
65  #endif
66
67  LEON3_IrqCtrl_Regs->mpstat = 1U << cpu_index;
68
69  return true;
70}
71
72void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
73{
74  (void) cpu_count;
75
76  /* Nothing to do */
77}
78
79void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
80{
81  /* send interrupt to destination CPU */
82  LEON3_IrqCtrl_Regs->force[target_processor_index] = 1 << LEON3_MP_IRQ;
83}
84
85void _BSP_Start_multitasking(
86  Context_Control *heir
87)
88{
89  _CPU_cache_invalidate_entire_instruction();
90  _CPU_Context_Restart_self( heir );
91}
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