1 | /* |
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2 | * pci.c : this file contains basic PCI Io functions. |
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3 | * |
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4 | * Copyright (C) 1999 valette@crf.canon.fr |
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5 | * |
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6 | * This code is heavily inspired by the public specification of STREAM V2 |
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7 | * that can be found at : |
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8 | * |
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9 | * <http://www.chorus.com/Documentation/index.html> by following |
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10 | * the STREAM API Specification Document link. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * pci.c,v 1.2.4.4 2004/11/10 22:15:01 joel Exp |
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17 | * |
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18 | * Till Straumann, <strauman@slac.stanford.edu>, 1/2002 |
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19 | * - separated bridge detection code out of this file |
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20 | * |
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21 | * |
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22 | * Adapted to GRPCI |
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23 | * Copyright (C) 2006 Gaisler Research |
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24 | * |
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25 | */ |
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26 | |
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27 | #include <pci.h> |
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28 | #include <stdlib.h> |
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29 | #include <rtems/bspIo.h> |
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30 | |
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31 | #define PCI_ADDR 0x80000400 |
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32 | #define DMAPCI_ADDR 0x80000500 |
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33 | #define PCI_CONF 0xfff50000 |
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34 | #define PCI_MEM_START 0xe0000000 |
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35 | #define PCI_MEM_END 0xf0000000 |
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36 | #define PCI_MEM_SIZE (PCI_MEM_START - PCI_MEM_END) |
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37 | |
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38 | /* If uncommented byte twisting is enabled */ |
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39 | /*#define BT_ENABLED 1*/ |
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40 | |
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41 | /* Define PCI_INFO to get a listing of configured devices at boot time */ |
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42 | #define PCI_INFO 1 |
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43 | |
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44 | #define DEBUG 1 |
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45 | |
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46 | #ifdef DEBUG |
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47 | #define DBG(x...) printk(x) |
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48 | #else |
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49 | #define DBG(x...) |
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50 | #endif |
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51 | |
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52 | /* allow for overriding these definitions */ |
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53 | #ifndef PCI_CONFIG_ADDR |
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54 | #define PCI_CONFIG_ADDR 0xcf8 |
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55 | #endif |
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56 | #ifndef PCI_CONFIG_DATA |
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57 | #define PCI_CONFIG_DATA 0xcfc |
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58 | #endif |
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59 | |
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60 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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61 | #define PCI_MULTI_FUNCTION 0x80 |
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62 | |
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63 | /* define a shortcut */ |
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64 | #define pci BSP_pci_configuration |
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65 | |
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66 | /* |
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67 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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68 | */ |
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69 | unsigned char ucMaxPCIBus; |
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70 | typedef struct { |
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71 | volatile unsigned int cfg_stat; |
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72 | volatile unsigned int bar0; |
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73 | volatile unsigned int page0; |
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74 | volatile unsigned int bar1; |
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75 | volatile unsigned int page1; |
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76 | volatile unsigned int iomap; |
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77 | volatile unsigned int stat_cmd; |
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78 | } LEON3_GRPCI_Regs_Map; |
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79 | |
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80 | LEON3_GRPCI_Regs_Map *pcic = (LEON3_GRPCI_Regs_Map *) PCI_ADDR; |
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81 | unsigned int *pcidma = (unsigned int *)DMAPCI_ADDR; |
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82 | |
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83 | struct pci_res { |
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84 | unsigned int size; |
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85 | unsigned char bar; |
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86 | unsigned char devfn; |
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87 | }; |
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88 | |
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89 | static inline unsigned int flip_dword (unsigned int l) |
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90 | { |
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91 | return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff); |
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92 | } |
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93 | |
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94 | |
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95 | /* The configuration access functions uses the DMA functionality of the |
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96 | * AT697 pci controller to be able access all slots |
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97 | */ |
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98 | |
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99 | |
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100 | static int |
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101 | BSP_pci_read_config_dword( |
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102 | unsigned char bus, |
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103 | unsigned char slot, |
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104 | unsigned char function, |
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105 | unsigned char offset, |
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106 | unsigned int *val |
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107 | ) |
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108 | { |
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109 | volatile unsigned int *pci_conf; |
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110 | |
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111 | if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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112 | |
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113 | if (slot > 21) { |
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114 | *val = 0xffffffff; |
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115 | return PCIBIOS_SUCCESSFUL; |
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116 | } |
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117 | |
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118 | pci_conf = (volatile unsigned int *) (PCI_CONF + |
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119 | ((slot<<11) | (function<<8) | offset)); |
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120 | |
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121 | #ifdef BT_ENABLED |
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122 | *val = flip_dword(*pci_conf); |
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123 | #else |
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124 | *val = *pci_conf; |
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125 | #endif |
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126 | |
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127 | if (pcic->cfg_stat & 0x100) { |
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128 | *val = 0xffffffff; |
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129 | } |
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130 | |
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131 | DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), *val); |
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132 | |
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133 | return PCIBIOS_SUCCESSFUL; |
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134 | } |
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135 | |
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136 | |
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137 | static int |
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138 | BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) { |
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139 | unsigned int v; |
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140 | |
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141 | if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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142 | |
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143 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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144 | *val = 0xffff & (v >> (8*(offset & 3))); |
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145 | |
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146 | return PCIBIOS_SUCCESSFUL; |
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147 | } |
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148 | |
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149 | |
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150 | static int |
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151 | BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) { |
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152 | unsigned int v; |
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153 | |
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154 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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155 | |
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156 | *val = 0xff & (v >> (8*(offset & 3))); |
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157 | |
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158 | return PCIBIOS_SUCCESSFUL; |
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159 | } |
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160 | |
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161 | |
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162 | static int |
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163 | BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int val) { |
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164 | |
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165 | volatile unsigned int *pci_conf; |
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166 | unsigned int value; |
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167 | |
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168 | if (offset & 3 || bus != 0) return PCIBIOS_BAD_REGISTER_NUMBER; |
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169 | |
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170 | |
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171 | pci_conf = (volatile unsigned int *) (PCI_CONF + |
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172 | ((slot<<11) | (function<<8) | (offset & ~3))); |
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173 | |
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174 | #ifdef BT_ENABLED |
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175 | value = flip_dword(val); |
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176 | #else |
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177 | value = val; |
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178 | #endif |
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179 | |
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180 | *pci_conf = value; |
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181 | |
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182 | DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), value); |
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183 | |
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184 | return PCIBIOS_SUCCESSFUL; |
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185 | } |
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186 | |
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187 | |
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188 | static int |
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189 | BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) { |
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190 | unsigned int v; |
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191 | |
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192 | if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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193 | |
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194 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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195 | |
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196 | v = (v & ~(0xffff << (8*(offset&3)))) | ((0xffff&val) << (8*(offset&3))); |
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197 | |
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198 | return pci_write_config_dword(bus, slot, function, offset&~3, v); |
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199 | } |
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200 | |
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201 | |
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202 | static int |
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203 | BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) { |
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204 | unsigned int v; |
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205 | |
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206 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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207 | |
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208 | v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3))); |
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209 | |
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210 | return pci_write_config_dword(bus, slot, function, offset&~3, v); |
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211 | } |
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212 | |
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213 | |
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214 | |
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215 | const pci_config_access_functions pci_access_functions = { |
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216 | BSP_pci_read_config_byte, |
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217 | BSP_pci_read_config_word, |
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218 | BSP_pci_read_config_dword, |
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219 | BSP_pci_write_config_byte, |
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220 | BSP_pci_write_config_word, |
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221 | BSP_pci_write_config_dword |
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222 | }; |
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223 | |
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224 | pci_config BSP_pci_configuration = { (volatile unsigned char*)PCI_CONFIG_ADDR, |
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225 | (volatile unsigned char*)PCI_CONFIG_DATA, |
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226 | &pci_access_functions }; |
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227 | |
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228 | |
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229 | |
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230 | |
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231 | int init_grpci(void) { |
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232 | |
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233 | volatile unsigned int *page0 = (unsigned volatile int *) PCI_MEM_START; |
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234 | unsigned int data, addr; |
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235 | |
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236 | #ifndef BT_ENABLED |
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237 | pci_write_config_dword(0,0,0,0x10, 0xffffffff); |
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238 | pci_read_config_dword(0,0,0,0x10, &addr); |
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239 | pci_write_config_dword(0,0,0,0x10, flip_dword(0x10000000)); /* Setup bar0 to nonzero value (grpci considers BAR==0 as invalid) */ |
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240 | addr = (~flip_dword(addr)+1)>>1; /* page0 is accessed through upper half of bar0 */ |
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241 | pcic->cfg_stat |= 0x10000000; /* Setup mmap reg so we can reach bar0 */ |
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242 | page0[addr/4] = 0; /* Disable bytetwisting ... */ |
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243 | #endif |
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244 | |
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245 | /* set 1:1 mapping between AHB -> PCI memory */ |
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246 | pcic->cfg_stat = (pcic->cfg_stat & 0x0fffffff) | PCI_MEM_START; |
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247 | |
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248 | /* and map system RAM at pci address 0x40000000 */ |
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249 | pci_write_config_dword(0, 0, 0, 0x14, 0x40000000); |
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250 | pcic->page1 = 0x40000000; |
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251 | |
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252 | /* set as bus master and enable pci memory responses */ |
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253 | pci_read_config_dword(0, 0, 0, 0x4, &data); |
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254 | pci_write_config_dword(0, 0, 0, 0x4, data | 0x6); |
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255 | |
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256 | return 0; |
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257 | } |
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258 | |
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259 | /* DMA functions which uses GRPCIs optional DMA controller (len in words) */ |
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260 | int dma_to_pci(unsigned int ahb_addr, unsigned int pci_addr, unsigned int len) { |
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261 | int ret = 0; |
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262 | |
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263 | pcidma[0] = 0x82; |
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264 | pcidma[1] = ahb_addr; |
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265 | pcidma[2] = pci_addr; |
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266 | pcidma[3] = len; |
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267 | pcidma[0] = 0x83; |
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268 | |
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269 | while ( (pcidma[0] & 0x4) == 0) |
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270 | ; |
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271 | |
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272 | if (pcidma[0] & 0x8) { /* error */ |
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273 | ret = -1; |
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274 | } |
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275 | |
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276 | pcidma[0] |= 0xC; |
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277 | return ret; |
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278 | |
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279 | } |
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280 | |
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281 | int dma_from_pci(unsigned int ahb_addr, unsigned int pci_addr, unsigned int len) { |
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282 | int ret = 0; |
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283 | |
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284 | pcidma[0] = 0x80; |
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285 | pcidma[1] = ahb_addr; |
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286 | pcidma[2] = pci_addr; |
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287 | pcidma[3] = len; |
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288 | pcidma[0] = 0x81; |
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289 | |
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290 | while ( (pcidma[0] & 0x4) == 0) |
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291 | ; |
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292 | |
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293 | if (pcidma[0] & 0x8) { /* error */ |
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294 | ret = -1; |
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295 | } |
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296 | |
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297 | pcidma[0] |= 0xC; |
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298 | return ret; |
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299 | |
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300 | } |
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301 | |
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302 | |
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303 | void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function) { |
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304 | unsigned int data; |
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305 | |
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306 | pci_read_config_dword(0, slot, function, PCI_COMMAND, &data); |
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307 | pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY); |
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308 | |
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309 | } |
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310 | |
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311 | void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function) { |
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312 | unsigned int data; |
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313 | |
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314 | pci_read_config_dword(0, slot, function, PCI_COMMAND, &data); |
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315 | pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER); |
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316 | |
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317 | } |
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318 | |
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319 | static inline void swap_res(struct pci_res **p1, struct pci_res **p2) { |
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320 | |
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321 | struct pci_res *tmp = *p1; |
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322 | *p1 = *p2; |
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323 | *p2 = tmp; |
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324 | |
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325 | } |
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326 | |
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327 | /* pci_allocate_resources |
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328 | * |
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329 | * This function scans the bus and assigns PCI addresses to all devices. It handles both |
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330 | * single function and multi function devices. All allocated devices are enabled and |
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331 | * latency timers are set to 40. |
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332 | * |
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333 | * NOTE that it only allocates PCI memory space devices (that are at least 1 KB). |
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334 | * IO spaces are not enabled. Also, it does not handle pci-pci bridges. They are left disabled. |
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335 | * |
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336 | * |
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337 | */ |
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338 | void pci_allocate_resources(void) { |
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339 | |
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340 | unsigned int slot, numfuncs, func, id, pos, size, tmp, i, swapped, addr, dev, fn; |
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341 | unsigned char header; |
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342 | struct pci_res **res; |
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343 | |
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344 | res = (struct pci_res **) malloc(sizeof(struct pci_res *)*32*8*6); |
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345 | |
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346 | for (i = 0; i < 32*8*6; i++) { |
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347 | res[i] = (struct pci_res *) malloc(sizeof(struct pci_res)); |
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348 | res[i]->size = 0; |
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349 | res[i]->devfn = i; |
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350 | } |
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351 | |
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352 | for(slot = 1; slot < PCI_MAX_DEVICES; slot++) { |
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353 | |
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354 | pci_read_config_dword(0, slot, 0, PCI_VENDOR_ID, &id); |
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355 | |
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356 | if(id == PCI_INVALID_VENDORDEVICEID || id == 0) { |
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357 | /* |
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358 | * This slot is empty |
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359 | */ |
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360 | continue; |
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361 | } |
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362 | |
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363 | pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); |
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364 | |
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365 | if(header & PCI_MULTI_FUNCTION) { |
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366 | numfuncs = PCI_MAX_FUNCTIONS; |
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367 | } |
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368 | else { |
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369 | numfuncs = 1; |
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370 | } |
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371 | |
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372 | for(func = 0; func < numfuncs; func++) { |
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373 | |
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374 | pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id); |
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375 | if(id == PCI_INVALID_VENDORDEVICEID || id == 0) { |
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376 | continue; |
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377 | } |
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378 | |
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379 | pci_read_config_dword(0, slot, func, PCI_CLASS_REVISION, &tmp); |
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380 | tmp >>= 16; |
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381 | if (tmp == PCI_CLASS_BRIDGE_PCI) { |
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382 | continue; |
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383 | } |
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384 | |
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385 | for (pos = 0; pos < 6; pos++) { |
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386 | pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff); |
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387 | pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), &size); |
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388 | |
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389 | if (size == 0 || size == 0xffffffff || (size & 0x3f1) != 0){ |
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390 | pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0); |
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391 | continue; |
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392 | |
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393 | }else { |
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394 | size &= 0xfffffff0; |
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395 | res[slot*8*6+func*6+pos]->size = ~size+1; |
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396 | res[slot*8*6+func*6+pos]->devfn = slot*8 + func; |
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397 | res[slot*8*6+func*6+pos]->bar = pos; |
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398 | |
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399 | DBG("Slot: %d, function: %d, bar%d size: %x\n", slot, func, pos, ~size+1); |
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400 | } |
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401 | } |
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402 | } |
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403 | } |
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404 | |
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405 | |
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406 | /* Sort the resources in descending order */ |
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407 | swapped = 1; |
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408 | while (swapped == 1) { |
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409 | swapped = 0; |
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410 | for (i = 0; i < 32*8*6-1; i++) { |
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411 | if (res[i]->size < res[i+1]->size) { |
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412 | swap_res(&res[i], &res[i+1]); |
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413 | swapped = 1; |
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414 | } |
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415 | } |
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416 | i++; |
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417 | } |
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418 | |
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419 | /* Assign the BARs */ |
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420 | addr = PCI_MEM_START; |
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421 | for (i = 0; i < 32*8*6; i++) { |
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422 | |
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423 | if (res[i]->size == 0) { |
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424 | goto done; |
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425 | } |
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426 | if ( (addr + res[i]->size) > PCI_MEM_END) { |
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427 | printk("Out of PCI memory space, all devices not configured.\n"); |
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428 | goto done; |
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429 | } |
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430 | |
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431 | dev = res[i]->devfn >> 3; |
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432 | fn = res[i]->devfn & 7; |
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433 | |
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434 | DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar); |
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435 | pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr); |
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436 | addr += res[i]->size; |
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437 | |
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438 | /* Set latency timer to 64 */ |
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439 | pci_read_config_dword(0, dev, fn, 0xC, &tmp); |
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440 | pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000); |
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441 | |
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442 | pci_mem_enable(0, dev, fn); |
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443 | |
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444 | } |
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445 | |
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446 | |
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447 | |
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448 | done: |
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449 | |
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450 | #ifdef PCI_INFO |
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451 | printk("\nPCI devices found and configured:\n"); |
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452 | for (slot = 1; slot < PCI_MAX_DEVICES; slot++) { |
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453 | |
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454 | pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); |
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455 | |
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456 | if(header & PCI_MULTI_FUNCTION) { |
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457 | numfuncs = PCI_MAX_FUNCTIONS; |
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458 | } |
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459 | else { |
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460 | numfuncs = 1; |
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461 | } |
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462 | |
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463 | for (func = 0; func < numfuncs; func++) { |
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464 | |
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465 | pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp); |
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466 | |
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467 | if (tmp & PCI_COMMAND_MEMORY) { |
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468 | |
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469 | pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id); |
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470 | |
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471 | if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue; |
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472 | |
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473 | printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16); |
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474 | |
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475 | for (pos = 0; pos < 6; pos++) { |
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476 | pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + pos*4, &tmp); |
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477 | |
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478 | if (tmp != 0 && tmp != 0xffffffff && (tmp & 0x3f1) == 0) { |
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479 | |
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480 | printk("\tBAR %d: %x\n", pos, tmp); |
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481 | } |
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482 | |
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483 | } |
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484 | printk("\n"); |
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485 | |
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486 | } |
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487 | |
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488 | } |
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489 | } |
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490 | printk("\n"); |
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491 | #endif |
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492 | |
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493 | for (i = 0; i < 1536; i++) { |
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494 | free(res[i]); |
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495 | } |
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496 | free(res); |
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497 | } |
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498 | |
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499 | |
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500 | |
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501 | int init_pci(void) |
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502 | { |
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503 | unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs; |
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504 | unsigned char ucHeader; |
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505 | unsigned char ucMaxSubordinate; |
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506 | unsigned int ulClass, ulDeviceID; |
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507 | |
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508 | DBG("Initializing PCI\n"); |
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509 | if ( init_grpci() ) { |
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510 | return -1; |
---|
511 | } |
---|
512 | pci_allocate_resources(); |
---|
513 | DBG("PCI resource allocation done\n"); |
---|
514 | /* |
---|
515 | * Scan PCI bus 0 looking for PCI-PCI bridges |
---|
516 | */ |
---|
517 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
---|
518 | (void)pci_read_config_dword(0, |
---|
519 | ucSlotNumber, |
---|
520 | 0, |
---|
521 | PCI_VENDOR_ID, |
---|
522 | &ulDeviceID); |
---|
523 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
---|
524 | /* |
---|
525 | * This slot is empty |
---|
526 | */ |
---|
527 | continue; |
---|
528 | } |
---|
529 | (void)pci_read_config_byte(0, |
---|
530 | ucSlotNumber, |
---|
531 | 0, |
---|
532 | PCI_HEADER_TYPE, |
---|
533 | &ucHeader); |
---|
534 | if(ucHeader&PCI_MULTI_FUNCTION) { |
---|
535 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
---|
536 | } |
---|
537 | else { |
---|
538 | ucNumFuncs=1; |
---|
539 | } |
---|
540 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
---|
541 | (void)pci_read_config_dword(0, |
---|
542 | ucSlotNumber, |
---|
543 | ucFnNumber, |
---|
544 | PCI_VENDOR_ID, |
---|
545 | &ulDeviceID); |
---|
546 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
---|
547 | /* |
---|
548 | * This slot/function is empty |
---|
549 | */ |
---|
550 | continue; |
---|
551 | } |
---|
552 | |
---|
553 | /* |
---|
554 | * This slot/function has a device fitted. |
---|
555 | */ |
---|
556 | (void)pci_read_config_dword(0, |
---|
557 | ucSlotNumber, |
---|
558 | ucFnNumber, |
---|
559 | PCI_CLASS_REVISION, |
---|
560 | &ulClass); |
---|
561 | ulClass >>= 16; |
---|
562 | if (ulClass == PCI_CLASS_BRIDGE_PCI) { |
---|
563 | /* |
---|
564 | * We have found a PCI-PCI bridge |
---|
565 | */ |
---|
566 | (void)pci_read_config_byte(0, |
---|
567 | ucSlotNumber, |
---|
568 | ucFnNumber, |
---|
569 | PCI_SUBORDINATE_BUS, |
---|
570 | &ucMaxSubordinate); |
---|
571 | if(ucMaxSubordinate>ucMaxPCIBus) { |
---|
572 | ucMaxPCIBus=ucMaxSubordinate; |
---|
573 | } |
---|
574 | } |
---|
575 | } |
---|
576 | } |
---|
577 | return 0; |
---|
578 | } |
---|
579 | |
---|
580 | /* |
---|
581 | * Return the number of PCI busses in the system |
---|
582 | */ |
---|
583 | unsigned char BusCountPCI(void) |
---|
584 | { |
---|
585 | return(ucMaxPCIBus+1); |
---|
586 | } |
---|