1 | /* leon.h |
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2 | * |
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3 | * LEON3 BSP data types and macros. |
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4 | * |
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5 | * COPYRIGHT (c) 1989-1998. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * |
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8 | * Modified for LEON3 BSP. |
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9 | * COPYRIGHT (c) 2004. |
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10 | * Gaisler Research. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #ifndef _INCLUDE_LEON_h |
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20 | #define _INCLUDE_LEON_h |
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21 | |
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22 | #include <rtems/score/sparc.h> |
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23 | #include <amba.h> |
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24 | |
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25 | #ifdef __cplusplus |
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26 | extern "C" { |
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27 | #endif |
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28 | |
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29 | #define LEON_INTERRUPT_EXTERNAL_1 5 |
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30 | |
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31 | #ifndef ASM |
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32 | /* |
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33 | * Trap Types for on-chip peripherals |
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34 | * |
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35 | * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments |
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36 | * |
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37 | * NOTE: The priority level for each source corresponds to the least |
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38 | * significant nibble of the trap type. |
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39 | */ |
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40 | |
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41 | #define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) |
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42 | |
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43 | #define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) |
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44 | |
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45 | #define LEON_INT_TRAP( _trap ) \ |
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46 | ( (_trap) >= 0x11 && \ |
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47 | (_trap) <= 0x1F ) |
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48 | |
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49 | /* |
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50 | * Structure for LEON memory mapped registers. |
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51 | * |
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52 | * Source: Section 6.1 - On-chip registers |
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53 | * |
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54 | * NOTE: There is only one of these structures per CPU, its base address |
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55 | * is 0x80000000, and the variable LEON_REG is placed there by the |
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56 | * linkcmds file. |
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57 | */ |
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58 | |
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59 | /* Leon uses dynamic register mapping using amba configuration records, |
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60 | * LEON_Register_Map is obsolete |
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61 | */ |
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62 | /* |
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63 | typedef struct { |
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64 | volatile unsigned int Memory_Config_1; |
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65 | volatile unsigned int Memory_Config_2; |
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66 | volatile unsigned int Edac_Control; |
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67 | volatile unsigned int Failed_Address; |
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68 | volatile unsigned int Memory_Status; |
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69 | volatile unsigned int Cache_Control; |
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70 | volatile unsigned int Power_Down; |
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71 | volatile unsigned int Write_Protection_1; |
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72 | volatile unsigned int Write_Protection_2; |
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73 | volatile unsigned int Leon_Configuration; |
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74 | volatile unsigned int dummy2; |
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75 | volatile unsigned int dummy3; |
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76 | volatile unsigned int dummy4; |
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77 | volatile unsigned int dummy5; |
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78 | volatile unsigned int dummy6; |
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79 | volatile unsigned int dummy7; |
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80 | volatile unsigned int Timer_Counter_1; |
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81 | volatile unsigned int Timer_Reload_1; |
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82 | volatile unsigned int Timer_Control_1; |
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83 | volatile unsigned int Watchdog; |
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84 | volatile unsigned int Timer_Counter_2; |
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85 | volatile unsigned int Timer_Reload_2; |
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86 | volatile unsigned int Timer_Control_2; |
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87 | volatile unsigned int dummy8; |
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88 | volatile unsigned int Scaler_Counter; |
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89 | volatile unsigned int Scaler_Reload; |
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90 | volatile unsigned int dummy9; |
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91 | volatile unsigned int dummy10; |
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92 | volatile unsigned int UART_Channel_1; |
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93 | volatile unsigned int UART_Status_1; |
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94 | volatile unsigned int UART_Control_1; |
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95 | volatile unsigned int UART_Scaler_1; |
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96 | volatile unsigned int UART_Channel_2; |
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97 | volatile unsigned int UART_Status_2; |
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98 | volatile unsigned int UART_Control_2; |
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99 | volatile unsigned int UART_Scaler_2; |
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100 | volatile unsigned int Interrupt_Mask; |
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101 | volatile unsigned int Interrupt_Pending; |
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102 | volatile unsigned int Interrupt_Force; |
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103 | volatile unsigned int Interrupt_Clear; |
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104 | volatile unsigned int PIO_Data; |
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105 | volatile unsigned int PIO_Direction; |
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106 | volatile unsigned int PIO_Interrupt; |
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107 | } LEON_Register_Map; |
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108 | */ |
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109 | |
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110 | typedef struct { |
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111 | volatile unsigned int data; |
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112 | volatile unsigned int status; |
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113 | volatile unsigned int ctrl; |
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114 | } LEON3_UART_Regs_Map; |
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115 | |
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116 | typedef struct { |
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117 | volatile unsigned int value; |
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118 | volatile unsigned int reload; |
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119 | volatile unsigned int conf; |
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120 | volatile unsigned int notused; |
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121 | } LEON3_Timer_SubType; |
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122 | |
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123 | typedef struct { |
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124 | volatile unsigned int scaler_value; /* common timer registers */ |
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125 | volatile unsigned int scaler_reload; |
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126 | volatile unsigned int status; |
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127 | volatile unsigned int notused; |
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128 | LEON3_Timer_SubType timer[8]; |
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129 | } LEON3_Timer_Regs_Map; |
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130 | |
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131 | typedef struct { |
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132 | volatile unsigned int iodata; |
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133 | volatile unsigned int ioout; |
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134 | volatile unsigned int iodir; |
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135 | volatile unsigned int irqmask; |
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136 | volatile unsigned int irqpol; |
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137 | volatile unsigned int irqedge; |
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138 | } LEON3_IOPORT_Regs_Map; |
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139 | |
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140 | /* /\* */ |
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141 | /* * This is used to manipulate the on-chip registers. */ |
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142 | /* * */ |
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143 | /* * The following symbol must be defined in the linkcmds file and point */ |
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144 | /* * to the correct location. */ |
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145 | /* *\/ */ |
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146 | /* Leon uses dynamic register mapping using amba configuration records */ |
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147 | /* LEON_Register_Map is obsolete */ |
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148 | /* extern LEON_Register_Map LEON_REG; */ |
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149 | |
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150 | #endif |
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151 | |
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152 | /* |
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153 | * The following defines the bits in Memory Configuration Register 1. |
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154 | */ |
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155 | |
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156 | #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 |
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157 | |
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158 | /* |
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159 | * The following defines the bits in Memory Configuration Register 1. |
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160 | */ |
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161 | |
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162 | #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 |
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163 | |
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164 | |
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165 | /* |
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166 | * The following defines the bits in the Timer Control Register. |
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167 | */ |
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168 | |
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169 | #define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ |
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170 | /* 0 = hold scalar and counter */ |
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171 | #define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ |
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172 | /* 0 = stop at 0 */ |
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173 | #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ |
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174 | /* 0 = no function */ |
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175 | |
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176 | /* |
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177 | * The following defines the bits in the UART Control Registers. |
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178 | * |
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179 | */ |
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180 | |
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181 | #define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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182 | |
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183 | /* |
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184 | * The following defines the bits in the LEON UART Status Registers. |
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185 | */ |
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186 | |
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187 | #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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188 | #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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189 | #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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190 | #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ |
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191 | #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ |
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192 | #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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193 | #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ |
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194 | #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ |
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195 | |
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196 | |
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197 | /* |
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198 | * The following defines the bits in the LEON UART Status Registers. |
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199 | */ |
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200 | |
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201 | #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ |
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202 | #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ |
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203 | #define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ |
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204 | #define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ |
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205 | #define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ |
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206 | #define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ |
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207 | #define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ |
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208 | #define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ |
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209 | |
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210 | extern volatile LEON3_IrqCtrl_Regs_Map *LEON3_IrqCtrl_Regs; /* LEON3 Interrupt Controller */ |
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211 | extern volatile LEON3_Timer_Regs_Map *LEON3_Timer_Regs; /* LEON3 GP Timer */ |
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212 | extern volatile LEON3_UART_Regs_Map *LEON3_Console_Uart[LEON3_APBUARTS]; |
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213 | |
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214 | extern int LEON3_Cpu_Index; |
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215 | |
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216 | /* Macros used for manipulating bits in LEON3 GP Timer Control Register */ |
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217 | |
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218 | #define LEON3_GPTIMER_EN 1 |
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219 | #define LEON3_GPTIMER_RL 2 |
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220 | #define LEON3_GPTIMER_LD 4 |
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221 | #define LEON3_GPTIMER_IRQEN 8 |
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222 | |
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223 | #define LEON3_MP_IRQ 14 /* Irq used by shared memory driver */ |
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224 | |
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225 | #define LEON3_IRQMPSTATUS_CPUNR 28 |
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226 | #define LEON3_IRQMPSTATUS_BROADCAST 27 |
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227 | |
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228 | |
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229 | #ifndef ASM |
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230 | |
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231 | /* |
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232 | * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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233 | * and the Interrupt Pending Registers. |
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234 | * |
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235 | * NOTE: For operations which are not atomic, this code disables interrupts |
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236 | * to guarantee there are no intervening accesses to the same register. |
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237 | * The operations which read the register, modify the value and then |
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238 | * store the result back are vulnerable. |
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239 | */ |
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240 | |
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241 | #define LEON_Clear_interrupt( _source ) \ |
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242 | do { \ |
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243 | LEON3_IrqCtrl_Regs->iclear = (1 << (_source)); \ |
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244 | } while (0) |
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245 | |
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246 | #define LEON_Force_interrupt( _source ) \ |
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247 | do { \ |
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248 | LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \ |
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249 | } while (0) |
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250 | |
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251 | #define LEON_Is_interrupt_pending( _source ) \ |
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252 | (LEON3_IrqCtrl_Regs->ipend & (1 << (_source))) |
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253 | |
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254 | #define LEON_Is_interrupt_masked( _source ) \ |
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255 | do {\ |
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256 | (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & (1 << (_source))); \ |
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257 | } while (0) |
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258 | |
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259 | |
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260 | #define LEON_Mask_interrupt( _source ) \ |
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261 | do { \ |
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262 | uint32_t _level; \ |
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263 | _level = sparc_disable_interrupts(); \ |
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264 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] &= ~(1 << (_source)); \ |
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265 | sparc_enable_interrupts( _level ); \ |
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266 | } while (0) |
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267 | |
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268 | #define LEON_Unmask_interrupt( _source ) \ |
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269 | do { \ |
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270 | uint32_t _level; \ |
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271 | _level = sparc_disable_interrupts(); \ |
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272 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] |= (1 << (_source)); \ |
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273 | sparc_enable_interrupts( _level ); \ |
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274 | } while (0) |
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275 | |
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276 | #define LEON_Disable_interrupt( _source, _previous ) \ |
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277 | do { \ |
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278 | uint32_t _level; \ |
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279 | uint32_t _mask = 1 << (_source); \ |
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280 | _level = sparc_disable_interrupts(); \ |
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281 | (_previous) = LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index]; \ |
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282 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = _previous & ~_mask; \ |
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283 | sparc_enable_interrupts( _level ); \ |
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284 | (_previous) &= _mask; \ |
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285 | } while (0) |
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286 | |
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287 | #define LEON_Restore_interrupt( _source, _previous ) \ |
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288 | do { \ |
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289 | uint32_t _level; \ |
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290 | uint32_t _mask = 1 << (_source); \ |
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291 | _level = sparc_disable_interrupts(); \ |
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292 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = \ |
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293 | (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & ~_mask) | (_previous); \ |
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294 | sparc_enable_interrupts( _level ); \ |
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295 | } while (0) |
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296 | |
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297 | |
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298 | /* |
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299 | * Each timer control register is organized as follows: |
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300 | * |
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301 | * D0 - Enable |
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302 | * 1 = enable counting |
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303 | * 0 = hold scaler and counter |
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304 | * |
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305 | * D1 - Counter Reload |
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306 | * 1 = reload counter at zero and restart |
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307 | * 0 = stop counter at zero |
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308 | * |
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309 | * D2 - Counter Load |
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310 | * 1 = load counter with preset value |
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311 | * 0 = no function |
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312 | * |
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313 | */ |
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314 | |
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315 | #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 |
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316 | #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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317 | |
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318 | #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 |
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319 | |
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320 | #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 |
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321 | #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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322 | |
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323 | #define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 |
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324 | #define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 |
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325 | |
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326 | #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 |
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327 | #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 |
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328 | |
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329 | #endif /* !ASM */ |
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330 | |
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331 | #ifdef __cplusplus |
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332 | } |
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333 | #endif |
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334 | |
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335 | #endif /* !_INCLUDE_LEON_h */ |
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336 | /* end of include file */ |
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337 | |
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