1 | /** |
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2 | * @file |
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3 | * @ingroup sparc_leon3 |
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4 | * @brief LEON3 BSP data types and macros |
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5 | */ |
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6 | |
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7 | /* leon.h |
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8 | * |
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9 | * LEON3 BSP data types and macros. |
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10 | * |
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11 | * COPYRIGHT (c) 1989-1998. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * Modified for LEON3 BSP. |
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15 | * COPYRIGHT (c) 2004. |
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16 | * Gaisler Research. |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef _INCLUDE_LEON_h |
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24 | #define _INCLUDE_LEON_h |
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25 | |
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26 | #include <rtems.h> |
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27 | #include <amba.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif |
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32 | |
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33 | #define LEON_INTERRUPT_EXTERNAL_1 5 |
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34 | |
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35 | #ifndef ASM |
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36 | /* |
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37 | * Trap Types for on-chip peripherals |
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38 | * |
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39 | * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments |
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40 | * |
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41 | * NOTE: The priority level for each source corresponds to the least |
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42 | * significant nibble of the trap type. |
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43 | */ |
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44 | |
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45 | #define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) |
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46 | |
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47 | #define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) |
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48 | |
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49 | #define LEON_INT_TRAP( _trap ) \ |
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50 | ( (_trap) >= 0x11 && \ |
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51 | (_trap) <= 0x1F ) |
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52 | |
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53 | /* /\* */ |
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54 | /* * This is used to manipulate the on-chip registers. */ |
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55 | /* * */ |
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56 | /* * The following symbol must be defined in the linkcmds file and point */ |
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57 | /* * to the correct location. */ |
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58 | /* *\/ */ |
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59 | /* Leon uses dynamic register mapping using amba configuration records */ |
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60 | /* LEON_Register_Map is obsolete */ |
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61 | /* extern LEON_Register_Map LEON_REG; */ |
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62 | |
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63 | #endif |
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64 | |
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65 | /* |
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66 | * The following defines the bits in Memory Configuration Register 1. |
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67 | */ |
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68 | |
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69 | #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 |
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70 | |
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71 | /* |
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72 | * The following defines the bits in Memory Configuration Register 1. |
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73 | */ |
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74 | |
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75 | #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 |
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76 | |
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77 | |
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78 | /* |
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79 | * The following defines the bits in the Timer Control Register. |
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80 | */ |
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81 | |
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82 | #define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ |
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83 | /* 0 = hold scalar and counter */ |
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84 | #define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ |
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85 | /* 0 = stop at 0 */ |
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86 | #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ |
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87 | /* 0 = no function */ |
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88 | |
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89 | /* |
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90 | * The following defines the bits in the UART Control Registers. |
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91 | */ |
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92 | |
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93 | #define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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94 | |
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95 | /* |
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96 | * The following defines the bits in the LEON UART Status Register. |
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97 | */ |
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98 | |
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99 | #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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100 | #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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101 | #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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102 | #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ |
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103 | #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ |
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104 | #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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105 | #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ |
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106 | #define LEON_REG_UART_STATUS_TF 0x00000200 /* FIFO Full */ |
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107 | #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ |
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108 | |
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109 | /* |
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110 | * The following defines the bits in the LEON UART Control Register. |
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111 | */ |
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112 | |
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113 | #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ |
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114 | #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ |
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115 | #define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ |
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116 | #define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ |
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117 | #define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ |
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118 | #define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ |
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119 | #define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ |
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120 | #define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ |
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121 | #define LEON_REG_UART_CTRL_DB 0x00000800 /* Debug FIFO enable */ |
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122 | #define LEON_REG_UART_CTRL_SI 0x00004000 /* TX shift register empty IRQ enable */ |
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123 | #define LEON_REG_UART_CTRL_FA 0x80000000 /* FIFO Available */ |
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124 | #define LEON_REG_UART_CTRL_FA_BIT 31 |
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125 | |
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126 | /* |
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127 | * The following defines the bits in the LEON Cache Control Register. |
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128 | */ |
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129 | #define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ |
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130 | #define LEON3_REG_CACHE_CTRL_DS 0x00800000 /* Data cache snooping */ |
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131 | |
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132 | /* LEON3 Interrupt Controller */ |
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133 | extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; |
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134 | extern struct ambapp_dev *LEON3_IrqCtrl_Adev; |
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135 | |
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136 | /* LEON3 GP Timer */ |
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137 | extern volatile struct gptimer_regs *LEON3_Timer_Regs; |
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138 | extern struct ambapp_dev *LEON3_Timer_Adev; |
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139 | |
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140 | /* LEON3 CPU Index of boot CPU */ |
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141 | extern uint32_t LEON3_Cpu_Index; |
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142 | |
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143 | /* The external IRQ number, -1 if not external interrupts */ |
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144 | extern int LEON3_IrqCtrl_EIrq; |
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145 | |
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146 | static __inline__ int bsp_irq_fixup(int irq) |
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147 | { |
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148 | int eirq, cpu; |
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149 | |
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150 | if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { |
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151 | /* Get interrupt number from IRQ controller */ |
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152 | cpu = _LEON3_Get_current_processor(); |
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153 | eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; |
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154 | if (eirq & 0x10) |
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155 | irq = eirq; |
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156 | } |
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157 | |
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158 | return irq; |
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159 | } |
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160 | |
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161 | /* Macros used for manipulating bits in LEON3 GP Timer Control Register */ |
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162 | |
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163 | #define LEON3_IRQMPSTATUS_CPUNR 28 |
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164 | #define LEON3_IRQMPSTATUS_BROADCAST 27 |
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165 | |
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166 | |
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167 | #ifndef ASM |
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168 | |
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169 | /* |
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170 | * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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171 | * and the Interrupt Pending Registers. |
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172 | * |
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173 | * NOTE: For operations which are not atomic, this code disables interrupts |
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174 | * to guarantee there are no intervening accesses to the same register. |
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175 | * The operations which read the register, modify the value and then |
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176 | * store the result back are vulnerable. |
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177 | */ |
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178 | |
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179 | extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; |
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180 | |
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181 | #define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ |
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182 | rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) |
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183 | |
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184 | #define LEON3_IRQCTRL_RELEASE( _lock_context ) \ |
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185 | rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) |
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186 | |
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187 | #define LEON_Clear_interrupt( _source ) \ |
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188 | do { \ |
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189 | LEON3_IrqCtrl_Regs->iclear = (1U << (_source)); \ |
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190 | } while (0) |
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191 | |
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192 | #define LEON_Force_interrupt( _source ) \ |
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193 | do { \ |
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194 | LEON3_IrqCtrl_Regs->iforce = (1U << (_source)); \ |
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195 | } while (0) |
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196 | |
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197 | #define LEON_Enable_interrupt_broadcast( _source ) \ |
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198 | do { \ |
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199 | rtems_interrupt_lock_context _lock_context; \ |
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200 | uint32_t _mask = 1U << ( _source ); \ |
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201 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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202 | LEON3_IrqCtrl_Regs->bcast |= _mask; \ |
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203 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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204 | } while (0) |
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205 | |
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206 | #define LEON_Disable_interrupt_broadcast( _source ) \ |
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207 | do { \ |
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208 | rtems_interrupt_lock_context _lock_context; \ |
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209 | uint32_t _mask = 1U << ( _source ); \ |
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210 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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211 | LEON3_IrqCtrl_Regs->bcast &= ~_mask; \ |
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212 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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213 | } while (0) |
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214 | |
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215 | #define LEON_Is_interrupt_pending( _source ) \ |
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216 | (LEON3_IrqCtrl_Regs->ipend & (1U << (_source))) |
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217 | |
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218 | #define LEON_Cpu_Is_interrupt_masked( _source, _cpu ) \ |
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219 | (!(LEON3_IrqCtrl_Regs->mask[_cpu] & (1U << (_source)))) |
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220 | |
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221 | #define LEON_Cpu_Mask_interrupt( _source, _cpu ) \ |
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222 | do { \ |
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223 | rtems_interrupt_lock_context _lock_context; \ |
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224 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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225 | LEON3_IrqCtrl_Regs->mask[_cpu] &= ~(1U << (_source)); \ |
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226 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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227 | } while (0) |
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228 | |
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229 | #define LEON_Cpu_Unmask_interrupt( _source, _cpu ) \ |
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230 | do { \ |
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231 | rtems_interrupt_lock_context _lock_context; \ |
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232 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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233 | LEON3_IrqCtrl_Regs->mask[_cpu] |= (1U << (_source)); \ |
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234 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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235 | } while (0) |
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236 | |
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237 | #define LEON_Cpu_Disable_interrupt( _source, _previous, _cpu ) \ |
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238 | do { \ |
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239 | rtems_interrupt_lock_context _lock_context; \ |
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240 | uint32_t _mask = 1U << (_source); \ |
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241 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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242 | (_previous) = LEON3_IrqCtrl_Regs->mask[_cpu]; \ |
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243 | LEON3_IrqCtrl_Regs->mask[_cpu] = _previous & ~_mask; \ |
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244 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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245 | (_previous) &= _mask; \ |
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246 | } while (0) |
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247 | |
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248 | #define LEON_Cpu_Restore_interrupt( _source, _previous, _cpu ) \ |
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249 | do { \ |
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250 | rtems_interrupt_lock_context _lock_context; \ |
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251 | uint32_t _mask = 1U << (_source); \ |
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252 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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253 | LEON3_IrqCtrl_Regs->mask[_cpu] = \ |
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254 | (LEON3_IrqCtrl_Regs->mask[_cpu] & ~_mask) | (_previous); \ |
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255 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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256 | } while (0) |
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257 | |
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258 | /* Map single-cpu operations to local CPU */ |
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259 | #define LEON_Is_interrupt_masked( _source ) \ |
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260 | LEON_Cpu_Is_interrupt_masked(_source, _LEON3_Get_current_processor()) |
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261 | |
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262 | #define LEON_Mask_interrupt(_source) \ |
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263 | LEON_Cpu_Mask_interrupt(_source, _LEON3_Get_current_processor()) |
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264 | |
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265 | #define LEON_Unmask_interrupt(_source) \ |
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266 | LEON_Cpu_Unmask_interrupt(_source, _LEON3_Get_current_processor()) |
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267 | |
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268 | #define LEON_Disable_interrupt(_source, _previous) \ |
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269 | LEON_Cpu_Disable_interrupt(_source, _previous, _LEON3_Get_current_processor()) |
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270 | |
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271 | #define LEON_Restore_interrupt(_source, _previous) \ |
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272 | LEON_Cpu_Restore_interrupt(_source, _previous, _LEON3_Get_current_processor()) |
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273 | |
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274 | /* Make all SPARC BSPs have common macros for interrupt handling */ |
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275 | #define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) |
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276 | #define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) |
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277 | #define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) |
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278 | #define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) |
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279 | #define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) |
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280 | #define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) |
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281 | #define BSP_Disable_interrupt(_source, _previous) \ |
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282 | LEON_Disable_interrupt(_source, _prev) |
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283 | #define BSP_Restore_interrupt(_source, _previous) \ |
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284 | LEON_Restore_interrupt(_source, _previous) |
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285 | |
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286 | /* Make all SPARC BSPs have common macros for interrupt handling on any CPU */ |
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287 | #define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \ |
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288 | LEON_Cpu_Is_interrupt_masked(_source, _cpu) |
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289 | #define BSP_Cpu_Unmask_interrupt(_source, _cpu) \ |
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290 | LEON_Cpu_Unmask_interrupt(_source, _cpu) |
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291 | #define BSP_Cpu_Mask_interrupt(_source, _cpu) \ |
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292 | LEON_Cpu_Mask_interrupt(_source, _cpu) |
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293 | #define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \ |
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294 | LEON_Cpu_Disable_interrupt(_source, _prev, _cpu) |
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295 | #define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \ |
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296 | LEON_Cpu_Restore_interrupt(_source, _previous, _cpu) |
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297 | |
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298 | /* |
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299 | * Each timer control register is organized as follows: |
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300 | * |
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301 | * D0 - Enable |
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302 | * 1 = enable counting |
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303 | * 0 = hold scaler and counter |
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304 | * |
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305 | * D1 - Counter Reload |
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306 | * 1 = reload counter at zero and restart |
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307 | * 0 = stop counter at zero |
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308 | * |
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309 | * D2 - Counter Load |
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310 | * 1 = load counter with preset value |
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311 | * 0 = no function |
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312 | * |
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313 | */ |
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314 | |
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315 | #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 |
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316 | #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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317 | |
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318 | #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 |
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319 | |
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320 | #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 |
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321 | #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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322 | |
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323 | #define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 |
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324 | #define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 |
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325 | |
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326 | #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 |
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327 | #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 |
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328 | |
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329 | #if defined(RTEMS_MULTIPROCESSING) |
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330 | #define LEON3_CLOCK_INDEX \ |
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331 | (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) |
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332 | #else |
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333 | #define LEON3_CLOCK_INDEX 0 |
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334 | #endif |
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335 | |
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336 | /* |
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337 | * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to |
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338 | * run with 1MHz. This is used to determine all clock frequencies of the PnP |
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339 | * devices. See also ambapp_freq_init() and ambapp_freq_get(). |
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340 | */ |
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341 | #define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 |
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342 | |
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343 | /* Load 32-bit word by forcing a cache-miss */ |
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344 | static inline unsigned int leon_r32_no_cache(uintptr_t addr) |
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345 | { |
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346 | unsigned int tmp; |
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347 | __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); |
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348 | return tmp; |
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349 | } |
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350 | |
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351 | /* Let user override which on-chip APBUART will be debug UART |
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352 | * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... |
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353 | * 1 = APBUART[0] |
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354 | * 2 = APBUART[1] |
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355 | * 3 = APBUART[2] |
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356 | * ... |
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357 | */ |
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358 | extern int syscon_uart_index; |
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359 | |
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360 | /* Let user override which on-chip APBUART will be debug UART |
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361 | * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... |
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362 | * 1 = APBUART[0] |
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363 | * 2 = APBUART[1] |
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364 | * 3 = APBUART[2] |
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365 | * ... |
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366 | */ |
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367 | extern int debug_uart_index; |
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368 | |
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369 | /* Let user override which on-chip TIMER core will be used for system clock |
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370 | * timer. This controls which timer core will be accociated with |
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371 | * LEON3_Timer_Regs registers base address. This value will by destroyed during |
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372 | * initialization. |
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373 | * 0 = Default configuration. GPTIMER[0] |
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374 | * 1 = GPTIMER[1] |
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375 | * 2 = GPTIMER[2] |
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376 | * ... |
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377 | */ |
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378 | extern int leon3_timer_core_index; |
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379 | |
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380 | /* Let user override system clock timer prescaler. This affects all timer |
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381 | * instances on the system clock timer core determined by |
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382 | * leon3_timer_core_index. |
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383 | * 0 = Default configuration. Use bootloader configured value. |
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384 | * N = Prescaler is set to N. N must not be less that number of timers. |
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385 | * 8 = Prescaler is set to 8 (the fastest prescaler possible on all HW) |
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386 | * ... |
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387 | */ |
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388 | extern unsigned int leon3_timer_prescaler; |
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389 | |
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390 | /* GRLIB extended IRQ controller register */ |
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391 | void leon3_ext_irq_init(void); |
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392 | |
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393 | void leon3_power_down_loop(void) RTEMS_NO_RETURN; |
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394 | |
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395 | static inline uint32_t leon3_get_cpu_count( |
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396 | volatile struct irqmp_regs *irqmp |
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397 | ) |
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398 | { |
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399 | uint32_t mpstat = irqmp->mpstat; |
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400 | |
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401 | return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; |
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402 | } |
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403 | |
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404 | static inline void leon3_set_system_register(uint32_t addr, uint32_t val) |
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405 | { |
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406 | __asm__ volatile( |
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407 | "sta %1, [%0] 2" |
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408 | : |
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409 | : "r" (addr), "r" (val) |
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410 | ); |
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411 | } |
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412 | |
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413 | static inline uint32_t leon3_get_system_register(uint32_t addr) |
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414 | { |
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415 | uint32_t val; |
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416 | |
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417 | __asm__ volatile( |
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418 | "lda [%1] 2, %0" |
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419 | : "=r" (val) |
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420 | : "r" (addr) |
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421 | ); |
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422 | |
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423 | return val; |
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424 | } |
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425 | |
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426 | static inline void leon3_set_cache_control_register(uint32_t val) |
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427 | { |
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428 | leon3_set_system_register(0x0, val); |
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429 | } |
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430 | |
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431 | static inline uint32_t leon3_get_cache_control_register(void) |
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432 | { |
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433 | return leon3_get_system_register(0x0); |
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434 | } |
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435 | |
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436 | static inline bool leon3_data_cache_snooping_enabled(void) |
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437 | { |
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438 | return leon3_get_cache_control_register() & LEON3_REG_CACHE_CTRL_DS; |
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439 | } |
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440 | |
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441 | static inline uint32_t leon3_get_inst_cache_config_register(void) |
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442 | { |
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443 | return leon3_get_system_register(0x8); |
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444 | } |
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445 | |
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446 | static inline uint32_t leon3_get_data_cache_config_register(void) |
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447 | { |
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448 | return leon3_get_system_register(0xc); |
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449 | } |
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450 | |
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451 | static inline bool leon3_irqmp_has_timestamp( |
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452 | volatile struct irqmp_timestamp_regs *irqmp_ts |
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453 | ) |
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454 | { |
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455 | return (irqmp_ts->control >> 27) > 0; |
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456 | } |
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457 | |
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458 | static inline uint32_t leon3_up_counter_low(void) |
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459 | { |
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460 | uint32_t asr23; |
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461 | |
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462 | __asm__ volatile ( |
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463 | "mov %%asr23, %0" |
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464 | : "=&r" (asr23) |
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465 | ); |
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466 | |
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467 | return asr23; |
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468 | } |
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469 | |
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470 | static inline uint32_t leon3_up_counter_high(void) |
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471 | { |
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472 | uint32_t asr22; |
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473 | |
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474 | __asm__ volatile ( |
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475 | "mov %%asr22, %0" |
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476 | : "=&r" (asr22) |
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477 | ); |
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478 | |
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479 | return asr22; |
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480 | } |
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481 | |
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482 | static inline void leon3_up_counter_enable(void) |
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483 | { |
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484 | __asm__ volatile ( |
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485 | "mov %g0, %asr23" |
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486 | ); |
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487 | } |
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488 | |
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489 | static inline bool leon3_up_counter_is_available(void) |
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490 | { |
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491 | return leon3_up_counter_low() != leon3_up_counter_low(); |
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492 | } |
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493 | |
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494 | static inline uint32_t leon3_up_counter_frequency(void) |
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495 | { |
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496 | /* |
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497 | * For simplicity, assume that the interrupt controller uses the processor |
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498 | * clock. This is at least true on the GR740. |
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499 | */ |
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500 | return ambapp_freq_get(&ambapp_plb, LEON3_IrqCtrl_Adev); |
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501 | } |
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502 | |
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503 | #endif /* !ASM */ |
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504 | |
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505 | #ifdef __cplusplus |
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506 | } |
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507 | #endif |
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508 | |
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509 | #endif /* !_INCLUDE_LEON_h */ |
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510 | /* end of include file */ |
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511 | |
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