source: rtems/c/src/lib/libbsp/sparc/leon3/include/leon.h @ 1982a19

4.104.114.84.95
Last change on this file since 1982a19 was 1982a19, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 6, 2007 at 12:01:30 AM

2007-09-05 Daniel Hellstrom <daniel@…>

  • Makefile.am, preinstall.am, amba/amba.c, include/amba.h, include/leon.h: LEON3 AMBA PnP bus scanning moved to shared/amba/amba.c and shared/include/ambapp.h. The AMBA scanning was improved to take account for PnP info address translation. This is useful when scanning remote AMBA busses for example when a board connected with PCI has an AMBA bus that needs to be scanned, before the addresses was hard coded. Also, LEON2 now have AMBA PnP bus scanning support. By using the new AMBA scanning routines it is possible to isolate the AMBA scanning code to ambapp.c, however existing drivers should be updated to use them in order to save space.
  • Property mode set to 100644
File size: 9.9 KB
Line 
1/*  leon.h
2 *
3 *  LEON3 BSP data types and macros.
4 *
5 *  COPYRIGHT (c) 1989-1998.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  Modified for LEON3 BSP.
9 *  COPYRIGHT (c) 2004.
10 *  Gaisler Research.
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18 
19#ifndef _INCLUDE_LEON_h
20#define _INCLUDE_LEON_h
21
22#include <rtems/score/sparc.h>
23#include <amba.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#define LEON_INTERRUPT_EXTERNAL_1 5
30
31#ifndef ASM
32/*
33 *  Trap Types for on-chip peripherals
34 *
35 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
36 *
37 *  NOTE: The priority level for each source corresponds to the least
38 *        significant nibble of the trap type.
39 */
40
41#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
42
43#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
44
45#define LEON_INT_TRAP( _trap ) \
46  ( (_trap) >= 0x11 && \
47    (_trap) <= 0x1F )
48   
49/*
50 *  Structure for LEON memory mapped registers. 
51 *
52 *  Source: Section 6.1 - On-chip registers
53 *
54 *  NOTE:  There is only one of these structures per CPU, its base address
55 *         is 0x80000000, and the variable LEON_REG is placed there by the
56 *         linkcmds file.
57 */
58
59/* Leon uses dynamic register mapping using amba configuration records,
60 * LEON_Register_Map is obsolete
61 */
62/*
63  typedef struct {
64        volatile unsigned int Memory_Config_1;
65        volatile unsigned int Memory_Config_2;
66        volatile unsigned int Edac_Control;
67        volatile unsigned int Failed_Address;
68        volatile unsigned int Memory_Status;
69        volatile unsigned int Cache_Control;
70        volatile unsigned int Power_Down;
71        volatile unsigned int Write_Protection_1;
72        volatile unsigned int Write_Protection_2;
73        volatile unsigned int Leon_Configuration;
74        volatile unsigned int dummy2;
75        volatile unsigned int dummy3;
76        volatile unsigned int dummy4;   
77        volatile unsigned int dummy5;
78        volatile unsigned int dummy6;
79        volatile unsigned int dummy7;
80        volatile unsigned int Timer_Counter_1;
81        volatile unsigned int Timer_Reload_1;
82        volatile unsigned int Timer_Control_1;
83        volatile unsigned int Watchdog;
84        volatile unsigned int Timer_Counter_2;
85        volatile unsigned int Timer_Reload_2;
86        volatile unsigned int Timer_Control_2;
87        volatile unsigned int dummy8;
88        volatile unsigned int Scaler_Counter;
89        volatile unsigned int Scaler_Reload;
90        volatile unsigned int dummy9;
91        volatile unsigned int dummy10;
92        volatile unsigned int UART_Channel_1;
93        volatile unsigned int UART_Status_1;
94        volatile unsigned int UART_Control_1;
95        volatile unsigned int UART_Scaler_1;
96        volatile unsigned int UART_Channel_2;
97        volatile unsigned int UART_Status_2;
98        volatile unsigned int UART_Control_2;
99        volatile unsigned int UART_Scaler_2;
100        volatile unsigned int Interrupt_Mask;
101        volatile unsigned int Interrupt_Pending;
102        volatile unsigned int Interrupt_Force;
103        volatile unsigned int Interrupt_Clear;
104        volatile unsigned int PIO_Data;
105        volatile unsigned int PIO_Direction;
106        volatile unsigned int PIO_Interrupt;
107} LEON_Register_Map;
108*/
109
110typedef struct {
111  volatile unsigned int data;
112  volatile unsigned int status;
113  volatile unsigned int ctrl;
114} LEON3_UART_Regs_Map;
115
116typedef struct {
117  volatile unsigned int value;
118  volatile unsigned int reload;
119  volatile unsigned int conf;
120  volatile unsigned int notused;
121} LEON3_Timer_SubType;
122
123typedef struct {
124  volatile unsigned int scaler_value;   /* common timer registers */
125  volatile unsigned int scaler_reload;
126  volatile unsigned int status;
127  volatile unsigned int notused;
128  LEON3_Timer_SubType timer[8];
129} LEON3_Timer_Regs_Map;
130
131typedef struct {
132  volatile unsigned int iodata;
133  volatile unsigned int ioout;
134  volatile unsigned int iodir;
135  volatile unsigned int irqmask;
136  volatile unsigned int irqpol;
137  volatile unsigned int irqedge;
138} LEON3_IOPORT_Regs_Map;
139
140/* /\* */
141/*  *  This is used to manipulate the on-chip registers. */
142/*  * */
143/*  *  The following symbol must be defined in the linkcmds file and point */
144/*  *  to the correct location. */
145/*  *\/ */
146/* Leon uses dynamic register mapping using amba configuration records */
147/* LEON_Register_Map is obsolete */
148/* extern LEON_Register_Map LEON_REG; */
149 
150#endif
151
152/*
153 *  The following defines the bits in Memory Configuration Register 1.
154 */
155
156#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x0003C000
157
158/*
159 *  The following defines the bits in Memory Configuration Register 1.
160 */
161
162#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
163
164 
165/*
166 *  The following defines the bits in the Timer Control Register.
167 */
168
169#define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
170                                                 /* 0 = hold scalar and counter */
171#define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
172                                                 /* 0 = stop at 0 */
173#define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
174                                                 /* 0 = no function */
175
176/*
177 *  The following defines the bits in the UART Control Registers.
178 *
179 */
180
181#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
182 
183/*
184 *  The following defines the bits in the LEON UART Status Registers.
185 */
186
187#define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
188#define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
189#define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
190#define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
191#define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
192#define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
193#define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
194#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
195
196 
197/*
198 *  The following defines the bits in the LEON UART Status Registers.
199 */
200
201#define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
202#define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
203#define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
204#define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
205#define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
206#define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
207#define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
208#define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
209
210extern volatile LEON3_IrqCtrl_Regs_Map *LEON3_IrqCtrl_Regs;  /* LEON3 Interrupt Controller */
211extern volatile LEON3_Timer_Regs_Map *LEON3_Timer_Regs; /* LEON3 GP Timer */
212extern volatile LEON3_UART_Regs_Map *LEON3_Console_Uart[LEON3_APBUARTS];
213
214extern int LEON3_Cpu_Index;
215
216/* Macros used for manipulating bits in LEON3 GP Timer Control Register */
217
218#define LEON3_GPTIMER_EN 1
219#define LEON3_GPTIMER_RL 2
220#define LEON3_GPTIMER_LD 4
221#define LEON3_GPTIMER_IRQEN 8
222
223#define LEON3_MP_IRQ    14        /* Irq used by shared memory driver */
224
225#ifndef ASM
226
227/*
228 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
229 *  and the Interrupt Pending Registers.
230 *
231 *  NOTE: For operations which are not atomic, this code disables interrupts
232 *        to guarantee there are no intervening accesses to the same register.
233 *        The operations which read the register, modify the value and then
234 *        store the result back are vulnerable.
235 */
236
237#define LEON_Clear_interrupt( _source ) \
238  do { \
239    LEON3_IrqCtrl_Regs->iclear = (1 << (_source)); \
240  } while (0)
241
242#define LEON_Force_interrupt( _source ) \
243  do { \
244    LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \
245  } while (0)
246 
247#define LEON_Is_interrupt_pending( _source ) \
248  (LEON3_IrqCtrl_Regs.ipend & (1 << (_source)))
249 
250#define LEON_Is_interrupt_masked( _source ) \
251  do {\
252     (LEON3_IrqCtrl_Regs.mask[LEON3_Cpu_Index] & (1 << (_source))); \
253   } while (0)
254
255 
256#define LEON_Mask_interrupt( _source ) \
257  do { \
258    uint32_t _level; \
259    _level = sparc_disable_interrupts(); \
260     LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index]  &= ~(1 << (_source)); \
261    sparc_enable_interrupts( _level ); \
262  } while (0)
263 
264#define LEON_Unmask_interrupt( _source ) \
265  do { \
266    uint32_t _level; \
267    _level = sparc_disable_interrupts(); \
268    LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index]  |= (1 << (_source)); \
269    sparc_enable_interrupts( _level ); \
270  } while (0)
271
272#define LEON_Disable_interrupt( _source, _previous ) \
273  do { \
274    uint32_t _level; \
275    uint32_t _mask = 1 << (_source); \
276    _level = sparc_disable_interrupts(); \
277     (_previous) = LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index]; \
278     LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = _previous & ~_mask; \
279    sparc_enable_interrupts( _level ); \
280    (_previous) &= _mask; \
281  } while (0)
282 
283#define LEON_Restore_interrupt( _source, _previous ) \
284  do { \
285    uint32_t _level; \
286    uint32_t _mask = 1 << (_source); \
287    _level = sparc_disable_interrupts(); \
288      LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = \
289        (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & ~_mask) | (_previous); \
290    sparc_enable_interrupts( _level ); \
291  } while (0)
292
293
294/*
295 *  Each timer control register is organized as follows:
296 *
297 *    D0 - Enable
298 *          1 = enable counting
299 *          0 = hold scaler and counter
300 *
301 *    D1 - Counter Reload
302 *          1 = reload counter at zero and restart
303 *          0 = stop counter at zero
304 *
305 *    D2 - Counter Load
306 *          1 = load counter with preset value
307 *          0 = no function
308 *
309 */
310
311#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000002
312#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
313
314#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER       0x00000004
315
316#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING    0x00000001
317#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
318
319#define LEON_REG_TIMER_COUNTER_RELOAD_MASK        0x00000002
320#define LEON_REG_TIMER_COUNTER_ENABLE_MASK        0x00000001
321
322#define LEON_REG_TIMER_COUNTER_DEFINED_MASK       0x00000003
323#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000003
324
325#endif /* !ASM */
326
327#ifdef __cplusplus
328}
329#endif
330
331#endif /* !_INCLUDE_LEON_h */
332/* end of include file */
333
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