[df217b0b] | 1 | /** |
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| 2 | * @file |
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| 3 | * @ingroup sparc_leon3 |
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| 4 | * @brief LEON3 BSP data types and macros |
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| 5 | */ |
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| 6 | |
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[41c9282] | 7 | /* leon.h |
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| 8 | * |
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| 9 | * LEON3 BSP data types and macros. |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1989-1998. |
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| 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * Modified for LEON3 BSP. |
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| 15 | * COPYRIGHT (c) 2004. |
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| 16 | * Gaisler Research. |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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[44b06ca] | 22 | |
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[41c9282] | 23 | #ifndef _INCLUDE_LEON_h |
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| 24 | #define _INCLUDE_LEON_h |
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| 25 | |
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| 26 | #include <rtems/score/sparc.h> |
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| 27 | #include <amba.h> |
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| 28 | |
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| 29 | #ifdef __cplusplus |
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| 30 | extern "C" { |
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| 31 | #endif |
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| 32 | |
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[0b83afe9] | 33 | #define LEON_INTERRUPT_EXTERNAL_1 5 |
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[cd0142d5] | 34 | |
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[41c9282] | 35 | #ifndef ASM |
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| 36 | /* |
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| 37 | * Trap Types for on-chip peripherals |
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| 38 | * |
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| 39 | * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments |
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| 40 | * |
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[44b06ca] | 41 | * NOTE: The priority level for each source corresponds to the least |
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[41c9282] | 42 | * significant nibble of the trap type. |
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| 43 | */ |
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| 44 | |
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| 45 | #define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) |
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| 46 | |
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| 47 | #define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) |
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| 48 | |
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| 49 | #define LEON_INT_TRAP( _trap ) \ |
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| 50 | ( (_trap) >= 0x11 && \ |
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| 51 | (_trap) <= 0x1F ) |
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[44b06ca] | 52 | |
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[41c9282] | 53 | /* /\* */ |
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| 54 | /* * This is used to manipulate the on-chip registers. */ |
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| 55 | /* * */ |
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| 56 | /* * The following symbol must be defined in the linkcmds file and point */ |
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| 57 | /* * to the correct location. */ |
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| 58 | /* *\/ */ |
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| 59 | /* Leon uses dynamic register mapping using amba configuration records */ |
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| 60 | /* LEON_Register_Map is obsolete */ |
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| 61 | /* extern LEON_Register_Map LEON_REG; */ |
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[44b06ca] | 62 | |
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[41c9282] | 63 | #endif |
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| 64 | |
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| 65 | /* |
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| 66 | * The following defines the bits in Memory Configuration Register 1. |
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| 67 | */ |
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| 68 | |
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| 69 | #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 |
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| 70 | |
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| 71 | /* |
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| 72 | * The following defines the bits in Memory Configuration Register 1. |
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| 73 | */ |
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| 74 | |
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| 75 | #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 |
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| 76 | |
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[44b06ca] | 77 | |
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[41c9282] | 78 | /* |
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| 79 | * The following defines the bits in the Timer Control Register. |
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| 80 | */ |
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| 81 | |
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| 82 | #define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ |
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| 83 | /* 0 = hold scalar and counter */ |
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| 84 | #define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ |
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| 85 | /* 0 = stop at 0 */ |
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| 86 | #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ |
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| 87 | /* 0 = no function */ |
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| 88 | |
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| 89 | /* |
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| 90 | * The following defines the bits in the UART Control Registers. |
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| 91 | * |
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| 92 | */ |
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| 93 | |
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[44b06ca] | 94 | #define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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| 95 | |
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[41c9282] | 96 | /* |
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| 97 | * The following defines the bits in the LEON UART Status Registers. |
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| 98 | */ |
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| 99 | |
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| 100 | #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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| 101 | #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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| 102 | #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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| 103 | #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ |
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| 104 | #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ |
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| 105 | #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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| 106 | #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ |
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| 107 | #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ |
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| 108 | |
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| 109 | /* |
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| 110 | * The following defines the bits in the LEON UART Status Registers. |
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| 111 | */ |
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| 112 | |
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| 113 | #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ |
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| 114 | #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ |
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| 115 | #define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ |
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| 116 | #define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ |
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| 117 | #define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ |
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| 118 | #define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ |
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| 119 | #define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ |
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| 120 | #define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ |
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| 121 | |
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[226d48d8] | 122 | extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; /* LEON3 Interrupt Controller */ |
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| 123 | extern volatile struct gptimer_regs *LEON3_Timer_Regs; /* LEON3 GP Timer */ |
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[41c9282] | 124 | |
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[2cee553] | 125 | /* LEON3 CPU Index of boot CPU */ |
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[9956f81d] | 126 | extern int LEON3_Cpu_Index; |
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| 127 | |
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[95518e59] | 128 | /* The external IRQ number, -1 if not external interrupts */ |
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| 129 | extern int LEON3_IrqCtrl_EIrq; |
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| 130 | |
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| 131 | static __inline__ int bsp_irq_fixup(int irq) |
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| 132 | { |
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| 133 | int eirq; |
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| 134 | |
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| 135 | if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { |
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| 136 | /* Get interrupt number from IRQ controller */ |
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| 137 | eirq = LEON3_IrqCtrl_Regs->intid[LEON3_Cpu_Index] & 0x1f; |
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| 138 | if (eirq & 0x10) |
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| 139 | irq = eirq; |
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| 140 | } |
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| 141 | |
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| 142 | return irq; |
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| 143 | } |
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| 144 | |
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[41c9282] | 145 | /* Macros used for manipulating bits in LEON3 GP Timer Control Register */ |
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| 146 | |
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| 147 | #define LEON3_GPTIMER_EN 1 |
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| 148 | #define LEON3_GPTIMER_RL 2 |
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| 149 | #define LEON3_GPTIMER_LD 4 |
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| 150 | #define LEON3_GPTIMER_IRQEN 8 |
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| 151 | |
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[9956f81d] | 152 | #define LEON3_MP_IRQ 14 /* Irq used by shared memory driver */ |
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| 153 | |
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[fdcd80e] | 154 | #define LEON3_IRQMPSTATUS_CPUNR 28 |
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| 155 | #define LEON3_IRQMPSTATUS_BROADCAST 27 |
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| 156 | |
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| 157 | |
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[41c9282] | 158 | #ifndef ASM |
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| 159 | |
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| 160 | /* |
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| 161 | * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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| 162 | * and the Interrupt Pending Registers. |
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| 163 | * |
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| 164 | * NOTE: For operations which are not atomic, this code disables interrupts |
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| 165 | * to guarantee there are no intervening accesses to the same register. |
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| 166 | * The operations which read the register, modify the value and then |
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| 167 | * store the result back are vulnerable. |
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| 168 | */ |
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| 169 | |
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| 170 | #define LEON_Clear_interrupt( _source ) \ |
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| 171 | do { \ |
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| 172 | LEON3_IrqCtrl_Regs->iclear = (1 << (_source)); \ |
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| 173 | } while (0) |
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| 174 | |
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| 175 | #define LEON_Force_interrupt( _source ) \ |
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| 176 | do { \ |
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| 177 | LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \ |
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| 178 | } while (0) |
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[44b06ca] | 179 | |
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[41c9282] | 180 | #define LEON_Is_interrupt_pending( _source ) \ |
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[b3559ee9] | 181 | (LEON3_IrqCtrl_Regs->ipend & (1 << (_source))) |
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[44b06ca] | 182 | |
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[41c9282] | 183 | #define LEON_Is_interrupt_masked( _source ) \ |
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[0b83afe9] | 184 | do {\ |
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[b3559ee9] | 185 | (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & (1 << (_source))); \ |
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[0b83afe9] | 186 | } while (0) |
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| 187 | |
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[41c9282] | 188 | #define LEON_Mask_interrupt( _source ) \ |
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| 189 | do { \ |
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| 190 | uint32_t _level; \ |
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| 191 | _level = sparc_disable_interrupts(); \ |
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[0b83afe9] | 192 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] &= ~(1 << (_source)); \ |
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[41c9282] | 193 | sparc_enable_interrupts( _level ); \ |
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| 194 | } while (0) |
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[44b06ca] | 195 | |
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[41c9282] | 196 | #define LEON_Unmask_interrupt( _source ) \ |
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| 197 | do { \ |
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| 198 | uint32_t _level; \ |
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| 199 | _level = sparc_disable_interrupts(); \ |
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[0b83afe9] | 200 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] |= (1 << (_source)); \ |
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[41c9282] | 201 | sparc_enable_interrupts( _level ); \ |
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| 202 | } while (0) |
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| 203 | |
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| 204 | #define LEON_Disable_interrupt( _source, _previous ) \ |
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| 205 | do { \ |
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| 206 | uint32_t _level; \ |
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| 207 | uint32_t _mask = 1 << (_source); \ |
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| 208 | _level = sparc_disable_interrupts(); \ |
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[0b83afe9] | 209 | (_previous) = LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index]; \ |
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| 210 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = _previous & ~_mask; \ |
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[41c9282] | 211 | sparc_enable_interrupts( _level ); \ |
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| 212 | (_previous) &= _mask; \ |
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| 213 | } while (0) |
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[44b06ca] | 214 | |
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[41c9282] | 215 | #define LEON_Restore_interrupt( _source, _previous ) \ |
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| 216 | do { \ |
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| 217 | uint32_t _level; \ |
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| 218 | uint32_t _mask = 1 << (_source); \ |
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| 219 | _level = sparc_disable_interrupts(); \ |
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[0b83afe9] | 220 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = \ |
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| 221 | (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & ~_mask) | (_previous); \ |
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[41c9282] | 222 | sparc_enable_interrupts( _level ); \ |
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| 223 | } while (0) |
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| 224 | |
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[95518e59] | 225 | /* Make all SPARC BSPs have common macros for interrupt handling */ |
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| 226 | #define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) |
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| 227 | #define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) |
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| 228 | #define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) |
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| 229 | #define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) |
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| 230 | #define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) |
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| 231 | #define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) |
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| 232 | #define BSP_Disable_interrupt(_source, _previous) \ |
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| 233 | LEON_Disable_interrupt(_source, _prev) |
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| 234 | #define BSP_Restore_interrupt(_source, _previous) \ |
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| 235 | LEON_Restore_interrupt(_source, _previous) |
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[0b83afe9] | 236 | |
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[41c9282] | 237 | /* |
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| 238 | * Each timer control register is organized as follows: |
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| 239 | * |
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| 240 | * D0 - Enable |
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| 241 | * 1 = enable counting |
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| 242 | * 0 = hold scaler and counter |
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| 243 | * |
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| 244 | * D1 - Counter Reload |
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| 245 | * 1 = reload counter at zero and restart |
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| 246 | * 0 = stop counter at zero |
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| 247 | * |
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| 248 | * D2 - Counter Load |
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[44b06ca] | 249 | * 1 = load counter with preset value |
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[41c9282] | 250 | * 0 = no function |
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| 251 | * |
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| 252 | */ |
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| 253 | |
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| 254 | #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 |
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| 255 | #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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| 256 | |
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| 257 | #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 |
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| 258 | |
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| 259 | #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 |
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| 260 | #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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| 261 | |
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| 262 | #define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 |
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| 263 | #define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 |
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| 264 | |
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| 265 | #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 |
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| 266 | #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 |
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| 267 | |
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[39671330] | 268 | /* Load 32-bit word by forcing a cache-miss */ |
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| 269 | static inline unsigned int leon_r32_no_cache(uintptr_t addr) |
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| 270 | { |
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| 271 | unsigned int tmp; |
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| 272 | asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); |
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| 273 | return tmp; |
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| 274 | } |
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| 275 | |
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[41c9282] | 276 | #endif /* !ASM */ |
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| 277 | |
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| 278 | #ifdef __cplusplus |
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| 279 | } |
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| 280 | #endif |
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| 281 | |
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| 282 | #endif /* !_INCLUDE_LEON_h */ |
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[0b83afe9] | 283 | /* end of include file */ |
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[41c9282] | 284 | |
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