[df217b0b] | 1 | /** |
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| 2 | * @file |
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| 3 | * @ingroup sparc_leon3 |
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| 4 | * @brief LEON3 BSP data types and macros |
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| 5 | */ |
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| 6 | |
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[41c9282] | 7 | /* leon.h |
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| 8 | * |
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| 9 | * LEON3 BSP data types and macros. |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1989-1998. |
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| 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * Modified for LEON3 BSP. |
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| 15 | * COPYRIGHT (c) 2004. |
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| 16 | * Gaisler Research. |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[41c9282] | 21 | */ |
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[44b06ca] | 22 | |
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[41c9282] | 23 | #ifndef _INCLUDE_LEON_h |
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| 24 | #define _INCLUDE_LEON_h |
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| 25 | |
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[2cb0877] | 26 | #include <rtems.h> |
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[41c9282] | 27 | #include <amba.h> |
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| 28 | |
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| 29 | #ifdef __cplusplus |
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| 30 | extern "C" { |
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| 31 | #endif |
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| 32 | |
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[0b83afe9] | 33 | #define LEON_INTERRUPT_EXTERNAL_1 5 |
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[cd0142d5] | 34 | |
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[41c9282] | 35 | #ifndef ASM |
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| 36 | /* |
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| 37 | * Trap Types for on-chip peripherals |
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| 38 | * |
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| 39 | * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments |
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| 40 | * |
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[44b06ca] | 41 | * NOTE: The priority level for each source corresponds to the least |
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[41c9282] | 42 | * significant nibble of the trap type. |
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| 43 | */ |
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| 44 | |
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| 45 | #define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) |
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| 46 | |
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| 47 | #define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) |
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| 48 | |
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| 49 | #define LEON_INT_TRAP( _trap ) \ |
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| 50 | ( (_trap) >= 0x11 && \ |
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| 51 | (_trap) <= 0x1F ) |
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[44b06ca] | 52 | |
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[41c9282] | 53 | /* /\* */ |
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| 54 | /* * This is used to manipulate the on-chip registers. */ |
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| 55 | /* * */ |
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| 56 | /* * The following symbol must be defined in the linkcmds file and point */ |
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| 57 | /* * to the correct location. */ |
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| 58 | /* *\/ */ |
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| 59 | /* Leon uses dynamic register mapping using amba configuration records */ |
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| 60 | /* LEON_Register_Map is obsolete */ |
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| 61 | /* extern LEON_Register_Map LEON_REG; */ |
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[44b06ca] | 62 | |
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[41c9282] | 63 | #endif |
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| 64 | |
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| 65 | /* |
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| 66 | * The following defines the bits in Memory Configuration Register 1. |
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| 67 | */ |
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| 68 | |
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| 69 | #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 |
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| 70 | |
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| 71 | /* |
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| 72 | * The following defines the bits in Memory Configuration Register 1. |
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| 73 | */ |
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| 74 | |
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| 75 | #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 |
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| 76 | |
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[44b06ca] | 77 | |
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[41c9282] | 78 | /* |
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| 79 | * The following defines the bits in the Timer Control Register. |
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| 80 | */ |
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| 81 | |
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| 82 | #define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ |
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[363b1f7] | 83 | /* 0 = hold scalar and counter */ |
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[41c9282] | 84 | #define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ |
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[363b1f7] | 85 | /* 0 = stop at 0 */ |
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[41c9282] | 86 | #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ |
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[363b1f7] | 87 | /* 0 = no function */ |
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[41c9282] | 88 | |
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[62f373fb] | 89 | /* |
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| 90 | * The following defines the bits in the LEON Cache Control Register. |
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| 91 | */ |
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| 92 | #define LEON3_REG_CACHE_CTRL_FI 0x00200000 /* Flush instruction cache */ |
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| 93 | |
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[363b1f7] | 94 | /* LEON3 Interrupt Controller */ |
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| 95 | extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs; |
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| 96 | /* LEON3 GP Timer */ |
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| 97 | extern volatile struct gptimer_regs *LEON3_Timer_Regs; |
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[41c9282] | 98 | |
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[2cee553] | 99 | /* LEON3 CPU Index of boot CPU */ |
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[ad56361] | 100 | extern uint32_t LEON3_Cpu_Index; |
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[9956f81d] | 101 | |
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[95518e59] | 102 | /* The external IRQ number, -1 if not external interrupts */ |
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| 103 | extern int LEON3_IrqCtrl_EIrq; |
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| 104 | |
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| 105 | static __inline__ int bsp_irq_fixup(int irq) |
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| 106 | { |
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[70eff78] | 107 | int eirq, cpu; |
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[95518e59] | 108 | |
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[70eff78] | 109 | if (LEON3_IrqCtrl_EIrq != 0 && irq == LEON3_IrqCtrl_EIrq) { |
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| 110 | /* Get interrupt number from IRQ controller */ |
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| 111 | cpu = _LEON3_Get_current_processor(); |
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| 112 | eirq = LEON3_IrqCtrl_Regs->intid[cpu] & 0x1f; |
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| 113 | if (eirq & 0x10) |
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| 114 | irq = eirq; |
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| 115 | } |
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[95518e59] | 116 | |
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[70eff78] | 117 | return irq; |
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[95518e59] | 118 | } |
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| 119 | |
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[41c9282] | 120 | /* Macros used for manipulating bits in LEON3 GP Timer Control Register */ |
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| 121 | |
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[fdcd80e] | 122 | #define LEON3_IRQMPSTATUS_CPUNR 28 |
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| 123 | #define LEON3_IRQMPSTATUS_BROADCAST 27 |
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| 124 | |
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| 125 | |
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[41c9282] | 126 | #ifndef ASM |
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| 127 | |
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| 128 | /* |
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| 129 | * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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| 130 | * and the Interrupt Pending Registers. |
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| 131 | * |
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| 132 | * NOTE: For operations which are not atomic, this code disables interrupts |
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| 133 | * to guarantee there are no intervening accesses to the same register. |
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| 134 | * The operations which read the register, modify the value and then |
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| 135 | * store the result back are vulnerable. |
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| 136 | */ |
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| 137 | |
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[2cb0877] | 138 | extern rtems_interrupt_lock LEON3_IrqCtrl_Lock; |
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| 139 | |
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[d50acdbb] | 140 | #define LEON3_IRQCTRL_ACQUIRE( _lock_context ) \ |
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| 141 | rtems_interrupt_lock_acquire( &LEON3_IrqCtrl_Lock, _lock_context ) |
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[2cb0877] | 142 | |
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[d50acdbb] | 143 | #define LEON3_IRQCTRL_RELEASE( _lock_context ) \ |
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| 144 | rtems_interrupt_lock_release( &LEON3_IrqCtrl_Lock, _lock_context ) |
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[2cb0877] | 145 | |
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[41c9282] | 146 | #define LEON_Clear_interrupt( _source ) \ |
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| 147 | do { \ |
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| 148 | LEON3_IrqCtrl_Regs->iclear = (1 << (_source)); \ |
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| 149 | } while (0) |
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| 150 | |
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| 151 | #define LEON_Force_interrupt( _source ) \ |
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| 152 | do { \ |
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| 153 | LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \ |
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| 154 | } while (0) |
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[44b06ca] | 155 | |
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[41c9282] | 156 | #define LEON_Is_interrupt_pending( _source ) \ |
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[b3559ee9] | 157 | (LEON3_IrqCtrl_Regs->ipend & (1 << (_source))) |
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[44b06ca] | 158 | |
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[41c9282] | 159 | #define LEON_Is_interrupt_masked( _source ) \ |
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[0b83afe9] | 160 | do {\ |
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[b3559ee9] | 161 | (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & (1 << (_source))); \ |
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[0b83afe9] | 162 | } while (0) |
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| 163 | |
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[41c9282] | 164 | #define LEON_Mask_interrupt( _source ) \ |
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| 165 | do { \ |
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[d50acdbb] | 166 | rtems_interrupt_lock_context _lock_context; \ |
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| 167 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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[0b83afe9] | 168 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] &= ~(1 << (_source)); \ |
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[d50acdbb] | 169 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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[41c9282] | 170 | } while (0) |
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[44b06ca] | 171 | |
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[41c9282] | 172 | #define LEON_Unmask_interrupt( _source ) \ |
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| 173 | do { \ |
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[d50acdbb] | 174 | rtems_interrupt_lock_context _lock_context; \ |
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| 175 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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[0b83afe9] | 176 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] |= (1 << (_source)); \ |
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[d50acdbb] | 177 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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[41c9282] | 178 | } while (0) |
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| 179 | |
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| 180 | #define LEON_Disable_interrupt( _source, _previous ) \ |
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| 181 | do { \ |
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[d50acdbb] | 182 | rtems_interrupt_lock_context _lock_context; \ |
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[41c9282] | 183 | uint32_t _mask = 1 << (_source); \ |
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[d50acdbb] | 184 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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[0b83afe9] | 185 | (_previous) = LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index]; \ |
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| 186 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = _previous & ~_mask; \ |
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[d50acdbb] | 187 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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[41c9282] | 188 | (_previous) &= _mask; \ |
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| 189 | } while (0) |
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[44b06ca] | 190 | |
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[41c9282] | 191 | #define LEON_Restore_interrupt( _source, _previous ) \ |
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| 192 | do { \ |
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[d50acdbb] | 193 | rtems_interrupt_lock_context _lock_context; \ |
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[41c9282] | 194 | uint32_t _mask = 1 << (_source); \ |
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[d50acdbb] | 195 | LEON3_IRQCTRL_ACQUIRE( &_lock_context ); \ |
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[0b83afe9] | 196 | LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] = \ |
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| 197 | (LEON3_IrqCtrl_Regs->mask[LEON3_Cpu_Index] & ~_mask) | (_previous); \ |
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[d50acdbb] | 198 | LEON3_IRQCTRL_RELEASE( &_lock_context ); \ |
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[41c9282] | 199 | } while (0) |
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| 200 | |
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[95518e59] | 201 | /* Make all SPARC BSPs have common macros for interrupt handling */ |
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| 202 | #define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) |
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| 203 | #define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) |
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| 204 | #define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) |
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| 205 | #define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) |
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| 206 | #define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) |
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| 207 | #define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) |
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| 208 | #define BSP_Disable_interrupt(_source, _previous) \ |
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| 209 | LEON_Disable_interrupt(_source, _prev) |
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| 210 | #define BSP_Restore_interrupt(_source, _previous) \ |
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| 211 | LEON_Restore_interrupt(_source, _previous) |
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[0b83afe9] | 212 | |
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[41c9282] | 213 | /* |
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| 214 | * Each timer control register is organized as follows: |
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| 215 | * |
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| 216 | * D0 - Enable |
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| 217 | * 1 = enable counting |
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| 218 | * 0 = hold scaler and counter |
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| 219 | * |
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| 220 | * D1 - Counter Reload |
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| 221 | * 1 = reload counter at zero and restart |
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| 222 | * 0 = stop counter at zero |
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| 223 | * |
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| 224 | * D2 - Counter Load |
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[44b06ca] | 225 | * 1 = load counter with preset value |
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[41c9282] | 226 | * 0 = no function |
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| 227 | * |
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| 228 | */ |
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| 229 | |
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| 230 | #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 |
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| 231 | #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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| 232 | |
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| 233 | #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 |
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| 234 | |
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| 235 | #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 |
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| 236 | #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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| 237 | |
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| 238 | #define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 |
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| 239 | #define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 |
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| 240 | |
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| 241 | #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 |
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| 242 | #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 |
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| 243 | |
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[a4bc90af] | 244 | #if defined(RTEMS_MULTIPROCESSING) |
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| 245 | #define LEON3_CLOCK_INDEX \ |
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[363b1f7] | 246 | (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0) |
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[a4bc90af] | 247 | #else |
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| 248 | #define LEON3_CLOCK_INDEX 0 |
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| 249 | #endif |
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| 250 | |
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[0a2096b] | 251 | /* |
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| 252 | * We assume that a boot loader (usually GRMON) initialized the GPTIMER 0 to |
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| 253 | * run with 1MHz. This is used to determine all clock frequencies of the PnP |
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| 254 | * devices. See also ambapp_freq_init() and ambapp_freq_get(). |
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| 255 | */ |
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| 256 | #define LEON3_GPTIMER_0_FREQUENCY_SET_BY_BOOT_LOADER 1000000 |
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| 257 | |
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[39671330] | 258 | /* Load 32-bit word by forcing a cache-miss */ |
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| 259 | static inline unsigned int leon_r32_no_cache(uintptr_t addr) |
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| 260 | { |
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[9f058fb] | 261 | unsigned int tmp; |
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| 262 | __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr)); |
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| 263 | return tmp; |
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[39671330] | 264 | } |
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| 265 | |
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[1d5d6de] | 266 | /* Let user override which on-chip APBUART will be debug UART |
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| 267 | * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... |
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| 268 | * 1 = APBUART[0] |
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| 269 | * 2 = APBUART[1] |
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| 270 | * 3 = APBUART[2] |
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| 271 | * ... |
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| 272 | */ |
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| 273 | extern int syscon_uart_index; |
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| 274 | |
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| 275 | /* Let user override which on-chip APBUART will be debug UART |
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| 276 | * 0 = Default APBUART. On MP system CPU0=APBUART0, CPU1=APBUART1... |
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| 277 | * 1 = APBUART[0] |
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| 278 | * 2 = APBUART[1] |
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| 279 | * 3 = APBUART[2] |
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| 280 | * ... |
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| 281 | */ |
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| 282 | extern int debug_uart_index; |
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| 283 | |
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[24bf11e] | 284 | void leon3_cpu_counter_initialize(void); |
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| 285 | |
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[f71f3d31] | 286 | /* GRLIB extended IRQ controller register */ |
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| 287 | void leon3_ext_irq_init(void); |
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| 288 | |
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[224b888] | 289 | void bsp_debug_uart_init(void); |
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| 290 | |
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[4fe6759e] | 291 | void leon3_power_down_loop(void) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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| 292 | |
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[7ec8d95] | 293 | static inline uint32_t leon3_get_cpu_count( |
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| 294 | volatile struct irqmp_regs *irqmp |
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| 295 | ) |
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| 296 | { |
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| 297 | uint32_t mpstat = irqmp->mpstat; |
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| 298 | |
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| 299 | return ((mpstat >> LEON3_IRQMPSTATUS_CPUNR) & 0xf) + 1; |
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| 300 | } |
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| 301 | |
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[80186ca8] | 302 | static inline void leon3_set_system_register(uint32_t addr, uint32_t val) |
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| 303 | { |
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| 304 | __asm__ volatile( |
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| 305 | "sta %1, [%0] 2" |
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| 306 | : |
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| 307 | : "r" (addr), "r" (val) |
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| 308 | ); |
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| 309 | } |
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| 310 | |
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| 311 | static inline uint32_t leon3_get_system_register(uint32_t addr) |
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| 312 | { |
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| 313 | uint32_t val; |
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| 314 | |
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| 315 | __asm__ volatile( |
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| 316 | "lda [%1] 2, %0" |
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| 317 | : "=r" (val) |
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| 318 | : "r" (addr) |
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| 319 | ); |
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| 320 | |
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| 321 | return val; |
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| 322 | } |
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| 323 | |
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| 324 | static inline void leon3_set_cache_control_register(uint32_t val) |
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| 325 | { |
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| 326 | leon3_set_system_register(0x0, val); |
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| 327 | } |
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| 328 | |
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| 329 | static inline uint32_t leon3_get_cache_control_register(void) |
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| 330 | { |
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| 331 | return leon3_get_system_register(0x0); |
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| 332 | } |
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| 333 | |
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| 334 | static inline uint32_t leon3_get_inst_cache_config_register(void) |
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| 335 | { |
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| 336 | return leon3_get_system_register(0x8); |
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| 337 | } |
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| 338 | |
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| 339 | static inline uint32_t leon3_get_data_cache_config_register(void) |
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| 340 | { |
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| 341 | return leon3_get_system_register(0xc); |
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| 342 | } |
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| 343 | |
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[6b115b3] | 344 | static inline bool leon3_irqmp_has_timestamp( |
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| 345 | volatile struct irqmp_timestamp_regs *irqmp_ts |
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| 346 | ) |
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| 347 | { |
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| 348 | return (irqmp_ts->control >> 27) > 0; |
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| 349 | } |
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| 350 | |
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[41c9282] | 351 | #endif /* !ASM */ |
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| 352 | |
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| 353 | #ifdef __cplusplus |
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| 354 | } |
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| 355 | #endif |
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| 356 | |
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| 357 | #endif /* !_INCLUDE_LEON_h */ |
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[0b83afe9] | 358 | /* end of include file */ |
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[41c9282] | 359 | |
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