1 | /* |
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2 | * pci.c : this file contains basic PCI Io functions. |
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3 | * |
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4 | * Copyright (C) 1999 valette@crf.canon.fr |
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5 | * |
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6 | * This code is heavily inspired by the public specification of STREAM V2 |
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7 | * that can be found at : |
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8 | * |
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9 | * <http://www.chorus.com/Documentation/index.html> by following |
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10 | * the STREAM API Specification Document link. |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | * |
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16 | * Till Straumann, <strauman@slac.stanford.edu>, 1/2002 |
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17 | * - separated bridge detection code out of this file |
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18 | * |
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19 | * Adapted to LEON2 AT697 PCI |
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20 | * Copyright (C) 2006 Gaisler Research |
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21 | * |
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22 | */ |
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23 | |
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24 | #include <pci.h> |
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25 | #include <rtems/bspIo.h> |
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26 | #include <stdlib.h> |
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27 | |
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28 | /* Define PCI_INFO to get a listing of configured devices at boot time */ |
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29 | #define PCI_INFO 1 |
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30 | |
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31 | /* #define DEBUG 1 */ |
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32 | |
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33 | #ifdef DEBUG |
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34 | #define DBG(x...) printk(x) |
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35 | #else |
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36 | #define DBG(x...) |
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37 | #endif |
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38 | |
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39 | /* allow for overriding these definitions */ |
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40 | #ifndef PCI_CONFIG_ADDR |
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41 | #define PCI_CONFIG_ADDR 0xcf8 |
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42 | #endif |
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43 | #ifndef PCI_CONFIG_DATA |
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44 | #define PCI_CONFIG_DATA 0xcfc |
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45 | #endif |
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46 | |
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47 | #define PCI_INVALID_VENDORDEVICEID 0xffffffff |
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48 | #define PCI_MULTI_FUNCTION 0x80 |
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49 | |
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50 | /* define a shortcut */ |
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51 | #define pci BSP_pci_configuration |
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52 | |
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53 | /* |
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54 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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55 | */ |
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56 | unsigned char ucMaxPCIBus; |
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57 | |
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58 | typedef struct { |
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59 | volatile unsigned int pciid1; /* 0x80000100 - PCI Device identification register 1 */ |
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60 | volatile unsigned int pcisc; /* 0x80000104 - PCI Status & Command */ |
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61 | volatile unsigned int pciid2; /* 0x80000108 - PCI Device identification register 2 */ |
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62 | volatile unsigned int pcibhlc; /* 0x8000010c - BIST, Header type, Cache line size register */ |
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63 | volatile unsigned int mbar1; /* 0x80000110 - Memory Base Address Register 1 */ |
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64 | volatile unsigned int mbar2; /* 0x80000114 - Memory Base Address Register 2 */ |
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65 | volatile unsigned int iobar3; /* 0x80000118 - IO Base Address Register 3 */ |
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66 | volatile unsigned int dummy1[4]; /* 0x8000011c - 0x80000128 */ |
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67 | volatile unsigned int pcisid; /* 0x8000012c - Subsystem identification register */ |
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68 | volatile unsigned int dummy2; /* 0x80000130 */ |
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69 | volatile unsigned int pcicp; /* 0x80000134 - PCI capabilities pointer register */ |
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70 | volatile unsigned int dummy3; /* 0x80000138 */ |
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71 | volatile unsigned int pcili; /* 0x8000013c - PCI latency interrupt register */ |
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72 | volatile unsigned int pcirt; /* 0x80000140 - PCI retry, trdy config */ |
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73 | volatile unsigned int pcicw; /* 0x80000144 - PCI configuration write register */ |
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74 | volatile unsigned int pcisa; /* 0x80000148 - PCI Initiator Start Address */ |
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75 | volatile unsigned int pciiw; /* 0x8000014c - PCI Initiator Write Register */ |
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76 | volatile unsigned int pcidma; /* 0x80000150 - PCI DMA configuration register */ |
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77 | volatile unsigned int pciis; /* 0x80000154 - PCI Initiator Status Register */ |
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78 | volatile unsigned int pciic; /* 0x80000158 - PCI Initiator Configuration */ |
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79 | volatile unsigned int pcitpa; /* 0x8000015c - PCI Target Page Address Register */ |
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80 | volatile unsigned int pcitsc; /* 0x80000160 - PCI Target Status-Command Register */ |
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81 | volatile unsigned int pciite; /* 0x80000164 - PCI Interrupt Enable Register */ |
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82 | volatile unsigned int pciitp; /* 0x80000168 - PCI Interrupt Pending Register */ |
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83 | volatile unsigned int pciitf; /* 0x8000016c - PCI Interrupt Force Register */ |
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84 | volatile unsigned int pcid; /* 0x80000170 - PCI Data Register */ |
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85 | volatile unsigned int pcibe; /* 0x80000174 - PCI Burst End Register */ |
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86 | volatile unsigned int pcidmaa; /* 0x80000178 - PCI DMA Address Register */ |
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87 | } AT697_PCI_Map; |
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88 | |
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89 | AT697_PCI_Map *pcic = (AT697_PCI_Map *) 0x80000100; |
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90 | |
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91 | #define PCI_MEM_START 0xa0000000 |
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92 | #define PCI_MEM_END 0xf0000000 |
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93 | #define PCI_MEM_SIZE (PCI_MEM_START - PCI_MEM_END) |
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94 | |
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95 | |
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96 | struct pci_res { |
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97 | unsigned int size; |
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98 | unsigned char bar; |
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99 | unsigned char devfn; |
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100 | }; |
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101 | |
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102 | /* The configuration access functions uses the DMA functionality of the |
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103 | * AT697 pci controller to be able access all slots |
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104 | */ |
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105 | |
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106 | static int |
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107 | BSP_pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int *val) { |
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108 | |
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109 | volatile unsigned int data; |
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110 | |
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111 | if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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112 | |
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113 | pcic->pciitp = 0xff; /* clear interrupts */ |
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114 | |
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115 | pcic->pcisa = ( 1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f); |
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116 | pcic->pcidma = 0xa01; |
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117 | pcic->pcidmaa = (unsigned int) &data; |
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118 | |
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119 | while (pcic->pciitp == 0) |
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120 | ; |
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121 | |
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122 | pcic->pciitp = 0xff; /* clear interrupts */ |
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123 | |
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124 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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125 | pcic->pcisc |= 0x20000000; |
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126 | *val = 0xffffffff; |
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127 | } |
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128 | else |
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129 | *val = data; |
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130 | |
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131 | DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), *val); |
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132 | |
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133 | return PCIBIOS_SUCCESSFUL; |
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134 | } |
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135 | |
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136 | |
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137 | static int |
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138 | BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) { |
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139 | unsigned int v; |
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140 | |
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141 | if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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142 | |
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143 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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144 | *val = 0xffff & (v >> (8*(offset & 3))); |
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145 | |
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146 | return PCIBIOS_SUCCESSFUL; |
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147 | } |
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148 | |
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149 | |
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150 | static int |
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151 | BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) { |
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152 | unsigned int v; |
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153 | |
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154 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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155 | |
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156 | *val = 0xff & (v >> (8*(offset & 3))); |
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157 | |
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158 | return PCIBIOS_SUCCESSFUL; |
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159 | } |
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160 | |
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161 | |
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162 | static int |
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163 | BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int val) { |
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164 | |
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165 | if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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166 | |
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167 | pcic->pciitp = 0xff; /* clear interrupts */ |
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168 | |
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169 | pcic->pcisa = ( 1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f); |
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170 | pcic->pcidma = 0xb01; |
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171 | pcic->pcidmaa = (unsigned int) &val; |
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172 | |
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173 | while (pcic->pciitp == 0) |
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174 | ; |
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175 | |
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176 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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177 | pcic->pcisc |= 0x20000000; |
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178 | } |
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179 | |
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180 | pcic->pciitp = 0xff; /* clear interrupts */ |
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181 | |
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182 | /* DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), val); */ |
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183 | |
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184 | return PCIBIOS_SUCCESSFUL; |
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185 | } |
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186 | |
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187 | |
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188 | static int |
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189 | BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) { |
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190 | unsigned int v; |
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191 | |
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192 | if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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193 | |
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194 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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195 | |
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196 | v = (v & ~(0xffff << (8*(offset&3)))) | ((0xffff&val) << (8*(offset&3))); |
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197 | |
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198 | return pci_write_config_dword(bus, slot, function, offset&~3, v); |
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199 | } |
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200 | |
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201 | |
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202 | static int |
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203 | BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) { |
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204 | unsigned int v; |
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205 | |
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206 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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207 | |
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208 | v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3))); |
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209 | |
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210 | return pci_write_config_dword(bus, slot, function, offset&~3, v); |
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211 | } |
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212 | |
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213 | |
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214 | |
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215 | const pci_config_access_functions pci_access_functions = { |
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216 | BSP_pci_read_config_byte, |
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217 | BSP_pci_read_config_word, |
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218 | BSP_pci_read_config_dword, |
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219 | BSP_pci_write_config_byte, |
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220 | BSP_pci_write_config_word, |
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221 | BSP_pci_write_config_dword |
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222 | }; |
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223 | |
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224 | rtems_pci_config_t BSP_pci_configuration = { |
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225 | (volatile unsigned char*)PCI_CONFIG_ADDR, |
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226 | (volatile unsigned char*)PCI_CONFIG_DATA, |
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227 | &pci_access_functions |
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228 | }; |
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229 | |
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230 | |
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231 | void init_at697_pci(void) { |
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232 | |
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233 | /* Reset */ |
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234 | pcic->pciic = 0xffffffff; |
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235 | |
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236 | /* Map system RAM at pci address 0x40000000 and system SDRAM to pci address 0x60000000 */ |
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237 | pcic->mbar1 = 0x40000000; |
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238 | pcic->mbar2 = 0x60000000; |
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239 | pcic->pcitpa = 0x40006000; |
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240 | |
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241 | /* Enable PCI master and target memory command response */ |
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242 | pcic->pcisc |= 0x40 | 0x6; |
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243 | |
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244 | /* Set latency timer to 64 */ |
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245 | pcic->pcibhlc = 0x00004000; |
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246 | |
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247 | /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */ |
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248 | pcic->pciic = 0x41; |
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249 | |
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250 | pcic->pciite = 0xff; |
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251 | |
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252 | } |
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253 | |
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254 | /* May not pass a 1k boundary */ |
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255 | int dma_from_pci_1k(unsigned int addr, unsigned int paddr, unsigned char len) { |
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256 | |
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257 | int retval = 0; |
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258 | |
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259 | if (addr & 3) { |
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260 | return -1; |
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261 | } |
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262 | |
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263 | pcic->pciitp = 0xff; /* clear interrupts */ |
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264 | |
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265 | pcic->pcisa = paddr; |
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266 | pcic->pcidma = 0xc00 | len; |
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267 | pcic->pcidmaa = addr; |
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268 | |
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269 | while (pcic->pciitp == 0) |
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270 | ; |
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271 | |
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272 | if (pcic->pciitp & 0x7F) { |
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273 | retval = -1; |
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274 | } |
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275 | |
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276 | pcic->pciitp = 0xff; /* clear interrupts */ |
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277 | |
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278 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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279 | pcic->pcisc |= 0x20000000; |
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280 | retval = -1; |
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281 | } |
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282 | |
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283 | return retval; |
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284 | } |
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285 | |
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286 | /* May not pass a 1k boundary */ |
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287 | int dma_to_pci_1k(unsigned int addr, unsigned int paddr, unsigned char len) { |
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288 | |
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289 | int retval = 0; |
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290 | |
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291 | if (addr & 3) return -1; |
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292 | |
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293 | pcic->pciitp = 0xff; /* clear interrupts */ |
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294 | |
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295 | pcic->pcisa = paddr; |
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296 | pcic->pcidma = 0x700 | len; |
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297 | pcic->pcidmaa = addr; |
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298 | |
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299 | while (pcic->pciitp == 0) |
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300 | ; |
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301 | |
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302 | if (pcic->pciitp & 0x7F) retval = -1; |
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303 | |
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304 | pcic->pciitp = 0xff; /* clear interrupts */ |
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305 | |
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306 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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307 | pcic->pcisc |= 0x20000000; |
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308 | retval = -1; |
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309 | } |
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310 | |
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311 | return retval; |
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312 | } |
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313 | |
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314 | /* Transfer len number of words from addr to paddr */ |
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315 | int dma_to_pci(unsigned int addr, unsigned int paddr, unsigned int len) { |
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316 | |
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317 | int tmp_len; |
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318 | |
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319 | /* Align to 1k boundary */ |
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320 | tmp_len = ((addr + 1024) & 0xfffffc00) - addr; |
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321 | |
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322 | tmp_len = (tmp_len/4 < len) ? tmp_len : (len*4); |
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323 | |
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324 | if (dma_to_pci_1k(addr, paddr, tmp_len/4) < 0) |
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325 | return -1; |
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326 | |
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327 | addr += tmp_len; |
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328 | paddr += tmp_len; |
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329 | len -= tmp_len/4; |
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330 | |
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331 | /* Transfer all 1k blocks */ |
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332 | while (len >= 128) { |
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333 | |
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334 | if (dma_to_pci_1k(addr, paddr, 128) < 0) |
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335 | return -1; |
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336 | |
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337 | addr += 512; |
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338 | paddr += 512; |
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339 | len -= 128; |
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340 | |
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341 | } |
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342 | |
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343 | /* Transfer last words */ |
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344 | if (len) return dma_to_pci_1k(addr, paddr, len); |
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345 | |
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346 | return 0; |
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347 | } |
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348 | |
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349 | /* Transfer len number of words from paddr to addr */ |
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350 | int dma_from_pci(unsigned int addr, unsigned int paddr, unsigned int len) { |
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351 | |
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352 | int tmp_len; |
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353 | |
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354 | /* Align to 1k boundary */ |
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355 | tmp_len = ((addr + 1024) & 0xfffffc00) - addr; |
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356 | |
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357 | tmp_len = (tmp_len/4 < len) ? tmp_len : (len*4); |
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358 | |
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359 | if (dma_from_pci_1k(addr, paddr, tmp_len/4) < 0) |
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360 | return -1; |
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361 | |
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362 | addr += tmp_len; |
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363 | paddr += tmp_len; |
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364 | len -= tmp_len/4; |
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365 | |
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366 | /* Transfer all 1k blocks */ |
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367 | while (len >= 128) { |
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368 | |
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369 | if (dma_from_pci_1k(addr, paddr, 128) < 0) |
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370 | return -1; |
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371 | addr += 512; |
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372 | paddr += 512; |
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373 | len -= 128; |
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374 | |
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375 | } |
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376 | |
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377 | /* Transfer last words */ |
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378 | if (len) return dma_from_pci_1k(addr, paddr, len); |
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379 | |
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380 | return 0; |
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381 | } |
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382 | |
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383 | void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function) { |
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384 | unsigned int data; |
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385 | |
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386 | pci_read_config_dword(0, slot, function, PCI_COMMAND, &data); |
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387 | pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY); |
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388 | |
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389 | } |
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390 | |
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391 | void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function) { |
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392 | unsigned int data; |
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393 | |
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394 | pci_read_config_dword(0, slot, function, PCI_COMMAND, &data); |
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395 | pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER); |
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396 | |
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397 | } |
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398 | |
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399 | static inline void swap_res(struct pci_res **p1, struct pci_res **p2) { |
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400 | |
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401 | struct pci_res *tmp = *p1; |
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402 | *p1 = *p2; |
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403 | *p2 = tmp; |
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404 | |
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405 | } |
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406 | |
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407 | /* pci_allocate_resources |
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408 | * |
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409 | * This function scans the bus and assigns PCI addresses to all devices. It handles both |
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410 | * single function and multi function devices. All allocated devices are enabled and |
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411 | * latency timers are set to 40. |
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412 | * |
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413 | * NOTE that it only allocates PCI memory space devices. IO spaces are not enabled. |
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414 | * Also, it does not handle pci-pci bridges. They are left disabled. |
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415 | * |
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416 | * |
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417 | */ |
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418 | void pci_allocate_resources(void) { |
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419 | |
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420 | unsigned int slot, numfuncs, func, id, pos, size, tmp, i, swapped, addr, dev, fn; |
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421 | unsigned char header; |
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422 | struct pci_res **res; |
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423 | |
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424 | res = (struct pci_res **) malloc(sizeof(struct pci_res *)*32*8*6); |
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425 | |
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426 | for (i = 0; i < 32*8*6; i++) { |
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427 | res[i] = (struct pci_res *) malloc(sizeof(struct pci_res)); |
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428 | res[i]->size = 0; |
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429 | res[i]->devfn = i; |
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430 | } |
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431 | |
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432 | for(slot = 0; slot< PCI_MAX_DEVICES; slot++) { |
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433 | |
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434 | pci_read_config_dword(0, slot, 0, PCI_VENDOR_ID, &id); |
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435 | |
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436 | if(id == PCI_INVALID_VENDORDEVICEID || id == 0) { |
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437 | /* |
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438 | * This slot is empty |
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439 | */ |
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440 | continue; |
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441 | } |
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442 | |
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443 | pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); |
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444 | |
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445 | if(header & PCI_MULTI_FUNCTION) { |
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446 | numfuncs = PCI_MAX_FUNCTIONS; |
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447 | } |
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448 | else { |
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449 | numfuncs = 1; |
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450 | } |
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451 | |
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452 | for(func = 0; func < numfuncs; func++) { |
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453 | |
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454 | pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id); |
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455 | if(id == PCI_INVALID_VENDORDEVICEID || id == 0) { |
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456 | continue; |
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457 | } |
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458 | |
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459 | pci_read_config_dword(0, slot, func, PCI_CLASS_REVISION, &tmp); |
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460 | tmp >>= 16; |
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461 | if (tmp == PCI_CLASS_BRIDGE_PCI) { |
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462 | continue; |
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463 | } |
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464 | |
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465 | for (pos = 0; pos < 6; pos++) { |
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466 | pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff); |
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467 | pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), &size); |
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468 | |
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469 | if (size == 0 || size == 0xffffffff || (size & 0xff) != 0) { |
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470 | pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0); |
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471 | continue; |
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472 | } |
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473 | |
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474 | else { |
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475 | res[slot*8*6+func*6+pos]->size = ~size+1; |
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476 | res[slot*8*6+func*6+pos]->devfn = slot*8 + func; |
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477 | res[slot*8*6+func*6+pos]->bar = pos; |
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478 | |
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479 | DBG("Slot: %d, function: %d, bar%d size: %x\n", slot, func, pos, ~size+1); |
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480 | } |
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481 | } |
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482 | } |
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483 | } |
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484 | |
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485 | |
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486 | /* Sort the resources in descending order */ |
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487 | |
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488 | swapped = 1; |
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489 | while (swapped == 1) { |
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490 | swapped = 0; |
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491 | for (i = 0; i < 32*8*6-1; i++) { |
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492 | if (res[i]->size < res[i+1]->size) { |
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493 | swap_res(&res[i], &res[i+1]); |
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494 | swapped = 1; |
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495 | } |
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496 | } |
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497 | i++; |
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498 | } |
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499 | |
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500 | /* Assign the BARs */ |
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501 | |
---|
502 | addr = PCI_MEM_START; |
---|
503 | for (i = 0; i < 32*8*6; i++) { |
---|
504 | |
---|
505 | if (res[i]->size == 0) { |
---|
506 | goto done; |
---|
507 | } |
---|
508 | if ( (addr + res[i]->size) > PCI_MEM_END) { |
---|
509 | printk("Out of PCI memory space, all devices not configured.\n"); |
---|
510 | goto done; |
---|
511 | } |
---|
512 | |
---|
513 | dev = res[i]->devfn >> 3; |
---|
514 | fn = res[i]->devfn & 7; |
---|
515 | |
---|
516 | DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar); |
---|
517 | pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr); |
---|
518 | addr += res[i]->size; |
---|
519 | |
---|
520 | /* Set latency timer to 64 */ |
---|
521 | pci_read_config_dword(0, dev, fn, 0xC, &tmp); |
---|
522 | pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000); |
---|
523 | |
---|
524 | pci_mem_enable(0, dev, fn); |
---|
525 | |
---|
526 | } |
---|
527 | |
---|
528 | |
---|
529 | |
---|
530 | done: |
---|
531 | |
---|
532 | #ifdef PCI_INFO |
---|
533 | printk("\nPCI devices found and configured:\n"); |
---|
534 | for (slot = 0; slot < PCI_MAX_DEVICES; slot++) { |
---|
535 | |
---|
536 | pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); |
---|
537 | |
---|
538 | if(header & PCI_MULTI_FUNCTION) { |
---|
539 | numfuncs = PCI_MAX_FUNCTIONS; |
---|
540 | } |
---|
541 | else { |
---|
542 | numfuncs = 1; |
---|
543 | } |
---|
544 | |
---|
545 | for (func = 0; func < numfuncs; func++) { |
---|
546 | |
---|
547 | pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp); |
---|
548 | |
---|
549 | if (tmp & PCI_COMMAND_MEMORY) { |
---|
550 | |
---|
551 | pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id); |
---|
552 | |
---|
553 | if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue; |
---|
554 | |
---|
555 | printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16); |
---|
556 | |
---|
557 | for (pos = 0; pos < 6; pos++) { |
---|
558 | pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + pos*4, &tmp); |
---|
559 | |
---|
560 | if (tmp != 0 && tmp != 0xffffffff && (tmp & 0xff) == 0) { |
---|
561 | |
---|
562 | printk("\tBAR %d: %x\n", pos, tmp); |
---|
563 | } |
---|
564 | |
---|
565 | } |
---|
566 | printk("\n"); |
---|
567 | |
---|
568 | } |
---|
569 | |
---|
570 | } |
---|
571 | } |
---|
572 | printk("\n"); |
---|
573 | #endif |
---|
574 | |
---|
575 | for (i = 0; i < 1536; i++) { |
---|
576 | free(res[i]); |
---|
577 | } |
---|
578 | free(res); |
---|
579 | } |
---|
580 | |
---|
581 | |
---|
582 | |
---|
583 | |
---|
584 | |
---|
585 | |
---|
586 | |
---|
587 | /* |
---|
588 | * This routine determines the maximum bus number in the system |
---|
589 | */ |
---|
590 | int init_pci(void) |
---|
591 | { |
---|
592 | unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs; |
---|
593 | unsigned char ucHeader; |
---|
594 | unsigned char ucMaxSubordinate; |
---|
595 | unsigned int ulClass, ulDeviceID; |
---|
596 | |
---|
597 | init_at697_pci(); |
---|
598 | pci_allocate_resources(); |
---|
599 | |
---|
600 | /* |
---|
601 | * Scan PCI bus 0 looking for PCI-PCI bridges |
---|
602 | */ |
---|
603 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
---|
604 | (void)pci_read_config_dword(0, |
---|
605 | ucSlotNumber, |
---|
606 | 0, |
---|
607 | PCI_VENDOR_ID, |
---|
608 | &ulDeviceID); |
---|
609 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
---|
610 | /* |
---|
611 | * This slot is empty |
---|
612 | */ |
---|
613 | continue; |
---|
614 | } |
---|
615 | (void)pci_read_config_byte(0, |
---|
616 | ucSlotNumber, |
---|
617 | 0, |
---|
618 | PCI_HEADER_TYPE, |
---|
619 | &ucHeader); |
---|
620 | if(ucHeader&PCI_MULTI_FUNCTION) { |
---|
621 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
---|
622 | } |
---|
623 | else { |
---|
624 | ucNumFuncs=1; |
---|
625 | } |
---|
626 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
---|
627 | (void)pci_read_config_dword(0, |
---|
628 | ucSlotNumber, |
---|
629 | ucFnNumber, |
---|
630 | PCI_VENDOR_ID, |
---|
631 | &ulDeviceID); |
---|
632 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
---|
633 | /* |
---|
634 | * This slot/function is empty |
---|
635 | */ |
---|
636 | continue; |
---|
637 | } |
---|
638 | |
---|
639 | /* |
---|
640 | * This slot/function has a device fitted. |
---|
641 | */ |
---|
642 | (void)pci_read_config_dword(0, |
---|
643 | ucSlotNumber, |
---|
644 | ucFnNumber, |
---|
645 | PCI_CLASS_REVISION, |
---|
646 | &ulClass); |
---|
647 | ulClass >>= 16; |
---|
648 | if (ulClass == PCI_CLASS_BRIDGE_PCI) { |
---|
649 | /* |
---|
650 | * We have found a PCI-PCI bridge |
---|
651 | */ |
---|
652 | (void)pci_read_config_byte(0, |
---|
653 | ucSlotNumber, |
---|
654 | ucFnNumber, |
---|
655 | PCI_SUBORDINATE_BUS, |
---|
656 | &ucMaxSubordinate); |
---|
657 | if(ucMaxSubordinate>ucMaxPCIBus) { |
---|
658 | ucMaxPCIBus=ucMaxSubordinate; |
---|
659 | } |
---|
660 | } |
---|
661 | } |
---|
662 | } |
---|
663 | return 0; |
---|
664 | } |
---|
665 | |
---|
666 | /* |
---|
667 | * Return the number of PCI busses in the system |
---|
668 | */ |
---|
669 | unsigned char BusCountPCI(void) |
---|
670 | { |
---|
671 | return(ucMaxPCIBus+1); |
---|
672 | } |
---|