[931e9cc0] | 1 | /* |
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| 2 | * pci.c : this file contains basic PCI Io functions. |
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| 3 | * |
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| 4 | * Copyright (C) 1999 valette@crf.canon.fr |
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| 5 | * |
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| 6 | * This code is heavily inspired by the public specification of STREAM V2 |
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| 7 | * that can be found at : |
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| 8 | * |
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| 9 | * <http://www.chorus.com/Documentation/index.html> by following |
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| 10 | * the STREAM API Specification Document link. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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[801a7ba6] | 13 | * found in the file LICENSE in this distribution or at |
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[931e9cc0] | 14 | * http://www.rtems.com/license/LICENSE. |
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| 15 | * |
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| 16 | * Till Straumann, <strauman@slac.stanford.edu>, 1/2002 |
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| 17 | * - separated bridge detection code out of this file |
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| 18 | * |
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[44b06ca] | 19 | * Adapted to LEON2 AT697 PCI |
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[931e9cc0] | 20 | * Copyright (C) 2006 Gaisler Research |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | #include <pci.h> |
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| 25 | #include <rtems/bspIo.h> |
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| 26 | #include <stdlib.h> |
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| 27 | |
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| 28 | /* Define PCI_INFO to get a listing of configured devices at boot time */ |
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[44b06ca] | 29 | #define PCI_INFO 1 |
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[931e9cc0] | 30 | |
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| 31 | /* #define DEBUG 1 */ |
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| 32 | |
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| 33 | #ifdef DEBUG |
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| 34 | #define DBG(x...) printk(x) |
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| 35 | #else |
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[44b06ca] | 36 | #define DBG(x...) |
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[931e9cc0] | 37 | #endif |
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| 38 | |
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| 39 | /* allow for overriding these definitions */ |
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| 40 | #ifndef PCI_CONFIG_ADDR |
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| 41 | #define PCI_CONFIG_ADDR 0xcf8 |
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| 42 | #endif |
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| 43 | #ifndef PCI_CONFIG_DATA |
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| 44 | #define PCI_CONFIG_DATA 0xcfc |
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| 45 | #endif |
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| 46 | |
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| 47 | /* define a shortcut */ |
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| 48 | #define pci BSP_pci_configuration |
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| 49 | |
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| 50 | /* |
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| 51 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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| 52 | */ |
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[44b06ca] | 53 | unsigned char ucMaxPCIBus; |
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[931e9cc0] | 54 | |
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| 55 | typedef struct { |
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| 56 | volatile unsigned int pciid1; /* 0x80000100 - PCI Device identification register 1 */ |
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| 57 | volatile unsigned int pcisc; /* 0x80000104 - PCI Status & Command */ |
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| 58 | volatile unsigned int pciid2; /* 0x80000108 - PCI Device identification register 2 */ |
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| 59 | volatile unsigned int pcibhlc; /* 0x8000010c - BIST, Header type, Cache line size register */ |
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| 60 | volatile unsigned int mbar1; /* 0x80000110 - Memory Base Address Register 1 */ |
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| 61 | volatile unsigned int mbar2; /* 0x80000114 - Memory Base Address Register 2 */ |
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| 62 | volatile unsigned int iobar3; /* 0x80000118 - IO Base Address Register 3 */ |
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[44b06ca] | 63 | volatile unsigned int dummy1[4]; /* 0x8000011c - 0x80000128 */ |
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[931e9cc0] | 64 | volatile unsigned int pcisid; /* 0x8000012c - Subsystem identification register */ |
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| 65 | volatile unsigned int dummy2; /* 0x80000130 */ |
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| 66 | volatile unsigned int pcicp; /* 0x80000134 - PCI capabilities pointer register */ |
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| 67 | volatile unsigned int dummy3; /* 0x80000138 */ |
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| 68 | volatile unsigned int pcili; /* 0x8000013c - PCI latency interrupt register */ |
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| 69 | volatile unsigned int pcirt; /* 0x80000140 - PCI retry, trdy config */ |
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| 70 | volatile unsigned int pcicw; /* 0x80000144 - PCI configuration write register */ |
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| 71 | volatile unsigned int pcisa; /* 0x80000148 - PCI Initiator Start Address */ |
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| 72 | volatile unsigned int pciiw; /* 0x8000014c - PCI Initiator Write Register */ |
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| 73 | volatile unsigned int pcidma; /* 0x80000150 - PCI DMA configuration register */ |
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| 74 | volatile unsigned int pciis; /* 0x80000154 - PCI Initiator Status Register */ |
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| 75 | volatile unsigned int pciic; /* 0x80000158 - PCI Initiator Configuration */ |
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[44b06ca] | 76 | volatile unsigned int pcitpa; /* 0x8000015c - PCI Target Page Address Register */ |
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[931e9cc0] | 77 | volatile unsigned int pcitsc; /* 0x80000160 - PCI Target Status-Command Register */ |
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| 78 | volatile unsigned int pciite; /* 0x80000164 - PCI Interrupt Enable Register */ |
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| 79 | volatile unsigned int pciitp; /* 0x80000168 - PCI Interrupt Pending Register */ |
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| 80 | volatile unsigned int pciitf; /* 0x8000016c - PCI Interrupt Force Register */ |
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[44b06ca] | 81 | volatile unsigned int pcid; /* 0x80000170 - PCI Data Register */ |
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[931e9cc0] | 82 | volatile unsigned int pcibe; /* 0x80000174 - PCI Burst End Register */ |
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| 83 | volatile unsigned int pcidmaa; /* 0x80000178 - PCI DMA Address Register */ |
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| 84 | } AT697_PCI_Map; |
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| 85 | |
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| 86 | AT697_PCI_Map *pcic = (AT697_PCI_Map *) 0x80000100; |
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| 87 | |
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| 88 | #define PCI_MEM_START 0xa0000000 |
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| 89 | #define PCI_MEM_END 0xf0000000 |
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| 90 | #define PCI_MEM_SIZE (PCI_MEM_START - PCI_MEM_END) |
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| 91 | |
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| 92 | |
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| 93 | struct pci_res { |
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| 94 | unsigned int size; |
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| 95 | unsigned char bar; |
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| 96 | unsigned char devfn; |
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| 97 | }; |
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| 98 | |
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| 99 | /* The configuration access functions uses the DMA functionality of the |
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| 100 | * AT697 pci controller to be able access all slots |
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| 101 | */ |
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[44b06ca] | 102 | |
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[38386473] | 103 | static int |
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| 104 | BSP_pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int *val) { |
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[931e9cc0] | 105 | |
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| 106 | volatile unsigned int data; |
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| 107 | |
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| 108 | if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 109 | |
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[44b06ca] | 110 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[931e9cc0] | 111 | |
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| 112 | pcic->pcisa = ( 1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f); |
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| 113 | pcic->pcidma = 0xa01; |
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| 114 | pcic->pcidmaa = (unsigned int) &data; |
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| 115 | |
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| 116 | while (pcic->pciitp == 0) |
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| 117 | ; |
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[44b06ca] | 118 | |
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| 119 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[931e9cc0] | 120 | |
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| 121 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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| 122 | pcic->pcisc |= 0x20000000; |
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| 123 | *val = 0xffffffff; |
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| 124 | } |
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| 125 | else |
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| 126 | *val = data; |
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| 127 | |
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[44b06ca] | 128 | DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), *val); |
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[931e9cc0] | 129 | |
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| 130 | return PCIBIOS_SUCCESSFUL; |
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| 131 | } |
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| 132 | |
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| 133 | |
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[44b06ca] | 134 | static int |
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[38386473] | 135 | BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) { |
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[931e9cc0] | 136 | unsigned int v; |
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| 137 | |
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| 138 | if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 139 | |
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| 140 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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| 141 | *val = 0xffff & (v >> (8*(offset & 3))); |
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| 142 | |
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| 143 | return PCIBIOS_SUCCESSFUL; |
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| 144 | } |
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| 145 | |
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| 146 | |
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[44b06ca] | 147 | static int |
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[38386473] | 148 | BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) { |
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[931e9cc0] | 149 | unsigned int v; |
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| 150 | |
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| 151 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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| 152 | |
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| 153 | *val = 0xff & (v >> (8*(offset & 3))); |
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| 154 | |
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| 155 | return PCIBIOS_SUCCESSFUL; |
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| 156 | } |
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| 157 | |
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| 158 | |
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[38386473] | 159 | static int |
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| 160 | BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int val) { |
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[931e9cc0] | 161 | |
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| 162 | if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 163 | |
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| 164 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[44b06ca] | 165 | |
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[931e9cc0] | 166 | pcic->pcisa = ( 1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f); |
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| 167 | pcic->pcidma = 0xb01; |
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| 168 | pcic->pcidmaa = (unsigned int) &val; |
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| 169 | |
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| 170 | while (pcic->pciitp == 0) |
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| 171 | ; |
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| 172 | |
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| 173 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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| 174 | pcic->pcisc |= 0x20000000; |
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| 175 | } |
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| 176 | |
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| 177 | pcic->pciitp = 0xff; /* clear interrupts */ |
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| 178 | |
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| 179 | /* DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) | (offset&0x3f), val); */ |
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| 180 | |
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| 181 | return PCIBIOS_SUCCESSFUL; |
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| 182 | } |
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| 183 | |
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| 184 | |
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[44b06ca] | 185 | static int |
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[38386473] | 186 | BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) { |
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[931e9cc0] | 187 | unsigned int v; |
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| 188 | |
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| 189 | if (offset & 1) return PCIBIOS_BAD_REGISTER_NUMBER; |
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| 190 | |
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| 191 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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| 192 | |
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| 193 | v = (v & ~(0xffff << (8*(offset&3)))) | ((0xffff&val) << (8*(offset&3))); |
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| 194 | |
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| 195 | return pci_write_config_dword(bus, slot, function, offset&~3, v); |
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| 196 | } |
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| 197 | |
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| 198 | |
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[44b06ca] | 199 | static int |
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[38386473] | 200 | BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) { |
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[931e9cc0] | 201 | unsigned int v; |
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| 202 | |
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| 203 | pci_read_config_dword(bus, slot, function, offset&~3, &v); |
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| 204 | |
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| 205 | v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3))); |
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[44b06ca] | 206 | |
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[931e9cc0] | 207 | return pci_write_config_dword(bus, slot, function, offset&~3, v); |
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| 208 | } |
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| 209 | |
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| 210 | |
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| 211 | |
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| 212 | const pci_config_access_functions pci_access_functions = { |
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[38386473] | 213 | BSP_pci_read_config_byte, |
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| 214 | BSP_pci_read_config_word, |
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| 215 | BSP_pci_read_config_dword, |
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| 216 | BSP_pci_write_config_byte, |
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| 217 | BSP_pci_write_config_word, |
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| 218 | BSP_pci_write_config_dword |
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[931e9cc0] | 219 | }; |
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| 220 | |
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[df0243f] | 221 | rtems_pci_config_t BSP_pci_configuration = { |
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| 222 | (volatile unsigned char*)PCI_CONFIG_ADDR, |
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| 223 | (volatile unsigned char*)PCI_CONFIG_DATA, |
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| 224 | &pci_access_functions |
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| 225 | }; |
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[931e9cc0] | 226 | |
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| 227 | |
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| 228 | void init_at697_pci(void) { |
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| 229 | |
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| 230 | /* Reset */ |
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| 231 | pcic->pciic = 0xffffffff; |
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| 232 | |
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| 233 | /* Map system RAM at pci address 0x40000000 and system SDRAM to pci address 0x60000000 */ |
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| 234 | pcic->mbar1 = 0x40000000; |
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| 235 | pcic->mbar2 = 0x60000000; |
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| 236 | pcic->pcitpa = 0x40006000; |
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| 237 | |
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| 238 | /* Enable PCI master and target memory command response */ |
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| 239 | pcic->pcisc |= 0x40 | 0x6; |
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| 240 | |
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| 241 | /* Set latency timer to 64 */ |
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| 242 | pcic->pcibhlc = 0x00004000; |
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| 243 | |
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| 244 | /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */ |
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| 245 | pcic->pciic = 0x41; |
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| 246 | |
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| 247 | pcic->pciite = 0xff; |
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| 248 | |
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| 249 | } |
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| 250 | |
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| 251 | /* May not pass a 1k boundary */ |
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| 252 | int dma_from_pci_1k(unsigned int addr, unsigned int paddr, unsigned char len) { |
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| 253 | |
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| 254 | int retval = 0; |
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| 255 | |
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| 256 | if (addr & 3) { |
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| 257 | return -1; |
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| 258 | } |
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| 259 | |
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[44b06ca] | 260 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[931e9cc0] | 261 | |
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| 262 | pcic->pcisa = paddr; |
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| 263 | pcic->pcidma = 0xc00 | len; |
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| 264 | pcic->pcidmaa = addr; |
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| 265 | |
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| 266 | while (pcic->pciitp == 0) |
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| 267 | ; |
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| 268 | |
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[44b06ca] | 269 | if (pcic->pciitp & 0x7F) { |
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[931e9cc0] | 270 | retval = -1; |
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| 271 | } |
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| 272 | |
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[44b06ca] | 273 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[931e9cc0] | 274 | |
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| 275 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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| 276 | pcic->pcisc |= 0x20000000; |
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| 277 | retval = -1; |
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| 278 | } |
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[44b06ca] | 279 | |
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[931e9cc0] | 280 | return retval; |
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| 281 | } |
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| 282 | |
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| 283 | /* May not pass a 1k boundary */ |
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| 284 | int dma_to_pci_1k(unsigned int addr, unsigned int paddr, unsigned char len) { |
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| 285 | |
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| 286 | int retval = 0; |
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| 287 | |
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| 288 | if (addr & 3) return -1; |
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| 289 | |
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[44b06ca] | 290 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[931e9cc0] | 291 | |
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| 292 | pcic->pcisa = paddr; |
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| 293 | pcic->pcidma = 0x700 | len; |
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| 294 | pcic->pcidmaa = addr; |
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| 295 | |
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| 296 | while (pcic->pciitp == 0) |
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| 297 | ; |
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[44b06ca] | 298 | |
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[931e9cc0] | 299 | if (pcic->pciitp & 0x7F) retval = -1; |
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| 300 | |
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[44b06ca] | 301 | pcic->pciitp = 0xff; /* clear interrupts */ |
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[931e9cc0] | 302 | |
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| 303 | if (pcic->pcisc & 0x20000000) { /* Master Abort */ |
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| 304 | pcic->pcisc |= 0x20000000; |
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| 305 | retval = -1; |
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| 306 | } |
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| 307 | |
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| 308 | return retval; |
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| 309 | } |
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| 310 | |
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| 311 | /* Transfer len number of words from addr to paddr */ |
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| 312 | int dma_to_pci(unsigned int addr, unsigned int paddr, unsigned int len) { |
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[44b06ca] | 313 | |
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[931e9cc0] | 314 | int tmp_len; |
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| 315 | |
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| 316 | /* Align to 1k boundary */ |
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| 317 | tmp_len = ((addr + 1024) & 0xfffffc00) - addr; |
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| 318 | |
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| 319 | tmp_len = (tmp_len/4 < len) ? tmp_len : (len*4); |
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| 320 | |
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| 321 | if (dma_to_pci_1k(addr, paddr, tmp_len/4) < 0) |
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| 322 | return -1; |
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| 323 | |
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| 324 | addr += tmp_len; |
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| 325 | paddr += tmp_len; |
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| 326 | len -= tmp_len/4; |
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[44b06ca] | 327 | |
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[931e9cc0] | 328 | /* Transfer all 1k blocks */ |
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| 329 | while (len >= 128) { |
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| 330 | |
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[44b06ca] | 331 | if (dma_to_pci_1k(addr, paddr, 128) < 0) |
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[931e9cc0] | 332 | return -1; |
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| 333 | |
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| 334 | addr += 512; |
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| 335 | paddr += 512; |
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| 336 | len -= 128; |
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| 337 | |
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| 338 | } |
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| 339 | |
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| 340 | /* Transfer last words */ |
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| 341 | if (len) return dma_to_pci_1k(addr, paddr, len); |
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| 342 | |
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| 343 | return 0; |
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| 344 | } |
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| 345 | |
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| 346 | /* Transfer len number of words from paddr to addr */ |
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| 347 | int dma_from_pci(unsigned int addr, unsigned int paddr, unsigned int len) { |
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| 348 | |
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| 349 | int tmp_len; |
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| 350 | |
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| 351 | /* Align to 1k boundary */ |
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| 352 | tmp_len = ((addr + 1024) & 0xfffffc00) - addr; |
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| 353 | |
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| 354 | tmp_len = (tmp_len/4 < len) ? tmp_len : (len*4); |
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| 355 | |
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| 356 | if (dma_from_pci_1k(addr, paddr, tmp_len/4) < 0) |
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| 357 | return -1; |
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| 358 | |
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| 359 | addr += tmp_len; |
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| 360 | paddr += tmp_len; |
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| 361 | len -= tmp_len/4; |
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[44b06ca] | 362 | |
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[931e9cc0] | 363 | /* Transfer all 1k blocks */ |
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| 364 | while (len >= 128) { |
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| 365 | |
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| 366 | if (dma_from_pci_1k(addr, paddr, 128) < 0) |
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| 367 | return -1; |
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| 368 | addr += 512; |
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| 369 | paddr += 512; |
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| 370 | len -= 128; |
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| 371 | |
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| 372 | } |
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| 373 | |
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| 374 | /* Transfer last words */ |
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| 375 | if (len) return dma_from_pci_1k(addr, paddr, len); |
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| 376 | |
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| 377 | return 0; |
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| 378 | } |
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| 379 | |
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| 380 | void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function) { |
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| 381 | unsigned int data; |
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| 382 | |
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| 383 | pci_read_config_dword(0, slot, function, PCI_COMMAND, &data); |
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[44b06ca] | 384 | pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY); |
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[931e9cc0] | 385 | |
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| 386 | } |
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| 387 | |
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| 388 | void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function) { |
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| 389 | unsigned int data; |
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| 390 | |
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| 391 | pci_read_config_dword(0, slot, function, PCI_COMMAND, &data); |
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[44b06ca] | 392 | pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER); |
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[931e9cc0] | 393 | |
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| 394 | } |
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| 395 | |
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| 396 | static inline void swap_res(struct pci_res **p1, struct pci_res **p2) { |
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| 397 | |
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| 398 | struct pci_res *tmp = *p1; |
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| 399 | *p1 = *p2; |
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| 400 | *p2 = tmp; |
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| 401 | |
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| 402 | } |
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| 403 | |
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| 404 | /* pci_allocate_resources |
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| 405 | * |
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| 406 | * This function scans the bus and assigns PCI addresses to all devices. It handles both |
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| 407 | * single function and multi function devices. All allocated devices are enabled and |
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| 408 | * latency timers are set to 40. |
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| 409 | * |
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| 410 | * NOTE that it only allocates PCI memory space devices. IO spaces are not enabled. |
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[44b06ca] | 411 | * Also, it does not handle pci-pci bridges. They are left disabled. |
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[931e9cc0] | 412 | * |
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| 413 | * |
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| 414 | */ |
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| 415 | void pci_allocate_resources(void) { |
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| 416 | |
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| 417 | unsigned int slot, numfuncs, func, id, pos, size, tmp, i, swapped, addr, dev, fn; |
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| 418 | unsigned char header; |
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| 419 | struct pci_res **res; |
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| 420 | |
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| 421 | res = (struct pci_res **) malloc(sizeof(struct pci_res *)*32*8*6); |
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| 422 | |
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| 423 | for (i = 0; i < 32*8*6; i++) { |
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[44b06ca] | 424 | res[i] = (struct pci_res *) malloc(sizeof(struct pci_res)); |
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[931e9cc0] | 425 | res[i]->size = 0; |
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| 426 | res[i]->devfn = i; |
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| 427 | } |
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| 428 | |
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| 429 | for(slot = 0; slot< PCI_MAX_DEVICES; slot++) { |
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| 430 | |
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| 431 | pci_read_config_dword(0, slot, 0, PCI_VENDOR_ID, &id); |
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| 432 | |
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| 433 | if(id == PCI_INVALID_VENDORDEVICEID || id == 0) { |
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| 434 | /* |
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| 435 | * This slot is empty |
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| 436 | */ |
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| 437 | continue; |
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| 438 | } |
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| 439 | |
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| 440 | pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); |
---|
[44b06ca] | 441 | |
---|
[8bbf69e] | 442 | if(header & PCI_HEADER_TYPE_MULTI_FUNCTION) { |
---|
[931e9cc0] | 443 | numfuncs = PCI_MAX_FUNCTIONS; |
---|
| 444 | } |
---|
| 445 | else { |
---|
| 446 | numfuncs = 1; |
---|
| 447 | } |
---|
| 448 | |
---|
| 449 | for(func = 0; func < numfuncs; func++) { |
---|
| 450 | |
---|
| 451 | pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id); |
---|
| 452 | if(id == PCI_INVALID_VENDORDEVICEID || id == 0) { |
---|
| 453 | continue; |
---|
| 454 | } |
---|
| 455 | |
---|
| 456 | pci_read_config_dword(0, slot, func, PCI_CLASS_REVISION, &tmp); |
---|
| 457 | tmp >>= 16; |
---|
| 458 | if (tmp == PCI_CLASS_BRIDGE_PCI) { |
---|
| 459 | continue; |
---|
| 460 | } |
---|
[44b06ca] | 461 | |
---|
[931e9cc0] | 462 | for (pos = 0; pos < 6; pos++) { |
---|
| 463 | pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff); |
---|
| 464 | pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), &size); |
---|
| 465 | |
---|
| 466 | if (size == 0 || size == 0xffffffff || (size & 0xff) != 0) { |
---|
| 467 | pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0); |
---|
| 468 | continue; |
---|
| 469 | } |
---|
| 470 | |
---|
| 471 | else { |
---|
| 472 | res[slot*8*6+func*6+pos]->size = ~size+1; |
---|
| 473 | res[slot*8*6+func*6+pos]->devfn = slot*8 + func; |
---|
| 474 | res[slot*8*6+func*6+pos]->bar = pos; |
---|
| 475 | |
---|
| 476 | DBG("Slot: %d, function: %d, bar%d size: %x\n", slot, func, pos, ~size+1); |
---|
| 477 | } |
---|
| 478 | } |
---|
| 479 | } |
---|
| 480 | } |
---|
| 481 | |
---|
| 482 | |
---|
[44b06ca] | 483 | /* Sort the resources in descending order */ |
---|
[931e9cc0] | 484 | |
---|
| 485 | swapped = 1; |
---|
| 486 | while (swapped == 1) { |
---|
| 487 | swapped = 0; |
---|
| 488 | for (i = 0; i < 32*8*6-1; i++) { |
---|
| 489 | if (res[i]->size < res[i+1]->size) { |
---|
| 490 | swap_res(&res[i], &res[i+1]); |
---|
| 491 | swapped = 1; |
---|
| 492 | } |
---|
| 493 | } |
---|
| 494 | i++; |
---|
| 495 | } |
---|
| 496 | |
---|
| 497 | /* Assign the BARs */ |
---|
| 498 | |
---|
| 499 | addr = PCI_MEM_START; |
---|
| 500 | for (i = 0; i < 32*8*6; i++) { |
---|
| 501 | |
---|
| 502 | if (res[i]->size == 0) { |
---|
| 503 | goto done; |
---|
| 504 | } |
---|
| 505 | if ( (addr + res[i]->size) > PCI_MEM_END) { |
---|
| 506 | printk("Out of PCI memory space, all devices not configured.\n"); |
---|
| 507 | goto done; |
---|
| 508 | } |
---|
[44b06ca] | 509 | |
---|
[931e9cc0] | 510 | dev = res[i]->devfn >> 3; |
---|
| 511 | fn = res[i]->devfn & 7; |
---|
[44b06ca] | 512 | |
---|
[931e9cc0] | 513 | DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar); |
---|
| 514 | pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr); |
---|
| 515 | addr += res[i]->size; |
---|
| 516 | |
---|
| 517 | /* Set latency timer to 64 */ |
---|
[44b06ca] | 518 | pci_read_config_dword(0, dev, fn, 0xC, &tmp); |
---|
[931e9cc0] | 519 | pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000); |
---|
| 520 | |
---|
[44b06ca] | 521 | pci_mem_enable(0, dev, fn); |
---|
| 522 | |
---|
| 523 | } |
---|
[931e9cc0] | 524 | |
---|
| 525 | |
---|
| 526 | |
---|
| 527 | done: |
---|
| 528 | |
---|
| 529 | #ifdef PCI_INFO |
---|
| 530 | printk("\nPCI devices found and configured:\n"); |
---|
| 531 | for (slot = 0; slot < PCI_MAX_DEVICES; slot++) { |
---|
[44b06ca] | 532 | |
---|
| 533 | pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); |
---|
| 534 | |
---|
[8bbf69e] | 535 | if(header & PCI_HEADER_TYPE_MULTI_FUNCTION) { |
---|
[931e9cc0] | 536 | numfuncs = PCI_MAX_FUNCTIONS; |
---|
| 537 | } |
---|
| 538 | else { |
---|
| 539 | numfuncs = 1; |
---|
| 540 | } |
---|
| 541 | |
---|
| 542 | for (func = 0; func < numfuncs; func++) { |
---|
[44b06ca] | 543 | |
---|
[931e9cc0] | 544 | pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp); |
---|
| 545 | |
---|
[44b06ca] | 546 | if (tmp & PCI_COMMAND_MEMORY) { |
---|
| 547 | |
---|
[931e9cc0] | 548 | pci_read_config_dword(0, slot, func, PCI_VENDOR_ID, &id); |
---|
| 549 | |
---|
| 550 | if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue; |
---|
[44b06ca] | 551 | |
---|
[931e9cc0] | 552 | printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16); |
---|
| 553 | |
---|
| 554 | for (pos = 0; pos < 6; pos++) { |
---|
| 555 | pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + pos*4, &tmp); |
---|
| 556 | |
---|
| 557 | if (tmp != 0 && tmp != 0xffffffff && (tmp & 0xff) == 0) { |
---|
| 558 | |
---|
| 559 | printk("\tBAR %d: %x\n", pos, tmp); |
---|
| 560 | } |
---|
[44b06ca] | 561 | |
---|
[931e9cc0] | 562 | } |
---|
| 563 | printk("\n"); |
---|
| 564 | |
---|
[44b06ca] | 565 | } |
---|
[931e9cc0] | 566 | |
---|
| 567 | } |
---|
| 568 | } |
---|
| 569 | printk("\n"); |
---|
| 570 | #endif |
---|
[44b06ca] | 571 | |
---|
[931e9cc0] | 572 | for (i = 0; i < 1536; i++) { |
---|
| 573 | free(res[i]); |
---|
| 574 | } |
---|
| 575 | free(res); |
---|
| 576 | } |
---|
| 577 | |
---|
| 578 | |
---|
| 579 | |
---|
| 580 | |
---|
| 581 | |
---|
| 582 | |
---|
| 583 | |
---|
| 584 | /* |
---|
| 585 | * This routine determines the maximum bus number in the system |
---|
| 586 | */ |
---|
[49c8f45] | 587 | int init_pci(void) |
---|
[931e9cc0] | 588 | { |
---|
| 589 | unsigned char ucSlotNumber, ucFnNumber, ucNumFuncs; |
---|
| 590 | unsigned char ucHeader; |
---|
| 591 | unsigned char ucMaxSubordinate; |
---|
[44b06ca] | 592 | unsigned int ulClass, ulDeviceID; |
---|
[931e9cc0] | 593 | |
---|
| 594 | init_at697_pci(); |
---|
| 595 | pci_allocate_resources(); |
---|
| 596 | |
---|
| 597 | /* |
---|
| 598 | * Scan PCI bus 0 looking for PCI-PCI bridges |
---|
| 599 | */ |
---|
| 600 | for(ucSlotNumber=0;ucSlotNumber<PCI_MAX_DEVICES;ucSlotNumber++) { |
---|
| 601 | (void)pci_read_config_dword(0, |
---|
| 602 | ucSlotNumber, |
---|
| 603 | 0, |
---|
| 604 | PCI_VENDOR_ID, |
---|
| 605 | &ulDeviceID); |
---|
| 606 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
---|
| 607 | /* |
---|
| 608 | * This slot is empty |
---|
| 609 | */ |
---|
| 610 | continue; |
---|
| 611 | } |
---|
| 612 | (void)pci_read_config_byte(0, |
---|
| 613 | ucSlotNumber, |
---|
| 614 | 0, |
---|
| 615 | PCI_HEADER_TYPE, |
---|
| 616 | &ucHeader); |
---|
[8bbf69e] | 617 | if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION) { |
---|
[931e9cc0] | 618 | ucNumFuncs=PCI_MAX_FUNCTIONS; |
---|
| 619 | } |
---|
| 620 | else { |
---|
| 621 | ucNumFuncs=1; |
---|
| 622 | } |
---|
| 623 | for(ucFnNumber=0;ucFnNumber<ucNumFuncs;ucFnNumber++) { |
---|
| 624 | (void)pci_read_config_dword(0, |
---|
| 625 | ucSlotNumber, |
---|
| 626 | ucFnNumber, |
---|
| 627 | PCI_VENDOR_ID, |
---|
| 628 | &ulDeviceID); |
---|
| 629 | if(ulDeviceID==PCI_INVALID_VENDORDEVICEID) { |
---|
| 630 | /* |
---|
| 631 | * This slot/function is empty |
---|
| 632 | */ |
---|
| 633 | continue; |
---|
| 634 | } |
---|
| 635 | |
---|
| 636 | /* |
---|
| 637 | * This slot/function has a device fitted. |
---|
| 638 | */ |
---|
| 639 | (void)pci_read_config_dword(0, |
---|
| 640 | ucSlotNumber, |
---|
| 641 | ucFnNumber, |
---|
| 642 | PCI_CLASS_REVISION, |
---|
| 643 | &ulClass); |
---|
| 644 | ulClass >>= 16; |
---|
| 645 | if (ulClass == PCI_CLASS_BRIDGE_PCI) { |
---|
| 646 | /* |
---|
| 647 | * We have found a PCI-PCI bridge |
---|
| 648 | */ |
---|
| 649 | (void)pci_read_config_byte(0, |
---|
| 650 | ucSlotNumber, |
---|
| 651 | ucFnNumber, |
---|
| 652 | PCI_SUBORDINATE_BUS, |
---|
| 653 | &ucMaxSubordinate); |
---|
| 654 | if(ucMaxSubordinate>ucMaxPCIBus) { |
---|
| 655 | ucMaxPCIBus=ucMaxSubordinate; |
---|
| 656 | } |
---|
| 657 | } |
---|
| 658 | } |
---|
| 659 | } |
---|
| 660 | return 0; |
---|
| 661 | } |
---|
| 662 | |
---|
| 663 | /* |
---|
| 664 | * Return the number of PCI busses in the system |
---|
| 665 | */ |
---|
[49c8f45] | 666 | unsigned char BusCountPCI(void) |
---|
[931e9cc0] | 667 | { |
---|
| 668 | return(ucMaxPCIBus+1); |
---|
| 669 | } |
---|