source: rtems/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c @ 9d88008

4.115
Last change on this file since 9d88008 was 9d88008, checked in by Daniel Hellstrom <daniel@…>, on 12/18/13 at 15:42:16

AT697PCI: fix PCI cfg writes
  • Property mode set to 100644
File size: 18.0 KB
Line 
1/*  LEON2 AT697 PCI Host Driver.
2 *
3 *  COPYRIGHT (c) 2008.
4 *  Cobham Gaisler AB.
5 *
6 *  Configures the AT697 PCI core and initialize,
7 *   - the PCI Library (pci.c)
8 *   - the general part of the PCI Bus driver (pci_bus.c)
9 * 
10 *  System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
11 *  default taken from Plug and Play, but may be overridden by the
12 *  driver resources INTA#..INTD#.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 */
18
19/* Configurable parameters
20 * =======================
21 *  INT[A..D]#         Select system IRQ (can be tranlated into I/O interrupt)
22 *  INT[A..D]#_PIO     Select PIO used to generate I/O interrupt
23 *
24 * Notes
25 * =====
26 *  IRQ must not be enabled before all PCI boards have been enabled, the
27 *  IRQ is therefore enabled first in init2. The init2() for this driver
28 *  is assumed to be executed earlier that all boards and their devices
29 *  driver's init2() function.
30 *
31 */
32
33#include <rtems/bspIo.h>
34#include <stdlib.h>
35#include <string.h>
36#include <stdio.h>
37#include <libcpu/byteorder.h>
38#include <libcpu/access.h>
39#include <pci.h>
40#include <pci/cfg.h>
41
42#include <drvmgr/drvmgr.h>
43#include <drvmgr/pci_bus.h>
44#include <drvmgr/leon2_amba_bus.h>
45
46#include <leon.h>
47
48/* Configuration options */
49
50#define SYSTEM_MAINMEM_START    0x40000000
51#define SYSTEM_MAINMEM_START2   0x60000000
52
53/* Interrupt assignment. Set to other value than 0xff in order to
54 * override defaults and plug&play information
55 */
56#ifndef AT697_INTA_SYSIRQ
57 #define AT697_INTA_SYSIRQ 0xff
58#endif
59#ifndef AT697_INTB_SYSIRQ
60 #define AT697_INTB_SYSIRQ 0xff
61#endif
62#ifndef AT697_INTC_SYSIRQ
63 #define AT697_INTC_SYSIRQ 0xff
64#endif
65#ifndef AT697_INTD_SYSIRQ
66 #define AT697_INTD_SYSIRQ 0xff
67#endif
68
69#ifndef AT697_INTA_PIO
70 #define AT697_INTA_PIO 0xff
71#endif
72#ifndef AT697_INTB_PIO
73 #define AT697_INTB_PIO 0xff
74#endif
75#ifndef AT697_INTC_PIO
76 #define AT697_INTC_PIO 0xff
77#endif
78#ifndef AT697_INTD_PIO
79 #define AT697_INTD_PIO 0xff
80#endif
81
82
83/* AT697 PCI */
84#define AT697_PCI_REG_ADR 0x80000100
85
86/* PCI Window used */
87#define PCI_MEM_START 0xa0000000
88#define PCI_MEM_END   0xf0000000
89#define PCI_MEM_SIZE  (PCI_MEM_END - PCI_MEM_START)
90
91/* #define DEBUG 1 */
92
93#ifdef DEBUG
94#define DBG(x...) printf(x)
95#else
96#define DBG(x...)
97#endif
98
99#define PCI_INVALID_VENDORDEVICEID      0xffffffff
100#define PCI_MULTI_FUNCTION              0x80
101
102struct at697pci_regs {
103    volatile unsigned int pciid1;        /* 0x80000100 - PCI Device identification register 1         */
104    volatile unsigned int pcisc;         /* 0x80000104 - PCI Status & Command                         */
105    volatile unsigned int pciid2;        /* 0x80000108 - PCI Device identification register 2         */
106    volatile unsigned int pcibhlc;       /* 0x8000010c - BIST, Header type, Cache line size register  */
107    volatile unsigned int mbar1;         /* 0x80000110 - Memory Base Address Register 1               */
108    volatile unsigned int mbar2;         /* 0x80000114 - Memory Base Address Register 2               */
109    volatile unsigned int iobar3;        /* 0x80000118 - IO Base Address Register 3                   */
110    volatile unsigned int dummy1[4];     /* 0x8000011c - 0x80000128                                   */
111    volatile unsigned int pcisid;        /* 0x8000012c - Subsystem identification register            */
112    volatile unsigned int dummy2;        /* 0x80000130                                                */
113    volatile unsigned int pcicp;         /* 0x80000134 - PCI capabilities pointer register            */
114    volatile unsigned int dummy3;        /* 0x80000138                                                */
115    volatile unsigned int pcili;         /* 0x8000013c - PCI latency interrupt register               */
116    volatile unsigned int pcirt;         /* 0x80000140 - PCI retry, trdy config                       */
117    volatile unsigned int pcicw;         /* 0x80000144 - PCI configuration write register             */
118    volatile unsigned int pcisa;         /* 0x80000148 - PCI Initiator Start Address                  */
119    volatile unsigned int pciiw;         /* 0x8000014c - PCI Initiator Write Register                 */
120    volatile unsigned int pcidma;        /* 0x80000150 - PCI DMA configuration register               */
121    volatile unsigned int pciis;         /* 0x80000154 - PCI Initiator Status Register                */
122    volatile unsigned int pciic;         /* 0x80000158 - PCI Initiator Configuration                  */
123    volatile unsigned int pcitpa;        /* 0x8000015c - PCI Target Page Address Register             */   
124    volatile unsigned int pcitsc;        /* 0x80000160 - PCI Target Status-Command Register           */
125    volatile unsigned int pciite;        /* 0x80000164 - PCI Interrupt Enable Register                */
126    volatile unsigned int pciitp;        /* 0x80000168 - PCI Interrupt Pending Register               */
127    volatile unsigned int pciitf;        /* 0x8000016c - PCI Interrupt Force Register                 */
128    volatile unsigned int pcid;          /* 0x80000170 - PCI Data Register                            */   
129    volatile unsigned int pcibe;         /* 0x80000174 - PCI Burst End Register                       */
130    volatile unsigned int pcidmaa;       /* 0x80000178 - PCI DMA Address Register                     */
131};
132
133/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
134 * to a system interrupt number.
135 */
136unsigned char at697_pci_irq_table[4] =
137{
138        /* INTA# */     AT697_INTA_SYSIRQ,
139        /* INTB# */     AT697_INTB_SYSIRQ,
140        /* INTC# */     AT697_INTC_SYSIRQ,
141        /* INTD# */     AT697_INTD_SYSIRQ
142};
143
144/* PCI Interrupt PIO assignment. Selects which GPIO pin will be used to
145 * generate the system IRQ.
146 *
147 * PCI IRQ -> GPIO -> 4 x I/O select -> System IRQ
148 *              ^- pio_table              ^- irq_select
149 */
150unsigned char at697_pci_irq_pio_table[4] =
151{
152        /* INTA# */     AT697_INTA_PIO,
153        /* INTB# */     AT697_INTB_PIO,
154        /* INTC# */     AT697_INTC_PIO,
155        /* INTD# */     AT697_INTD_PIO
156};
157
158/* Driver private data struture */
159struct at697pci_priv {
160        struct drvmgr_dev       *dev;
161        struct at697pci_regs    *regs;
162        int                     minor;
163
164        uint32_t                bar1_pci_adr;
165        uint32_t                bar2_pci_adr;
166
167        struct drvmgr_map_entry maps_up[3];
168        struct drvmgr_map_entry maps_down[2];
169        struct pcibus_config    config;
170};
171
172struct at697pci_priv *at697pcipriv = NULL;
173static int at697pci_minor = 0;
174
175int at697pci_init1(struct drvmgr_dev *dev);
176int at697pci_init2(struct drvmgr_dev *dev);
177
178/* AT697 PCI DRIVER */
179
180struct drvmgr_drv_ops at697pci_ops =
181{
182        .init = {at697pci_init1, at697pci_init2, NULL, NULL},
183        .remove = NULL,
184        .info = NULL
185};
186
187struct leon2_amba_dev_id at697pci_ids[] =
188{
189        {LEON2_AMBA_AT697PCI_ID},
190        {0}             /* Mark end of table */
191};
192
193struct leon2_amba_drv_info at697pci_info =
194{
195        {
196                DRVMGR_OBJ_DRV,                 /* Driver */
197                NULL,                           /* Next driver */
198                NULL,                           /* Device list */
199                DRIVER_LEON2_AMBA_AT697PCI,     /* Driver ID */
200                "AT697PCI_DRV",                 /* Driver Name */
201                DRVMGR_BUS_TYPE_LEON2_AMBA,     /* Bus Type */
202                &at697pci_ops,
203                NULL,                           /* Funcs */
204                0,                              /* No devices yet */
205                sizeof(struct at697pci_priv),   /* let drvmgr alloc private */
206        },
207        &at697pci_ids[0]
208};
209
210void at697pci_register_drv(void)
211{
212        DBG("Registering AT697 PCI driver\n");
213        drvmgr_drv_register(&at697pci_info.general);
214}
215
216/*  The configuration access functions uses the DMA functionality of the
217 *  AT697 pci controller to be able access all slots
218 */
219
220int at697pci_cfg_r32(pci_dev_t dev, int offset, uint32_t *val)
221{
222        struct at697pci_regs *regs;
223        volatile unsigned int data = 0;
224        unsigned int address;
225        int bus = PCI_DEV_BUS(dev);
226        int slot = PCI_DEV_SLOT(dev);
227        int func = PCI_DEV_FUNC(dev);
228        int retval;
229
230        if (slot > 15 || (offset & ~0xfc)) {
231                *val = 0xffffffff;
232                return PCISTS_EINVAL;
233        }
234
235        regs = at697pcipriv->regs;
236
237        regs->pciitp = 0xff; /* clear interrupts */
238
239        if ( bus == 0 ) {
240                /* PCI Access - TYPE 0 */
241                address = (1<<(16+slot)) | (func << 8) | offset;
242        } else {
243                /* PCI access - TYPE 1 */
244                address = ((bus & 0xff) << 16) | ((slot & 0x1f) << 11) |
245                                (func << 8) | offset | 1;
246        }
247        regs->pcisa = address;
248        regs->pcidma = 0xa01;
249        regs->pcidmaa = (unsigned int) &data;
250
251        while (regs->pciitp == 0)
252                ;
253
254        regs->pciitp = 0xff; /* clear interrupts */
255
256        if (regs->pcisc & 0x20000000)  { /* Master Abort */
257                regs->pcisc |= 0x20000000;
258                *val = 0xffffffff;
259                retval = PCISTS_MSTABRT;
260        } else {
261                *val = data;
262                retval = PCISTS_OK;
263        }
264
265        DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
266                bus, slot, func, offset,  address, *val);
267
268        return retval;
269}
270
271int at697pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
272{
273        uint32_t v;
274        int retval;
275
276        if (ofs & 1)
277                return PCISTS_EINVAL;
278
279        retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
280        *val = 0xffff & (v >> (8*(ofs & 0x3)));
281
282        return retval;
283}
284
285int at697pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
286{
287        uint32_t v;
288        int retval;
289
290        retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
291
292        *val = 0xff & (v >> (8*(ofs & 3)));
293
294        return retval;
295}
296
297int at697pci_cfg_w32(pci_dev_t dev, int offset, uint32_t val)
298{
299        struct at697pci_regs *regs;
300        volatile unsigned int tmp_val = val;
301        unsigned int address;
302        int bus = PCI_DEV_BUS(dev);
303        int slot = PCI_DEV_SLOT(dev);
304        int func = PCI_DEV_FUNC(dev);
305        int retval;
306
307        if (slot > 15 || (offset & ~0xfc))
308                return PCISTS_EINVAL;
309
310        regs = at697pcipriv->regs;
311
312        regs->pciitp = 0xff; /* clear interrupts */
313
314        if ( bus == 0 ) {
315                /* PCI Access - TYPE 0 */
316                address = (1<<(16+slot)) | (func << 8) | offset;
317        } else {
318                /* PCI access - TYPE 1 */
319                address = ((bus & 0xff) << 16) | ((slot & 0x1f) << 11) |
320                                (func << 8) | offset | 1;
321        }
322        regs->pcisa = address;
323        regs->pcidma = 0xb01;
324        regs->pcidmaa = (unsigned int) &tmp_val;
325
326        while (regs->pciitp == 0)
327                ;
328
329        if (regs->pcisc & 0x20000000)  { /* Master Abort */
330                regs->pcisc |= 0x20000000;
331                retval = PCISTS_MSTABRT;
332        } else
333                retval = PCISTS_OK;
334
335        regs->pciitp = 0xff; /* clear interrupts */
336
337        DBG("pci_write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
338                bus, slot, func, offset, address, val);
339
340        return retval;
341}
342
343int at697pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
344{
345        uint32_t v;
346        int retval;
347
348        if (ofs & 1)
349                return PCISTS_EINVAL;
350
351        retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
352        if (retval != PCISTS_OK)
353                return retval;
354
355        v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
356
357        return at697pci_cfg_w32(dev, ofs & ~0x3, v);
358}
359
360int at697pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
361{
362        uint32_t v;
363
364        at697pci_cfg_r32(dev, ofs & ~0x3, &v);
365
366        v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
367
368        return at697pci_cfg_w32(dev, ofs & ~0x3, v);
369}
370
371/* Return the assigned system IRQ number that corresponds to the PCI
372 * "Interrupt Pin" information from configuration space.
373 *
374 * The IRQ information is stored in the at697_pci_irq_table configurable
375 * by the user.
376 *
377 * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
378 * 0xff if not assigned.
379 */
380uint8_t at697pci_bus0_irq_map(pci_dev_t dev, int irq_pin)
381{
382        uint8_t sysIrqNr = 0; /* not assigned */
383        int irq_group;
384
385        if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
386                /* Use default IRQ decoding on PCI BUS0 according slot numbering */
387                irq_group = PCI_DEV_SLOT(dev) & 0x3;
388                irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
389                /* Valid PCI "Interrupt Pin" number */
390                sysIrqNr = at697_pci_irq_table[irq_pin];
391        }
392        return sysIrqNr;
393}
394
395int at697pci_translate(uint32_t *address, int type, int dir)
396{
397        /* No address translation implmented at this point */
398        return 0;
399}
400
401extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
402
403/* AT697 Big-Endian PCI access routines */
404struct pci_access_drv at697pci_access_drv = {
405        .cfg =
406        {
407                at697pci_cfg_r8,
408                at697pci_cfg_r16,
409                at697pci_cfg_r32,
410                at697pci_cfg_w8,
411                at697pci_cfg_w16,
412                at697pci_cfg_w32,
413        },
414        .io =
415        {       /* AT697 only supports non-standard Big-Endian PCI Bus */
416                _ld8,
417                _ld_be16,
418                _ld_be32,
419                _st8,
420                _st_be16,
421                _st_be32,
422
423        },
424        .memreg = &pci_memreg_sparc_be_ops,
425        .translate = at697pci_translate,
426};
427
428/* Initializes the AT697PCI core hardware
429 *
430 */
431int at697pci_hw_init(struct at697pci_priv *priv)
432{
433        struct at697pci_regs *regs = priv->regs;
434        unsigned short vendor = regs->pciid1 >> 16;
435        pci_dev_t host = PCI_DEV(0, 0, 0);
436
437        /* Must match ATMEL or ESA ID */
438        if ( !((vendor == 0x1202) || (vendor == 0x1E0F)) ) {
439                /* No AT697 PCI, quit */
440                return -1;
441        }
442
443        /* If not in system slot we are not host and we must abort.
444         * This is a host only driver.
445         */
446        if ((regs->pciis & 0x1000) != 0) {
447                return -1;
448        }
449
450        /* Reset PCI Core */
451        regs->pciic = 0xffffffff;
452
453        /* Mask PCI interrupts */
454        regs->pciite = 0;
455
456        /* Map parts of AT697 main memory into PCI (for DMA) */
457        regs->mbar1  = priv->bar1_pci_adr;
458        regs->mbar2  = priv->bar2_pci_adr;
459        regs->pcitpa = (priv->bar1_pci_adr & 0xff000000) |
460                       ((priv->bar2_pci_adr>>16) & 0xff00);
461
462        /* Enable PCI master and target memory command response  */
463        regs->pcisc |= 0x40 | 0x6;
464
465        /* Set latency timer to 64 */
466        regs->pcibhlc = 0x00004000;
467
468        /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */
469        regs->pciic = 0x41;
470
471        return 0;
472}
473
474/* Initializes the AT697PCI core and driver, must be called before calling init_pci()
475 *
476 * Return values
477 *  0             Successful initalization
478 *  -1            Error during initialization.
479 */
480int at697pci_init(struct at697pci_priv *priv)
481{
482        int pin;
483        union drvmgr_key_value *value;
484        char keyname_sysirq[6];
485        char keyname_pio[10];
486
487        /* PCI core, init private structure */
488        priv->regs = (struct at697pci_regs *) AT697_PCI_REG_ADR;
489
490        /* Init PCI interrupt assignment table to all use the interrupt routed
491         * through the GPIO core.
492         *
493         * INT[A..D]# selects system IRQ (and I/O interrupt)
494         * INT[A..D]#_PIO selects PIO used to generate I/O interrupt
495         */
496        strcpy(keyname_sysirq, "INTX#");
497        strcpy(keyname_pio, "INTX#_PIO");
498        for (pin=1; pin<5; pin++) {
499                if ( at697_pci_irq_table[pin-1] == 0xff ) {
500                        /* User may override hardcoded IRQ setup */
501                        keyname_sysirq[3] = 'A' + (pin-1);
502                        value = drvmgr_dev_key_get(priv->dev,
503                                        keyname_sysirq, KEY_TYPE_INT);
504                        if ( value )
505                                at697_pci_irq_table[pin-1] = value->i;
506                }
507                if ( at697_pci_irq_pio_table[pin-1] == 0xff ) {
508                        /* User may override hardcoded IRQ setup */
509                        keyname_pio[3] = 'A' + (pin-1);
510                        value = drvmgr_dev_key_get(priv->dev,
511                                                keyname_pio, KEY_TYPE_INT);
512                        if ( value )
513                                at697_pci_irq_pio_table[pin-1] = value->i;
514                }
515        }
516
517        /* Use GRPCI target BAR1 and BAR2 to map CPU RAM to PCI, this is to
518         * make it possible for PCI peripherals to do DMA directly to CPU memory
519         *
520         * Defualt is to map system RAM at pci address 0x40000000 and system
521         * SDRAM to pci address 0x60000000
522         */
523        value = drvmgr_dev_key_get(priv->dev, "tgtbar1", KEY_TYPE_INT);
524        if (value)
525                priv->bar1_pci_adr = value->i;
526        else
527                priv->bar1_pci_adr = SYSTEM_MAINMEM_START; /* default */
528
529        value = drvmgr_dev_key_get(priv->dev, "tgtbar2", KEY_TYPE_INT);
530        if (value)
531                priv->bar2_pci_adr = value->i;
532        else
533                priv->bar2_pci_adr = SYSTEM_MAINMEM_START2; /* default */
534
535        /* Init the PCI Core */
536        if ( at697pci_hw_init(priv) ) {
537                return -3;
538        }
539
540        /* Down streams translation table */
541        priv->maps_down[0].name = "AMBA -> PCI MEM Window";
542        priv->maps_down[0].size = 0xF0000000 - 0xA0000000;
543        priv->maps_down[0].from_adr = (void *)0xA0000000;
544        priv->maps_down[0].to_adr = (void *)0xA0000000;
545        /* End table */
546        priv->maps_down[1].size = 0;
547
548        /* Up streams translation table, 2x16Mb mapped 1:1  */
549        priv->maps_up[0].name = "Target BAR0 -> AMBA";
550        priv->maps_up[0].size = 0x01000000; /* 16Mb BAR1 */
551        priv->maps_up[0].from_adr = (void *)priv->bar1_pci_adr;
552        priv->maps_up[0].to_adr = (void *)priv->bar1_pci_adr;
553        priv->maps_up[1].name = "Target BAR1 -> AMBA";
554        priv->maps_up[1].size = 0x01000000; /* 16Mb BAR2 */
555        priv->maps_up[1].from_adr = (void *)priv->bar2_pci_adr;
556        priv->maps_up[1].to_adr = (void *)priv->bar2_pci_adr;
557        /* End table */
558        priv->maps_up[2].size = 0;
559
560        return 0;
561}
562
563/* Called when a core is found with the AMBA device and vendor ID
564 * given in at697pci_ids[].
565 */
566int at697pci_init1(struct drvmgr_dev *dev)
567{
568        struct at697pci_priv *priv;
569        struct pci_auto_setup at697pci_auto_cfg;
570
571        DBG("AT697PCI[%d] on bus %s\n", dev->minor_drv,
572                dev->parent->dev->name);
573
574        if ( at697pci_minor != 0 ) {
575                DBG("Driver only supports one PCI core\n");
576                return DRVMGR_FAIL;
577        }
578
579        at697pcipriv = priv = dev->priv;
580        if ( !priv )
581                return DRVMGR_NOMEM;
582
583        priv->dev = dev;
584        priv->minor = at697pci_minor++;
585
586        if (at697pci_init(priv)) {
587                DBG("Failed to initialize at697pci driver\n");
588                return DRVMGR_EIO;
589        }
590
591        /* Host is always Big-Endian */
592        pci_endian = PCI_BIG_ENDIAN;
593
594        if (pci_access_drv_register(&at697pci_access_drv)) {
595                /* Access routines registration failed */
596                return DRVMGR_FAIL;
597        }
598
599        /* Prepare memory MAP */
600        at697pci_auto_cfg.options = 0;
601        at697pci_auto_cfg.mem_start = 0;
602        at697pci_auto_cfg.mem_size = 0;
603        at697pci_auto_cfg.memio_start = PCI_MEM_START;
604        at697pci_auto_cfg.memio_size = PCI_MEM_SIZE;
605        at697pci_auto_cfg.io_start = 0;
606        at697pci_auto_cfg.io_size = 0;
607        at697pci_auto_cfg.irq_map = at697pci_bus0_irq_map;
608        at697pci_auto_cfg.irq_route = NULL; /* use standard routing */
609        pci_config_register(&at697pci_auto_cfg);
610
611        if (pci_config_init()) {
612                /* PCI configuration failed */
613                return DRVMGR_FAIL;
614        }
615
616        priv->config.maps_down = &priv->maps_down[0];
617        priv->config.maps_up = &priv->maps_up[0];
618        return pcibus_register(dev, &priv->config);
619}
620
621int at697pci_init2(struct drvmgr_dev *dev)
622{
623#if 0
624        struct at697pci_priv *priv = dev->priv;
625#endif
626        int pin, irq, pio, ioport;
627        LEON_Register_Map *regs = (LEON_Register_Map *)0x80000000;
628
629        /* Enable interrupts now that init1 has been reached for all devices
630         * on the bus.
631         */
632
633        for (pin=1; pin<5; pin++) {
634                irq = at697_pci_irq_table[pin-1];
635                pio = at697_pci_irq_pio_table[pin-1];
636                if ( (pio < 16) && (irq >= 4) && (irq <= 7) ) {
637                        /* AT697 I/O IRQ, we know how to set up this
638                         *
639                         * IRQ 4 -> I/O 0
640                         * IRQ 5 -> I/O 1
641                         * IRQ 6 -> I/O 2
642                         * IRQ 7 -> I/O 3
643                         */
644                        ioport = irq - 4;
645
646                        /* First disable interrupts */
647                        regs->PIO_Interrupt &= ~(0xff << (ioport * 8));
648                        /* Set PIO as input pin */
649                        regs->PIO_Direction &= ~(1 << pio);
650                        /* Set Low Level sensitivity */
651                        regs->PIO_Interrupt |= ((0x80 | pio) << (ioport * 8));
652                }
653        }
654
655        /* Unmask Interrupt */
656        /*priv->regs->pciite = 0xff;*/
657
658        return DRVMGR_OK;
659}
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