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source: rtems/c/src/lib/libbsp/sparc/leon2/pci/at697_pci.c @ 05ce8bd5

4.115

Last change on this file since 05ce8bd5 was 05ce8bd5, checked in by Daniel Hellstrom <daniel@…>, on 02/10/15 at 07:32:42
AT697PCI: fix build warnings
Property mode set to `100644`
File size: 18.0 KB

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1	/* LEON2 AT697 PCI Host Driver.
2	*
3	* COPYRIGHT (c) 2008.
4	* Cobham Gaisler AB.
5	*
6	* Configures the AT697 PCI core and initialize,
7	* - the PCI Library (pci.c)
8	* - the general part of the PCI Bus driver (pci_bus.c)
9	*
10	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
11	* default taken from Plug and Play, but may be overridden by the
12	* driver resources INTA#..INTD#.
13	*
14	* The license and distribution terms for this file may be
15	* found in found in the file LICENSE in this distribution or at
16	* http://www.rtems.com/license/LICENSE.
17	*/
18
19	/* Configurable parameters
20	* =======================
21	* INT[A..D]# Select system IRQ (can be tranlated into I/O interrupt)
22	* INT[A..D]#_PIO Select PIO used to generate I/O interrupt
23	*
24	* Notes
25	* =====
26	* IRQ must not be enabled before all PCI boards have been enabled, the
27	* IRQ is therefore enabled first in init2. The init2() for this driver
28	* is assumed to be executed earlier that all boards and their devices
29	* driver's init2() function.
30	*
31	*/
32
33	#include <rtems/bspIo.h>
34	#include <stdlib.h>
35	#include <string.h>
36	#include <stdio.h>
37	#include <libcpu/byteorder.h>
38	#include <libcpu/access.h>
39	#include <pci.h>
40	#include <pci/cfg.h>
41
42	#include <drvmgr/drvmgr.h>
43	#include <drvmgr/pci_bus.h>
44	#include <drvmgr/leon2_amba_bus.h>
45
46	#include <at697_pci.h>
47	#include <leon.h>
48
49	/* Configuration options */
50
51	#define SYSTEM_MAINMEM_START 0x40000000
52	#define SYSTEM_MAINMEM_START2 0x60000000
53
54	/* Interrupt assignment. Set to other value than 0xff in order to
55	* override defaults and plug&play information
56	*/
57	#ifndef AT697_INTA_SYSIRQ
58	#define AT697_INTA_SYSIRQ 0xff
59	#endif
60	#ifndef AT697_INTB_SYSIRQ
61	#define AT697_INTB_SYSIRQ 0xff
62	#endif
63	#ifndef AT697_INTC_SYSIRQ
64	#define AT697_INTC_SYSIRQ 0xff
65	#endif
66	#ifndef AT697_INTD_SYSIRQ
67	#define AT697_INTD_SYSIRQ 0xff
68	#endif
69
70	#ifndef AT697_INTA_PIO
71	#define AT697_INTA_PIO 0xff
72	#endif
73	#ifndef AT697_INTB_PIO
74	#define AT697_INTB_PIO 0xff
75	#endif
76	#ifndef AT697_INTC_PIO
77	#define AT697_INTC_PIO 0xff
78	#endif
79	#ifndef AT697_INTD_PIO
80	#define AT697_INTD_PIO 0xff
81	#endif
82
83
84	/* AT697 PCI */
85	#define AT697_PCI_REG_ADR 0x80000100
86
87	/* PCI Window used */
88	#define PCI_MEM_START 0xa0000000
89	#define PCI_MEM_END 0xf0000000
90	#define PCI_MEM_SIZE (PCI_MEM_END - PCI_MEM_START)
91
92	/* #define DEBUG 1 */
93
94	#ifdef DEBUG
95	#define DBG(x...) printf(x)
96	#else
97	#define DBG(x...)
98	#endif
99
100	#define PCI_INVALID_VENDORDEVICEID 0xffffffff
101	#define PCI_MULTI_FUNCTION 0x80
102
103	struct at697pci_regs {
104	volatile unsigned int pciid1; /* 0x80000100 - PCI Device identification register 1 */
105	volatile unsigned int pcisc; /* 0x80000104 - PCI Status & Command */
106	volatile unsigned int pciid2; /* 0x80000108 - PCI Device identification register 2 */
107	volatile unsigned int pcibhlc; /* 0x8000010c - BIST, Header type, Cache line size register */
108	volatile unsigned int mbar1; /* 0x80000110 - Memory Base Address Register 1 */
109	volatile unsigned int mbar2; /* 0x80000114 - Memory Base Address Register 2 */
110	volatile unsigned int iobar3; /* 0x80000118 - IO Base Address Register 3 */
111	volatile unsigned int dummy1[4]; /* 0x8000011c - 0x80000128 */
112	volatile unsigned int pcisid; /* 0x8000012c - Subsystem identification register */
113	volatile unsigned int dummy2; /* 0x80000130 */
114	volatile unsigned int pcicp; /* 0x80000134 - PCI capabilities pointer register */
115	volatile unsigned int dummy3; /* 0x80000138 */
116	volatile unsigned int pcili; /* 0x8000013c - PCI latency interrupt register */
117	volatile unsigned int pcirt; /* 0x80000140 - PCI retry, trdy config */
118	volatile unsigned int pcicw; /* 0x80000144 - PCI configuration write register */
119	volatile unsigned int pcisa; /* 0x80000148 - PCI Initiator Start Address */
120	volatile unsigned int pciiw; /* 0x8000014c - PCI Initiator Write Register */
121	volatile unsigned int pcidma; /* 0x80000150 - PCI DMA configuration register */
122	volatile unsigned int pciis; /* 0x80000154 - PCI Initiator Status Register */
123	volatile unsigned int pciic; /* 0x80000158 - PCI Initiator Configuration */
124	volatile unsigned int pcitpa; /* 0x8000015c - PCI Target Page Address Register */
125	volatile unsigned int pcitsc; /* 0x80000160 - PCI Target Status-Command Register */
126	volatile unsigned int pciite; /* 0x80000164 - PCI Interrupt Enable Register */
127	volatile unsigned int pciitp; /* 0x80000168 - PCI Interrupt Pending Register */
128	volatile unsigned int pciitf; /* 0x8000016c - PCI Interrupt Force Register */
129	volatile unsigned int pcid; /* 0x80000170 - PCI Data Register */
130	volatile unsigned int pcibe; /* 0x80000174 - PCI Burst End Register */
131	volatile unsigned int pcidmaa; /* 0x80000178 - PCI DMA Address Register */
132	};
133
134	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
135	* to a system interrupt number.
136	*/
137	unsigned char at697_pci_irq_table[4] =
138	{
139	/* INTA# */ AT697_INTA_SYSIRQ,
140	/* INTB# */ AT697_INTB_SYSIRQ,
141	/* INTC# */ AT697_INTC_SYSIRQ,
142	/* INTD# */ AT697_INTD_SYSIRQ
143	};
144
145	/* PCI Interrupt PIO assignment. Selects which GPIO pin will be used to
146	* generate the system IRQ.
147	*
148	* PCI IRQ -> GPIO -> 4 x I/O select -> System IRQ
149	* ^- pio_table ^- irq_select
150	*/
151	unsigned char at697_pci_irq_pio_table[4] =
152	{
153	/* INTA# */ AT697_INTA_PIO,
154	/* INTB# */ AT697_INTB_PIO,
155	/* INTC# */ AT697_INTC_PIO,
156	/* INTD# */ AT697_INTD_PIO
157	};
158
159	/* Driver private data struture */
160	struct at697pci_priv {
161	struct drvmgr_dev *dev;
162	struct at697pci_regs *regs;
163	int minor;
164
165	uint32_t bar1_pci_adr;
166	uint32_t bar2_pci_adr;
167
168	struct drvmgr_map_entry maps_up[3];
169	struct drvmgr_map_entry maps_down[2];
170	struct pcibus_config config;
171	};
172
173	struct at697pci_priv *at697pcipriv = NULL;
174	static int at697pci_minor = 0;
175
176	int at697pci_init1(struct drvmgr_dev *dev);
177	int at697pci_init2(struct drvmgr_dev *dev);
178
179	/* AT697 PCI DRIVER */
180
181	struct drvmgr_drv_ops at697pci_ops =
182	{
183	.init = {at697pci_init1, at697pci_init2, NULL, NULL},
184	.remove = NULL,
185	.info = NULL
186	};
187
188	struct leon2_amba_dev_id at697pci_ids[] =
189	{
190	{LEON2_AMBA_AT697PCI_ID},
191	{0} /* Mark end of table */
192	};
193
194	struct leon2_amba_drv_info at697pci_info =
195	{
196	{
197	DRVMGR_OBJ_DRV, /* Driver */
198	NULL, /* Next driver */
199	NULL, /* Device list */
200	DRIVER_LEON2_AMBA_AT697PCI, /* Driver ID */
201	"AT697PCI_DRV", /* Driver Name */
202	DRVMGR_BUS_TYPE_LEON2_AMBA, /* Bus Type */
203	&at697pci_ops,
204	NULL, /* Funcs */
205	0, /* No devices yet */
206	sizeof(struct at697pci_priv), /* let drvmgr alloc private */
207	},
208	&at697pci_ids[0]
209	};
210
211	void at697pci_register_drv(void)
212	{
213	DBG("Registering AT697 PCI driver\n");
214	drvmgr_drv_register(&at697pci_info.general);
215	}
216
217	/* The configuration access functions uses the DMA functionality of the
218	* AT697 pci controller to be able access all slots
219	*/
220
221	static int at697pci_cfg_r32(pci_dev_t dev, int offset, uint32_t *val)
222	{
223	struct at697pci_regs *regs;
224	volatile unsigned int data = 0;
225	unsigned int address;
226	int bus = PCI_DEV_BUS(dev);
227	int slot = PCI_DEV_SLOT(dev);
228	int func = PCI_DEV_FUNC(dev);
229	int retval;
230
231	if (slot > 15 \|\| (offset & ~0xfc)) {
232	*val = 0xffffffff;
233	return PCISTS_EINVAL;
234	}
235
236	regs = at697pcipriv->regs;
237
238	regs->pciitp = 0xff; /* clear interrupts */
239
240	if ( bus == 0 ) {
241	/* PCI Access - TYPE 0 */
242	address = (1<<(16+slot)) \| (func << 8) \| offset;
243	} else {
244	/* PCI access - TYPE 1 */
245	address = ((bus & 0xff) << 16) \| ((slot & 0x1f) << 11) \|
246	(func << 8) \| offset \| 1;
247	}
248	regs->pcisa = address;
249	regs->pcidma = 0xa01;
250	regs->pcidmaa = (unsigned int) &data;
251
252	while (regs->pciitp == 0)
253	;
254
255	regs->pciitp = 0xff; /* clear interrupts */
256
257	if (regs->pcisc & 0x20000000) { /* Master Abort */
258	regs->pcisc \|= 0x20000000;
259	*val = 0xffffffff;
260	retval = PCISTS_MSTABRT;
261	} else {
262	*val = data;
263	retval = PCISTS_OK;
264	}
265
266	DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
267	bus, slot, func, offset, address, *val);
268
269	return retval;
270	}
271
272	static int at697pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
273	{
274	uint32_t v;
275	int retval;
276
277	if (ofs & 1)
278	return PCISTS_EINVAL;
279
280	retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
281	val = 0xffff & (v >> (8(ofs & 0x3)));
282
283	return retval;
284	}
285
286	static int at697pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
287	{
288	uint32_t v;
289	int retval;
290
291	retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
292
293	val = 0xff & (v >> (8(ofs & 3)));
294
295	return retval;
296	}
297
298	static int at697pci_cfg_w32(pci_dev_t dev, int offset, uint32_t val)
299	{
300	struct at697pci_regs *regs;
301	volatile unsigned int tmp_val = val;
302	unsigned int address;
303	int bus = PCI_DEV_BUS(dev);
304	int slot = PCI_DEV_SLOT(dev);
305	int func = PCI_DEV_FUNC(dev);
306	int retval;
307
308	if (slot > 15 \|\| (offset & ~0xfc))
309	return PCISTS_EINVAL;
310
311	regs = at697pcipriv->regs;
312
313	regs->pciitp = 0xff; /* clear interrupts */
314
315	if ( bus == 0 ) {
316	/* PCI Access - TYPE 0 */
317	address = (1<<(16+slot)) \| (func << 8) \| offset;
318	} else {
319	/* PCI access - TYPE 1 */
320	address = ((bus & 0xff) << 16) \| ((slot & 0x1f) << 11) \|
321	(func << 8) \| offset \| 1;
322	}
323	regs->pcisa = address;
324	regs->pcidma = 0xb01;
325	regs->pcidmaa = (unsigned int) &tmp_val;
326
327	while (regs->pciitp == 0)
328	;
329
330	if (regs->pcisc & 0x20000000) { /* Master Abort */
331	regs->pcisc \|= 0x20000000;
332	retval = PCISTS_MSTABRT;
333	} else
334	retval = PCISTS_OK;
335
336	regs->pciitp = 0xff; /* clear interrupts */
337
338	DBG("pci_write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
339	bus, slot, func, offset, address, val);
340
341	return retval;
342	}
343
344	static int at697pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
345	{
346	uint32_t v;
347	int retval;
348
349	if (ofs & 1)
350	return PCISTS_EINVAL;
351
352	retval = at697pci_cfg_r32(dev, ofs & ~0x3, &v);
353	if (retval != PCISTS_OK)
354	return retval;
355
356	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
357
358	return at697pci_cfg_w32(dev, ofs & ~0x3, v);
359	}
360
361	static int at697pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
362	{
363	uint32_t v;
364
365	at697pci_cfg_r32(dev, ofs & ~0x3, &v);
366
367	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
368
369	return at697pci_cfg_w32(dev, ofs & ~0x3, v);
370	}
371
372	/* Return the assigned system IRQ number that corresponds to the PCI
373	* "Interrupt Pin" information from configuration space.
374	*
375	* The IRQ information is stored in the at697_pci_irq_table configurable
376	* by the user.
377	*
378	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
379	* 0xff if not assigned.
380	*/
381	static uint8_t at697pci_bus0_irq_map(pci_dev_t dev, int irq_pin)
382	{
383	uint8_t sysIrqNr = 0; /* not assigned */
384	int irq_group;
385
386	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
387	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
388	irq_group = PCI_DEV_SLOT(dev) & 0x3;
389	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
390	/* Valid PCI "Interrupt Pin" number */
391	sysIrqNr = at697_pci_irq_table[irq_pin];
392	}
393	return sysIrqNr;
394	}
395
396	static int at697pci_translate(uint32_t *address, int type, int dir)
397	{
398	/* No address translation implmented at this point */
399	return 0;
400	}
401
402	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
403
404	/* AT697 Big-Endian PCI access routines */
405	static struct pci_access_drv at697pci_access_drv = {
406	.cfg =
407	{
408	at697pci_cfg_r8,
409	at697pci_cfg_r16,
410	at697pci_cfg_r32,
411	at697pci_cfg_w8,
412	at697pci_cfg_w16,
413	at697pci_cfg_w32,
414	},
415	.io =
416	{ /* AT697 only supports non-standard Big-Endian PCI Bus */
417	_ld8,
418	_ld_be16,
419	_ld_be32,
420	_st8,
421	_st_be16,
422	_st_be32,
423
424	},
425	.memreg = &pci_memreg_sparc_be_ops,
426	.translate = at697pci_translate,
427	};
428
429	/* Initializes the AT697PCI core hardware
430	*
431	*/
432	static int at697pci_hw_init(struct at697pci_priv *priv)
433	{
434	struct at697pci_regs *regs = priv->regs;
435	unsigned short vendor = regs->pciid1 >> 16;
436
437	/* Must match ATMEL or ESA ID */
438	if ( !((vendor == 0x1202) \|\| (vendor == 0x1E0F)) ) {
439	/* No AT697 PCI, quit */
440	return -1;
441	}
442
443	/* If not in system slot we are not host and we must abort.
444	* This is a host only driver.
445	*/
446	if ((regs->pciis & 0x1000) != 0) {
447	return -1;
448	}
449
450	/* Reset PCI Core */
451	regs->pciic = 0xffffffff;
452
453	/* Mask PCI interrupts */
454	regs->pciite = 0;
455
456	/* Map parts of AT697 main memory into PCI (for DMA) */
457	regs->mbar1 = priv->bar1_pci_adr;
458	regs->mbar2 = priv->bar2_pci_adr;
459	regs->pcitpa = (priv->bar1_pci_adr & 0xff000000) \|
460	((priv->bar2_pci_adr>>16) & 0xff00);
461
462	/* Enable PCI master and target memory command response */
463	regs->pcisc \|= 0x40 \| 0x6;
464
465	/* Set latency timer to 64 */
466	regs->pcibhlc = 0x00004000;
467
468	/* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */
469	regs->pciic = 0x41;
470
471	return 0;
472	}
473
474	/* Initializes the AT697PCI core and driver, must be called before calling init_pci()
475	*
476	* Return values
477	* 0 Successful initalization
478	* -1 Error during initialization.
479	*/
480	static int at697pci_init(struct at697pci_priv *priv)
481	{
482	int pin;
483	union drvmgr_key_value *value;
484	char keyname_sysirq[6];
485	char keyname_pio[10];
486
487	/* PCI core, init private structure */
488	priv->regs = (struct at697pci_regs *) AT697_PCI_REG_ADR;
489
490	/* Init PCI interrupt assignment table to all use the interrupt routed
491	* through the GPIO core.
492	*
493	* INT[A..D]# selects system IRQ (and I/O interrupt)
494	* INT[A..D]#_PIO selects PIO used to generate I/O interrupt
495	*/
496	strcpy(keyname_sysirq, "INTX#");
497	strcpy(keyname_pio, "INTX#_PIO");
498	for (pin=1; pin<5; pin++) {
499	if ( at697_pci_irq_table[pin-1] == 0xff ) {
500	/* User may override hardcoded IRQ setup */
501	keyname_sysirq[3] = 'A' + (pin-1);
502	value = drvmgr_dev_key_get(priv->dev,
503	keyname_sysirq, KEY_TYPE_INT);
504	if ( value )
505	at697_pci_irq_table[pin-1] = value->i;
506	}
507	if ( at697_pci_irq_pio_table[pin-1] == 0xff ) {
508	/* User may override hardcoded IRQ setup */
509	keyname_pio[3] = 'A' + (pin-1);
510	value = drvmgr_dev_key_get(priv->dev,
511	keyname_pio, KEY_TYPE_INT);
512	if ( value )
513	at697_pci_irq_pio_table[pin-1] = value->i;
514	}
515	}
516
517	/* Use GRPCI target BAR1 and BAR2 to map CPU RAM to PCI, this is to
518	* make it possible for PCI peripherals to do DMA directly to CPU memory
519	*
520	* Defualt is to map system RAM at pci address 0x40000000 and system
521	* SDRAM to pci address 0x60000000
522	*/
523	value = drvmgr_dev_key_get(priv->dev, "tgtbar1", KEY_TYPE_INT);
524	if (value)
525	priv->bar1_pci_adr = value->i;
526	else
527	priv->bar1_pci_adr = SYSTEM_MAINMEM_START; /* default */
528
529	value = drvmgr_dev_key_get(priv->dev, "tgtbar2", KEY_TYPE_INT);
530	if (value)
531	priv->bar2_pci_adr = value->i;
532	else
533	priv->bar2_pci_adr = SYSTEM_MAINMEM_START2; /* default */
534
535	/* Init the PCI Core */
536	if ( at697pci_hw_init(priv) ) {
537	return -3;
538	}
539
540	/* Down streams translation table */
541	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
542	priv->maps_down[0].size = 0xF0000000 - 0xA0000000;
543	priv->maps_down[0].from_adr = (void *)0xA0000000;
544	priv->maps_down[0].to_adr = (void *)0xA0000000;
545	/* End table */
546	priv->maps_down[1].size = 0;
547
548	/* Up streams translation table, 2x16Mb mapped 1:1 */
549	priv->maps_up[0].name = "Target BAR0 -> AMBA";
550	priv->maps_up[0].size = 0x01000000; /* 16Mb BAR1 */
551	priv->maps_up[0].from_adr = (void *)priv->bar1_pci_adr;
552	priv->maps_up[0].to_adr = (void *)priv->bar1_pci_adr;
553	priv->maps_up[1].name = "Target BAR1 -> AMBA";
554	priv->maps_up[1].size = 0x01000000; /* 16Mb BAR2 */
555	priv->maps_up[1].from_adr = (void *)priv->bar2_pci_adr;
556	priv->maps_up[1].to_adr = (void *)priv->bar2_pci_adr;
557	/* End table */
558	priv->maps_up[2].size = 0;
559
560	return 0;
561	}
562
563	/* Called when a core is found with the AMBA device and vendor ID
564	* given in at697pci_ids[].
565	*/
566	int at697pci_init1(struct drvmgr_dev *dev)
567	{
568	struct at697pci_priv *priv;
569	struct pci_auto_setup at697pci_auto_cfg;
570
571	DBG("AT697PCI[%d] on bus %s\n", dev->minor_drv,
572	dev->parent->dev->name);
573
574	if ( at697pci_minor != 0 ) {
575	DBG("Driver only supports one PCI core\n");
576	return DRVMGR_FAIL;
577	}
578
579	at697pcipriv = priv = dev->priv;
580	if ( !priv )
581	return DRVMGR_NOMEM;
582
583	priv->dev = dev;
584	priv->minor = at697pci_minor++;
585
586	if (at697pci_init(priv)) {
587	DBG("Failed to initialize at697pci driver\n");
588	return DRVMGR_EIO;
589	}
590
591	/* Host is always Big-Endian */
592	pci_endian = PCI_BIG_ENDIAN;
593
594	if (pci_access_drv_register(&at697pci_access_drv)) {
595	/* Access routines registration failed */
596	return DRVMGR_FAIL;
597	}
598
599	/* Prepare memory MAP */
600	at697pci_auto_cfg.options = 0;
601	at697pci_auto_cfg.mem_start = 0;
602	at697pci_auto_cfg.mem_size = 0;
603	at697pci_auto_cfg.memio_start = PCI_MEM_START;
604	at697pci_auto_cfg.memio_size = PCI_MEM_SIZE;
605	at697pci_auto_cfg.io_start = 0;
606	at697pci_auto_cfg.io_size = 0;
607	at697pci_auto_cfg.irq_map = at697pci_bus0_irq_map;
608	at697pci_auto_cfg.irq_route = NULL; /* use standard routing */
609	pci_config_register(&at697pci_auto_cfg);
610
611	if (pci_config_init()) {
612	/* PCI configuration failed */
613	return DRVMGR_FAIL;
614	}
615
616	priv->config.maps_down = &priv->maps_down[0];
617	priv->config.maps_up = &priv->maps_up[0];
618	return pcibus_register(dev, &priv->config);
619	}
620
621	int at697pci_init2(struct drvmgr_dev *dev)
622	{
623	#if 0
624	struct at697pci_priv *priv = dev->priv;
625	#endif
626	int pin, irq, pio, ioport;
627	LEON_Register_Map regs = (LEON_Register_Map )0x80000000;
628
629	/* Enable interrupts now that init1 has been reached for all devices
630	* on the bus.
631	*/
632
633	for (pin=1; pin<5; pin++) {
634	irq = at697_pci_irq_table[pin-1];
635	pio = at697_pci_irq_pio_table[pin-1];
636	if ( (pio < 16) && (irq >= 4) && (irq <= 7) ) {
637	/* AT697 I/O IRQ, we know how to set up this
638	*
639	* IRQ 4 -> I/O 0
640	* IRQ 5 -> I/O 1
641	* IRQ 6 -> I/O 2
642	* IRQ 7 -> I/O 3
643	*/
644	ioport = irq - 4;
645
646	/* First disable interrupts */
647	regs->PIO_Interrupt &= ~(0xff << (ioport * 8));
648	/* Set PIO as input pin */
649	regs->PIO_Direction &= ~(1 << pio);
650	/* Set Low Level sensitivity */
651	regs->PIO_Interrupt \|= ((0x80 \| pio) << (ioport * 8));
652	}
653	}
654
655	/* Unmask Interrupt */
656	/priv->regs->pciite = 0xff;/
657
658	return DRVMGR_OK;
659	}

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