source: rtems/c/src/lib/libbsp/sparc/leon2/include/leon.h @ c74bd51

Last change on this file since c74bd51 was c74bd51, checked in by Daniel Hellstrom <daniel@…>, on 04/06/12 at 10:05:07

SPARC BSPs: implemented shared-irq using libbsp/shared layer

The implementation use IRQ number instead of vector number since
some IRQs does not have a unique vector, for example the extended
interrupts all enter the same trap vector entry.

Added support for the LEON3 extended interrupt controller when using
the shared IRQ layer.

ERC32 patches untested.

Signed-off-by: Daniel Hellstrom <daniel@…>

Regenerate
  • Property mode set to 100644
File size: 14.4 KB
Line 
1/*  erc32.h
2 *
3 *  This include file contains information pertaining to the LEON-1.
4 *  The LEON-1 is a custom SPARC V7 implementation.
5 *  This CPU has a number of on-board peripherals and
6 *  was developed by the European Space Agency to target space applications.
7 *
8 *  NOTE:  Other than where absolutely required, this version currently
9 *         supports only the peripherals and bits used by the basic board
10 *         support package. This includes at least significant pieces of
11 *         the following items:
12 *
13 *           + UART Channels A and B
14 *           + Real Time Clock
15 *           + Memory Control Register
16 *           + Interrupt Control
17 *
18 *  COPYRIGHT (c) 1989-1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.rtems.com/license/LICENSE.
24 *
25 *  Ported to LEON implementation of the SPARC by On-Line Applications
26 *  Research Corporation (OAR) under contract to the European Space
27 *  Agency (ESA).
28 *
29 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
30 *  European Space Agency.
31 *
32 *  $Id$
33 */
34
35#ifndef _INCLUDE_LEON_h
36#define _INCLUDE_LEON_h
37
38#include <rtems/score/sparc.h>
39
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44/*
45 *  Interrupt Sources
46 *
47 *  The interrupt source numbers directly map to the trap type and to
48 *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
49 *  and the Interrupt Pending Registers.
50 */
51
52#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR  1
53#define LEON_INTERRUPT_UART_2_RX_TX              2
54#define LEON_INTERRUPT_UART_1_RX_TX              3
55#define LEON_INTERRUPT_EXTERNAL_0                4
56#define LEON_INTERRUPT_EXTERNAL_1                5
57#define LEON_INTERRUPT_EXTERNAL_2                6
58#define LEON_INTERRUPT_EXTERNAL_3                7
59#define LEON_INTERRUPT_TIMER1                    8
60#define LEON_INTERRUPT_TIMER2                    9
61#define LEON_INTERRUPT_EMPTY1                    10
62#define LEON_INTERRUPT_EMPTY2                    11
63#define LEON_INTERRUPT_EMPTY3                    12
64#define LEON_INTERRUPT_EMPTY4                    13
65#define LEON_INTERRUPT_EMPTY5                    14
66#define LEON_INTERRUPT_EMPTY6                    15
67
68#ifndef ASM
69
70/*
71 *  Trap Types for on-chip peripherals
72 *
73 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
74 *
75 *  NOTE: The priority level for each source corresponds to the least
76 *        significant nibble of the trap type.
77 */
78
79#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
80
81#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
82
83#define LEON_INT_TRAP( _trap ) \
84  ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \
85    (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) )
86
87/*
88 *  Structure for LEON memory mapped registers.
89 *
90 *  Source: Section 6.1 - On-chip registers
91 *
92 *  NOTE:  There is only one of these structures per CPU, its base address
93 *         is 0x80000000, and the variable LEON_REG is placed there by the
94 *         linkcmds file.
95 */
96
97typedef struct {
98        volatile unsigned int Memory_Config_1;
99        volatile unsigned int Memory_Config_2;
100        volatile unsigned int Edac_Control;
101        volatile unsigned int Failed_Address;
102        volatile unsigned int Memory_Status;
103        volatile unsigned int Cache_Control;
104        volatile unsigned int Power_Down;
105        volatile unsigned int Write_Protection_1;
106        volatile unsigned int Write_Protection_2;
107        volatile unsigned int Leon_Configuration;
108        volatile unsigned int dummy2;
109        volatile unsigned int dummy3;
110        volatile unsigned int dummy4;
111        volatile unsigned int dummy5;
112        volatile unsigned int dummy6;
113        volatile unsigned int dummy7;
114        volatile unsigned int Timer_Counter_1;
115        volatile unsigned int Timer_Reload_1;
116        volatile unsigned int Timer_Control_1;
117        volatile unsigned int Watchdog;
118        volatile unsigned int Timer_Counter_2;
119        volatile unsigned int Timer_Reload_2;
120        volatile unsigned int Timer_Control_2;
121        volatile unsigned int dummy8;
122        volatile unsigned int Scaler_Counter;
123        volatile unsigned int Scaler_Reload;
124        volatile unsigned int dummy9;
125        volatile unsigned int dummy10;
126        volatile unsigned int UART_Channel_1;
127        volatile unsigned int UART_Status_1;
128        volatile unsigned int UART_Control_1;
129        volatile unsigned int UART_Scaler_1;
130        volatile unsigned int UART_Channel_2;
131        volatile unsigned int UART_Status_2;
132        volatile unsigned int UART_Control_2;
133        volatile unsigned int UART_Scaler_2;
134        volatile unsigned int Interrupt_Mask;
135        volatile unsigned int Interrupt_Pending;
136        volatile unsigned int Interrupt_Force;
137        volatile unsigned int Interrupt_Clear;
138        volatile unsigned int PIO_Data;
139        volatile unsigned int PIO_Direction;
140        volatile unsigned int PIO_Interrupt;
141} LEON_Register_Map;
142
143#endif
144
145/*
146 *  The following constants are intended to be used ONLY in assembly
147 *  language files.
148 *
149 *  NOTE:  The intended style of usage is to load the address of LEON REGS
150 *         into a register and then use these as displacements from
151 *         that register.
152 */
153
154#ifdef ASM
155
156#define  LEON_REG_MEMCFG1_OFFSET                                  0x00
157#define  LEON_REG_MEMCFG2_OFFSET                                  0x04
158#define  LEON_REG_EDACCTRL_OFFSET                                 0x08
159#define  LEON_REG_FAILADDR_OFFSET                                 0x0C
160#define  LEON_REG_MEMSTATUS_OFFSET                                0x10
161#define  LEON_REG_CACHECTRL_OFFSET                                0x14
162#define  LEON_REG_POWERDOWN_OFFSET                                0x18
163#define  LEON_REG_WRITEPROT1_OFFSET                               0x1C
164#define  LEON_REG_WRITEPROT2_OFFSET                               0x20
165#define  LEON_REG_LEONCONF_OFFSET                                 0x24
166#define  LEON_REG_UNIMPLEMENTED_2_OFFSET                          0x28
167#define  LEON_REG_UNIMPLEMENTED_3_OFFSET                          0x2C
168#define  LEON_REG_UNIMPLEMENTED_4_OFFSET                          0x30
169#define  LEON_REG_UNIMPLEMENTED_5_OFFSET                          0x34
170#define  LEON_REG_UNIMPLEMENTED_6_OFFSET                          0x38
171#define  LEON_REG_UNIMPLEMENTED_7_OFFSET                          0x3C
172#define  LEON_REG_TIMERCNT1_OFFSET                                0x40
173#define  LEON_REG_TIMERLOAD1_OFFSET                               0x44
174#define  LEON_REG_TIMERCTRL1_OFFSET                               0x48
175#define  LEON_REG_WDOG_OFFSET                                     0x4C
176#define  LEON_REG_TIMERCNT2_OFFSET                                0x50
177#define  LEON_REG_TIMERLOAD2_OFFSET                               0x54
178#define  LEON_REG_TIMERCTRL2_OFFSET                               0x58
179#define  LEON_REG_UNIMPLEMENTED_8_OFFSET                          0x5C
180#define  LEON_REG_SCALERCNT_OFFSET                                0x60
181#define  LEON_REG_SCALER_LOAD_OFFSET                              0x64
182#define  LEON_REG_UNIMPLEMENTED_9_OFFSET                          0x68
183#define  LEON_REG_UNIMPLEMENTED_10_OFFSET                         0x6C
184#define  LEON_REG_UARTDATA1_OFFSET                                0x70
185#define  LEON_REG_UARTSTATUS1_OFFSET                              0x74
186#define  LEON_REG_UARTCTRL1_OFFSET                                0x78
187#define  LEON_REG_UARTSCALER1_OFFSET                              0x7C
188#define  LEON_REG_UARTDATA2_OFFSET                                0x80
189#define  LEON_REG_UARTSTATUS2_OFFSET                              0x84
190#define  LEON_REG_UARTCTRL2_OFFSET                                0x88
191#define  LEON_REG_UARTSCALER2_OFFSET                              0x8C
192#define  LEON_REG_IRQMASK_OFFSET                                  0x90
193#define  LEON_REG_IRQPEND_OFFSET                                  0x94
194#define  LEON_REG_IRQFORCE_OFFSET                                 0x98
195#define  LEON_REG_IRQCLEAR_OFFSET                                 0x9C
196#define  LEON_REG_PIODATA_OFFSET                                  0xA0
197#define  LEON_REG_PIODIR_OFFSET                                   0xA4
198#define  LEON_REG_PIOIRQ_OFFSET                                   0xA8
199#define  LEON_REG_SIM_RAM_SIZE_OFFSET                             0xF4
200#define  LEON_REG_SIM_ROM_SIZE_OFFSET                             0xF8
201
202#endif
203
204/*
205 *  The following defines the bits in Memory Configuration Register 1.
206 */
207
208#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x0003C000
209
210/*
211 *  The following defines the bits in Memory Configuration Register 1.
212 */
213
214#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
215
216
217/*
218 *  The following defines the bits in the Timer Control Register.
219 */
220
221#define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
222                                                 /* 0 = hold scalar and counter */
223#define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
224                                                 /* 0 = stop at 0 */
225#define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
226                                                 /* 0 = no function */
227
228/*
229 *  The following defines the bits in the UART Control Registers.
230 *
231 */
232
233#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
234
235/*
236 *  The following defines the bits in the LEON UART Status Registers.
237 */
238
239#define LEON_REG_UART_STATUS_CLR  0x00000000 /* Clear all status bits */
240#define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
241#define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
242#define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
243#define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
244#define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
245#define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
246#define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
247#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
248
249
250/*
251 *  The following defines the bits in the LEON UART Status Registers.
252 */
253
254#define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
255#define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
256#define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
257#define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
258#define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
259#define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
260#define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
261#define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
262
263#ifndef ASM
264
265/*
266 *  This is used to manipulate the on-chip registers.
267 *
268 *  The following symbol must be defined in the linkcmds file and point
269 *  to the correct location.
270 */
271
272extern LEON_Register_Map LEON_REG;
273
274static __inline__ int bsp_irq_fixup(int irq)
275{
276       return irq;
277}
278
279/*
280 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
281 *  and the Interrupt Pending Registers.
282 *
283 *  NOTE: For operations which are not atomic, this code disables interrupts
284 *        to guarantee there are no intervening accesses to the same register.
285 *        The operations which read the register, modify the value and then
286 *        store the result back are vulnerable.
287 */
288
289#define LEON_Clear_interrupt( _source ) \
290  do { \
291    LEON_REG.Interrupt_Clear = (1 << (_source)); \
292  } while (0)
293
294#define LEON_Force_interrupt( _source ) \
295  do { \
296    LEON_REG.Interrupt_Force = (1 << (_source)); \
297  } while (0)
298
299#define LEON_Is_interrupt_pending( _source ) \
300  (LEON_REG.Interrupt_Pending & (1 << (_source)))
301
302#define LEON_Is_interrupt_masked( _source ) \
303  (LEON_REG.Interrupt_Masked & (1 << (_source)))
304
305#define LEON_Mask_interrupt( _source ) \
306  do { \
307    uint32_t _level; \
308    \
309    _level = sparc_disable_interrupts(); \
310      LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
311    sparc_enable_interrupts( _level ); \
312  } while (0)
313
314#define LEON_Unmask_interrupt( _source ) \
315  do { \
316    uint32_t _level; \
317    \
318    _level = sparc_disable_interrupts(); \
319      LEON_REG.Interrupt_Mask |= (1 << (_source)); \
320    sparc_enable_interrupts( _level ); \
321  } while (0)
322
323#define LEON_Disable_interrupt( _source, _previous ) \
324  do { \
325    uint32_t _level; \
326    uint32_t _mask = 1 << (_source); \
327    \
328    _level = sparc_disable_interrupts(); \
329      (_previous) = LEON_REG.Interrupt_Mask; \
330      LEON_REG.Interrupt_Mask = _previous & ~_mask; \
331    sparc_enable_interrupts( _level ); \
332    (_previous) &= _mask; \
333  } while (0)
334
335#define LEON_Restore_interrupt( _source, _previous ) \
336  do { \
337    uint32_t _level; \
338    uint32_t _mask = 1 << (_source); \
339    \
340    _level = sparc_disable_interrupts(); \
341      LEON_REG.Interrupt_Mask = \
342        (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \
343    sparc_enable_interrupts( _level ); \
344  } while (0)
345
346/* Make all SPARC BSPs have common macros for interrupt handling */
347#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
348#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
349#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
350#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
351#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
352#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
353#define BSP_Disable_interrupt(_source, _previous) \
354        LEON_Disable_interrupt(_source, _prev)
355#define BSP_Restore_interrupt(_source, _previous) \
356        LEON_Restore_interrupt(_source, _previous)
357
358/*
359 *  Each timer control register is organized as follows:
360 *
361 *    D0 - Enable
362 *          1 = enable counting
363 *          0 = hold scaler and counter
364 *
365 *    D1 - Counter Reload
366 *          1 = reload counter at zero and restart
367 *          0 = stop counter at zero
368 *
369 *    D2 - Counter Load
370 *          1 = load counter with preset value
371 *          0 = no function
372 *
373 */
374
375#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000002
376#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
377
378#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER       0x00000004
379
380#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING    0x00000001
381#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
382
383#define LEON_REG_TIMER_COUNTER_RELOAD_MASK        0x00000002
384#define LEON_REG_TIMER_COUNTER_ENABLE_MASK        0x00000001
385
386#define LEON_REG_TIMER_COUNTER_DEFINED_MASK       0x00000003
387#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000003
388
389/* Load 32-bit word by forcing a cache-miss */
390static inline unsigned int leon_r32_no_cache(uintptr_t addr)
391{
392        unsigned int tmp;
393        asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr));
394        return tmp;
395}
396
397#endif /* !ASM */
398
399#ifdef __cplusplus
400}
401#endif
402
403#endif /* !_INCLUDE_LEON_h */
404
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