source: rtems/c/src/lib/libbsp/sparc/leon2/include/leon.h @ aaaedba

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1/*  erc32.h
2 *
3 *  This include file contains information pertaining to the LEON-1.
4 *  The LEON-1 is a custom SPARC V7 implementation.
5 *  This CPU has a number of on-board peripherals and
6 *  was developed by the European Space Agency to target space applications.
7 *
8 *  NOTE:  Other than where absolutely required, this version currently
9 *         supports only the peripherals and bits used by the basic board
10 *         support package. This includes at least significant pieces of
11 *         the following items:
12 *
13 *           + UART Channels A and B
14 *           + Real Time Clock
15 *           + Memory Control Register
16 *           + Interrupt Control
17 *
18 *  COPYRIGHT (c) 1989-1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *
21 *  The license and distribution terms for this file may be
22 *  found in the file LICENSE in this distribution or at
23 *  http://www.rtems.com/license/LICENSE.
24 *
25 *  Ported to LEON implementation of the SPARC by On-Line Applications
26 *  Research Corporation (OAR) under contract to the European Space
27 *  Agency (ESA).
28 *
29 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
30 *  European Space Agency.
31 */
32
33#ifndef _INCLUDE_LEON_h
34#define _INCLUDE_LEON_h
35
36#include <rtems/score/sparc.h>
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42/*
43 *  Interrupt Sources
44 *
45 *  The interrupt source numbers directly map to the trap type and to
46 *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
47 *  and the Interrupt Pending Registers.
48 */
49
50#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR  1
51#define LEON_INTERRUPT_UART_2_RX_TX              2
52#define LEON_INTERRUPT_UART_1_RX_TX              3
53#define LEON_INTERRUPT_EXTERNAL_0                4
54#define LEON_INTERRUPT_EXTERNAL_1                5
55#define LEON_INTERRUPT_EXTERNAL_2                6
56#define LEON_INTERRUPT_EXTERNAL_3                7
57#define LEON_INTERRUPT_TIMER1                    8
58#define LEON_INTERRUPT_TIMER2                    9
59#define LEON_INTERRUPT_EMPTY1                    10
60#define LEON_INTERRUPT_EMPTY2                    11
61#define LEON_INTERRUPT_EMPTY3                    12
62#define LEON_INTERRUPT_EMPTY4                    13
63#define LEON_INTERRUPT_EMPTY5                    14
64#define LEON_INTERRUPT_EMPTY6                    15
65
66#ifndef ASM
67
68/*
69 *  Trap Types for on-chip peripherals
70 *
71 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
72 *
73 *  NOTE: The priority level for each source corresponds to the least
74 *        significant nibble of the trap type.
75 */
76
77#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
78
79#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
80
81#define LEON_INT_TRAP( _trap ) \
82  ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \
83    (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) )
84
85/*
86 *  Structure for LEON memory mapped registers.
87 *
88 *  Source: Section 6.1 - On-chip registers
89 *
90 *  NOTE:  There is only one of these structures per CPU, its base address
91 *         is 0x80000000, and the variable LEON_REG is placed there by the
92 *         linkcmds file.
93 */
94
95typedef struct {
96        volatile unsigned int Memory_Config_1;
97        volatile unsigned int Memory_Config_2;
98        volatile unsigned int Edac_Control;
99        volatile unsigned int Failed_Address;
100        volatile unsigned int Memory_Status;
101        volatile unsigned int Cache_Control;
102        volatile unsigned int Power_Down;
103        volatile unsigned int Write_Protection_1;
104        volatile unsigned int Write_Protection_2;
105        volatile unsigned int Leon_Configuration;
106        volatile unsigned int dummy2;
107        volatile unsigned int dummy3;
108        volatile unsigned int dummy4;
109        volatile unsigned int dummy5;
110        volatile unsigned int dummy6;
111        volatile unsigned int dummy7;
112        volatile unsigned int Timer_Counter_1;
113        volatile unsigned int Timer_Reload_1;
114        volatile unsigned int Timer_Control_1;
115        volatile unsigned int Watchdog;
116        volatile unsigned int Timer_Counter_2;
117        volatile unsigned int Timer_Reload_2;
118        volatile unsigned int Timer_Control_2;
119        volatile unsigned int dummy8;
120        volatile unsigned int Scaler_Counter;
121        volatile unsigned int Scaler_Reload;
122        volatile unsigned int dummy9;
123        volatile unsigned int dummy10;
124        volatile unsigned int UART_Channel_1;
125        volatile unsigned int UART_Status_1;
126        volatile unsigned int UART_Control_1;
127        volatile unsigned int UART_Scaler_1;
128        volatile unsigned int UART_Channel_2;
129        volatile unsigned int UART_Status_2;
130        volatile unsigned int UART_Control_2;
131        volatile unsigned int UART_Scaler_2;
132        volatile unsigned int Interrupt_Mask;
133        volatile unsigned int Interrupt_Pending;
134        volatile unsigned int Interrupt_Force;
135        volatile unsigned int Interrupt_Clear;
136        volatile unsigned int PIO_Data;
137        volatile unsigned int PIO_Direction;
138        volatile unsigned int PIO_Interrupt;
139} LEON_Register_Map;
140
141#endif
142
143/*
144 *  The following constants are intended to be used ONLY in assembly
145 *  language files.
146 *
147 *  NOTE:  The intended style of usage is to load the address of LEON REGS
148 *         into a register and then use these as displacements from
149 *         that register.
150 */
151
152#ifdef ASM
153
154#define  LEON_REG_MEMCFG1_OFFSET                                  0x00
155#define  LEON_REG_MEMCFG2_OFFSET                                  0x04
156#define  LEON_REG_EDACCTRL_OFFSET                                 0x08
157#define  LEON_REG_FAILADDR_OFFSET                                 0x0C
158#define  LEON_REG_MEMSTATUS_OFFSET                                0x10
159#define  LEON_REG_CACHECTRL_OFFSET                                0x14
160#define  LEON_REG_POWERDOWN_OFFSET                                0x18
161#define  LEON_REG_WRITEPROT1_OFFSET                               0x1C
162#define  LEON_REG_WRITEPROT2_OFFSET                               0x20
163#define  LEON_REG_LEONCONF_OFFSET                                 0x24
164#define  LEON_REG_UNIMPLEMENTED_2_OFFSET                          0x28
165#define  LEON_REG_UNIMPLEMENTED_3_OFFSET                          0x2C
166#define  LEON_REG_UNIMPLEMENTED_4_OFFSET                          0x30
167#define  LEON_REG_UNIMPLEMENTED_5_OFFSET                          0x34
168#define  LEON_REG_UNIMPLEMENTED_6_OFFSET                          0x38
169#define  LEON_REG_UNIMPLEMENTED_7_OFFSET                          0x3C
170#define  LEON_REG_TIMERCNT1_OFFSET                                0x40
171#define  LEON_REG_TIMERLOAD1_OFFSET                               0x44
172#define  LEON_REG_TIMERCTRL1_OFFSET                               0x48
173#define  LEON_REG_WDOG_OFFSET                                     0x4C
174#define  LEON_REG_TIMERCNT2_OFFSET                                0x50
175#define  LEON_REG_TIMERLOAD2_OFFSET                               0x54
176#define  LEON_REG_TIMERCTRL2_OFFSET                               0x58
177#define  LEON_REG_UNIMPLEMENTED_8_OFFSET                          0x5C
178#define  LEON_REG_SCALERCNT_OFFSET                                0x60
179#define  LEON_REG_SCALER_LOAD_OFFSET                              0x64
180#define  LEON_REG_UNIMPLEMENTED_9_OFFSET                          0x68
181#define  LEON_REG_UNIMPLEMENTED_10_OFFSET                         0x6C
182#define  LEON_REG_UARTDATA1_OFFSET                                0x70
183#define  LEON_REG_UARTSTATUS1_OFFSET                              0x74
184#define  LEON_REG_UARTCTRL1_OFFSET                                0x78
185#define  LEON_REG_UARTSCALER1_OFFSET                              0x7C
186#define  LEON_REG_UARTDATA2_OFFSET                                0x80
187#define  LEON_REG_UARTSTATUS2_OFFSET                              0x84
188#define  LEON_REG_UARTCTRL2_OFFSET                                0x88
189#define  LEON_REG_UARTSCALER2_OFFSET                              0x8C
190#define  LEON_REG_IRQMASK_OFFSET                                  0x90
191#define  LEON_REG_IRQPEND_OFFSET                                  0x94
192#define  LEON_REG_IRQFORCE_OFFSET                                 0x98
193#define  LEON_REG_IRQCLEAR_OFFSET                                 0x9C
194#define  LEON_REG_PIODATA_OFFSET                                  0xA0
195#define  LEON_REG_PIODIR_OFFSET                                   0xA4
196#define  LEON_REG_PIOIRQ_OFFSET                                   0xA8
197#define  LEON_REG_SIM_RAM_SIZE_OFFSET                             0xF4
198#define  LEON_REG_SIM_ROM_SIZE_OFFSET                             0xF8
199
200#endif
201
202/*
203 *  The following defines the bits in Memory Configuration Register 1.
204 */
205
206#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x0003C000
207
208/*
209 *  The following defines the bits in Memory Configuration Register 1.
210 */
211
212#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
213
214
215/*
216 *  The following defines the bits in the Timer Control Register.
217 */
218
219#define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
220                                                 /* 0 = hold scalar and counter */
221#define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
222                                                 /* 0 = stop at 0 */
223#define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
224                                                 /* 0 = no function */
225
226/*
227 *  The following defines the bits in the UART Control Registers.
228 *
229 */
230
231#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
232
233/*
234 *  The following defines the bits in the LEON UART Status Registers.
235 */
236
237#define LEON_REG_UART_STATUS_CLR  0x00000000 /* Clear all status bits */
238#define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
239#define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
240#define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
241#define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
242#define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
243#define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
244#define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
245#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
246
247
248/*
249 *  The following defines the bits in the LEON UART Status Registers.
250 */
251
252#define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
253#define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
254#define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
255#define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
256#define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
257#define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
258#define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
259#define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
260
261#ifndef ASM
262
263/*
264 *  This is used to manipulate the on-chip registers.
265 *
266 *  The following symbol must be defined in the linkcmds file and point
267 *  to the correct location.
268 */
269
270extern LEON_Register_Map LEON_REG;
271
272static __inline__ int bsp_irq_fixup(int irq)
273{
274       return irq;
275}
276
277/*
278 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
279 *  and the Interrupt Pending Registers.
280 *
281 *  NOTE: For operations which are not atomic, this code disables interrupts
282 *        to guarantee there are no intervening accesses to the same register.
283 *        The operations which read the register, modify the value and then
284 *        store the result back are vulnerable.
285 */
286
287#define LEON_Clear_interrupt( _source ) \
288  do { \
289    LEON_REG.Interrupt_Clear = (1 << (_source)); \
290  } while (0)
291
292#define LEON_Force_interrupt( _source ) \
293  do { \
294    LEON_REG.Interrupt_Force = (1 << (_source)); \
295  } while (0)
296
297#define LEON_Is_interrupt_pending( _source ) \
298  (LEON_REG.Interrupt_Pending & (1 << (_source)))
299
300#define LEON_Is_interrupt_masked( _source ) \
301  (LEON_REG.Interrupt_Masked & (1 << (_source)))
302
303#define LEON_Mask_interrupt( _source ) \
304  do { \
305    uint32_t _level; \
306    \
307    _level = sparc_disable_interrupts(); \
308      LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
309    sparc_enable_interrupts( _level ); \
310  } while (0)
311
312#define LEON_Unmask_interrupt( _source ) \
313  do { \
314    uint32_t _level; \
315    \
316    _level = sparc_disable_interrupts(); \
317      LEON_REG.Interrupt_Mask |= (1 << (_source)); \
318    sparc_enable_interrupts( _level ); \
319  } while (0)
320
321#define LEON_Disable_interrupt( _source, _previous ) \
322  do { \
323    uint32_t _level; \
324    uint32_t _mask = 1 << (_source); \
325    \
326    _level = sparc_disable_interrupts(); \
327      (_previous) = LEON_REG.Interrupt_Mask; \
328      LEON_REG.Interrupt_Mask = _previous & ~_mask; \
329    sparc_enable_interrupts( _level ); \
330    (_previous) &= _mask; \
331  } while (0)
332
333#define LEON_Restore_interrupt( _source, _previous ) \
334  do { \
335    uint32_t _level; \
336    uint32_t _mask = 1 << (_source); \
337    \
338    _level = sparc_disable_interrupts(); \
339      LEON_REG.Interrupt_Mask = \
340        (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \
341    sparc_enable_interrupts( _level ); \
342  } while (0)
343
344/* Make all SPARC BSPs have common macros for interrupt handling */
345#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
346#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
347#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
348#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
349#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
350#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
351#define BSP_Disable_interrupt(_source, _previous) \
352        LEON_Disable_interrupt(_source, _prev)
353#define BSP_Restore_interrupt(_source, _previous) \
354        LEON_Restore_interrupt(_source, _previous)
355
356/*
357 *  Each timer control register is organized as follows:
358 *
359 *    D0 - Enable
360 *          1 = enable counting
361 *          0 = hold scaler and counter
362 *
363 *    D1 - Counter Reload
364 *          1 = reload counter at zero and restart
365 *          0 = stop counter at zero
366 *
367 *    D2 - Counter Load
368 *          1 = load counter with preset value
369 *          0 = no function
370 *
371 */
372
373#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000002
374#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
375
376#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER       0x00000004
377
378#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING    0x00000001
379#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
380
381#define LEON_REG_TIMER_COUNTER_RELOAD_MASK        0x00000002
382#define LEON_REG_TIMER_COUNTER_ENABLE_MASK        0x00000001
383
384#define LEON_REG_TIMER_COUNTER_DEFINED_MASK       0x00000003
385#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000003
386
387/* Load 32-bit word by forcing a cache-miss */
388static inline unsigned int leon_r32_no_cache(uintptr_t addr)
389{
390        unsigned int tmp;
391        asm volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr));
392        return tmp;
393}
394
395#endif /* !ASM */
396
397#ifdef __cplusplus
398}
399#endif
400
401#endif /* !_INCLUDE_LEON_h */
402
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