1 | /* erc32.h |
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2 | * |
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3 | * This include file contains information pertaining to the LEON-1. |
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4 | * The LEON-1 is a custom SPARC V7 implementation. |
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5 | * This CPU has a number of on-board peripherals and |
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6 | * was developed by the European Space Agency to target space applications. |
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7 | * |
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8 | * NOTE: Other than where absolutely required, this version currently |
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9 | * supports only the peripherals and bits used by the basic board |
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10 | * support package. This includes at least significant pieces of |
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11 | * the following items: |
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12 | * |
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13 | * + UART Channels A and B |
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14 | * + Real Time Clock |
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15 | * + Memory Control Register |
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16 | * + Interrupt Control |
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17 | * |
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18 | * COPYRIGHT (c) 1989-1998. |
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19 | * On-Line Applications Research Corporation (OAR). |
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20 | * |
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21 | * The license and distribution terms for this file may be |
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22 | * found in the file LICENSE in this distribution or at |
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23 | * http://www.rtems.com/license/LICENSE. |
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24 | * |
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25 | * Ported to LEON implementation of the SPARC by On-Line Applications |
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26 | * Research Corporation (OAR) under contract to the European Space |
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27 | * Agency (ESA). |
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28 | * |
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29 | * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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30 | * European Space Agency. |
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31 | * |
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32 | * $Id$ |
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33 | */ |
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34 | |
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35 | #ifndef _INCLUDE_LEON_h |
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36 | #define _INCLUDE_LEON_h |
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37 | |
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38 | #include <rtems/score/sparc.h> |
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39 | |
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40 | #ifdef __cplusplus |
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41 | extern "C" { |
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42 | #endif |
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43 | |
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44 | /* |
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45 | * Interrupt Sources |
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46 | * |
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47 | * The interrupt source numbers directly map to the trap type and to |
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48 | * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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49 | * and the Interrupt Pending Registers. |
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50 | */ |
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51 | |
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52 | #define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 |
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53 | #define LEON_INTERRUPT_UART_2_RX_TX 2 |
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54 | #define LEON_INTERRUPT_UART_1_RX_TX 3 |
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55 | #define LEON_INTERRUPT_EXTERNAL_0 4 |
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56 | #define LEON_INTERRUPT_EXTERNAL_1 5 |
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57 | #define LEON_INTERRUPT_EXTERNAL_2 6 |
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58 | #define LEON_INTERRUPT_EXTERNAL_3 7 |
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59 | #define LEON_INTERRUPT_TIMER1 8 |
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60 | #define LEON_INTERRUPT_TIMER2 9 |
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61 | #define LEON_INTERRUPT_EMPTY1 10 |
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62 | #define LEON_INTERRUPT_EMPTY2 11 |
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63 | #define LEON_INTERRUPT_EMPTY3 12 |
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64 | #define LEON_INTERRUPT_EMPTY4 13 |
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65 | #define LEON_INTERRUPT_EMPTY5 14 |
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66 | #define LEON_INTERRUPT_EMPTY6 15 |
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67 | |
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68 | #ifndef ASM |
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69 | |
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70 | /* |
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71 | * Trap Types for on-chip peripherals |
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72 | * |
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73 | * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments |
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74 | * |
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75 | * NOTE: The priority level for each source corresponds to the least |
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76 | * significant nibble of the trap type. |
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77 | */ |
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78 | |
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79 | #define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10) |
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80 | |
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81 | #define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10) |
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82 | |
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83 | #define LEON_INT_TRAP( _trap ) \ |
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84 | ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \ |
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85 | (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) ) |
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86 | |
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87 | /* |
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88 | * Structure for LEON memory mapped registers. |
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89 | * |
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90 | * Source: Section 6.1 - On-chip registers |
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91 | * |
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92 | * NOTE: There is only one of these structures per CPU, its base address |
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93 | * is 0x80000000, and the variable LEON_REG is placed there by the |
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94 | * linkcmds file. |
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95 | */ |
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96 | |
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97 | typedef struct { |
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98 | volatile unsigned int Memory_Config_1; |
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99 | volatile unsigned int Memory_Config_2; |
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100 | volatile unsigned int Edac_Control; |
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101 | volatile unsigned int Failed_Address; |
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102 | volatile unsigned int Memory_Status; |
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103 | volatile unsigned int Cache_Control; |
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104 | volatile unsigned int Power_Down; |
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105 | volatile unsigned int Write_Protection_1; |
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106 | volatile unsigned int Write_Protection_2; |
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107 | volatile unsigned int Leon_Configuration; |
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108 | volatile unsigned int dummy2; |
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109 | volatile unsigned int dummy3; |
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110 | volatile unsigned int dummy4; |
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111 | volatile unsigned int dummy5; |
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112 | volatile unsigned int dummy6; |
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113 | volatile unsigned int dummy7; |
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114 | volatile unsigned int Timer_Counter_1; |
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115 | volatile unsigned int Timer_Reload_1; |
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116 | volatile unsigned int Timer_Control_1; |
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117 | volatile unsigned int Watchdog; |
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118 | volatile unsigned int Timer_Counter_2; |
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119 | volatile unsigned int Timer_Reload_2; |
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120 | volatile unsigned int Timer_Control_2; |
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121 | volatile unsigned int dummy8; |
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122 | volatile unsigned int Scaler_Counter; |
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123 | volatile unsigned int Scaler_Reload; |
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124 | volatile unsigned int dummy9; |
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125 | volatile unsigned int dummy10; |
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126 | volatile unsigned int UART_Channel_1; |
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127 | volatile unsigned int UART_Status_1; |
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128 | volatile unsigned int UART_Control_1; |
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129 | volatile unsigned int UART_Scaler_1; |
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130 | volatile unsigned int UART_Channel_2; |
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131 | volatile unsigned int UART_Status_2; |
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132 | volatile unsigned int UART_Control_2; |
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133 | volatile unsigned int UART_Scaler_2; |
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134 | volatile unsigned int Interrupt_Mask; |
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135 | volatile unsigned int Interrupt_Pending; |
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136 | volatile unsigned int Interrupt_Force; |
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137 | volatile unsigned int Interrupt_Clear; |
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138 | volatile unsigned int PIO_Data; |
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139 | volatile unsigned int PIO_Direction; |
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140 | volatile unsigned int PIO_Interrupt; |
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141 | } LEON_Register_Map; |
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142 | |
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143 | #endif |
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144 | |
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145 | /* |
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146 | * The following constants are intended to be used ONLY in assembly |
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147 | * language files. |
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148 | * |
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149 | * NOTE: The intended style of usage is to load the address of LEON REGS |
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150 | * into a register and then use these as displacements from |
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151 | * that register. |
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152 | */ |
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153 | |
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154 | #ifdef ASM |
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155 | |
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156 | #define LEON_REG_MEMCFG1_OFFSET 0x00 |
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157 | #define LEON_REG_MEMCFG2_OFFSET 0x04 |
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158 | #define LEON_REG_EDACCTRL_OFFSET 0x08 |
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159 | #define LEON_REG_FAILADDR_OFFSET 0x0C |
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160 | #define LEON_REG_MEMSTATUS_OFFSET 0x10 |
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161 | #define LEON_REG_CACHECTRL_OFFSET 0x14 |
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162 | #define LEON_REG_POWERDOWN_OFFSET 0x18 |
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163 | #define LEON_REG_WRITEPROT1_OFFSET 0x1C |
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164 | #define LEON_REG_WRITEPROT2_OFFSET 0x20 |
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165 | #define LEON_REG_LEONCONF_OFFSET 0x24 |
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166 | #define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28 |
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167 | #define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C |
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168 | #define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30 |
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169 | #define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34 |
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170 | #define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38 |
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171 | #define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C |
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172 | #define LEON_REG_TIMERCNT1_OFFSET 0x40 |
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173 | #define LEON_REG_TIMERLOAD1_OFFSET 0x44 |
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174 | #define LEON_REG_TIMERCTRL1_OFFSET 0x48 |
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175 | #define LEON_REG_WDOG_OFFSET 0x4C |
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176 | #define LEON_REG_TIMERCNT2_OFFSET 0x50 |
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177 | #define LEON_REG_TIMERLOAD2_OFFSET 0x54 |
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178 | #define LEON_REG_TIMERCTRL2_OFFSET 0x58 |
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179 | #define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C |
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180 | #define LEON_REG_SCALERCNT_OFFSET 0x60 |
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181 | #define LEON_REG_SCALER_LOAD_OFFSET 0x64 |
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182 | #define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68 |
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183 | #define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C |
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184 | #define LEON_REG_UARTDATA1_OFFSET 0x70 |
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185 | #define LEON_REG_UARTSTATUS1_OFFSET 0x74 |
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186 | #define LEON_REG_UARTCTRL1_OFFSET 0x78 |
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187 | #define LEON_REG_UARTSCALER1_OFFSET 0x7C |
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188 | #define LEON_REG_UARTDATA2_OFFSET 0x80 |
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189 | #define LEON_REG_UARTSTATUS2_OFFSET 0x84 |
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190 | #define LEON_REG_UARTCTRL2_OFFSET 0x88 |
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191 | #define LEON_REG_UARTSCALER2_OFFSET 0x8C |
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192 | #define LEON_REG_IRQMASK_OFFSET 0x90 |
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193 | #define LEON_REG_IRQPEND_OFFSET 0x94 |
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194 | #define LEON_REG_IRQFORCE_OFFSET 0x98 |
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195 | #define LEON_REG_IRQCLEAR_OFFSET 0x9C |
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196 | #define LEON_REG_PIODATA_OFFSET 0xA0 |
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197 | #define LEON_REG_PIODIR_OFFSET 0xA4 |
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198 | #define LEON_REG_PIOIRQ_OFFSET 0xA8 |
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199 | #define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4 |
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200 | #define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8 |
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201 | |
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202 | #endif |
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203 | |
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204 | /* |
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205 | * The following defines the bits in Memory Configuration Register 1. |
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206 | */ |
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207 | |
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208 | #define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 |
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209 | |
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210 | /* |
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211 | * The following defines the bits in Memory Configuration Register 1. |
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212 | */ |
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213 | |
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214 | #define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 |
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215 | |
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216 | |
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217 | /* |
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218 | * The following defines the bits in the Timer Control Register. |
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219 | */ |
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220 | |
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221 | #define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ |
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222 | /* 0 = hold scalar and counter */ |
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223 | #define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ |
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224 | /* 0 = stop at 0 */ |
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225 | #define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ |
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226 | /* 0 = no function */ |
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227 | |
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228 | /* |
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229 | * The following defines the bits in the UART Control Registers. |
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230 | * |
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231 | */ |
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232 | |
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233 | #define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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234 | |
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235 | /* |
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236 | * The following defines the bits in the LEON UART Status Registers. |
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237 | */ |
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238 | |
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239 | #define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */ |
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240 | #define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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241 | #define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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242 | #define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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243 | #define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ |
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244 | #define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ |
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245 | #define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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246 | #define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ |
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247 | #define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ |
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248 | |
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249 | |
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250 | /* |
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251 | * The following defines the bits in the LEON UART Status Registers. |
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252 | */ |
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253 | |
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254 | #define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ |
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255 | #define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ |
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256 | #define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ |
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257 | #define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ |
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258 | #define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ |
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259 | #define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ |
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260 | #define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ |
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261 | #define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ |
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262 | |
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263 | #ifndef ASM |
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264 | |
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265 | /* |
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266 | * This is used to manipulate the on-chip registers. |
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267 | * |
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268 | * The following symbol must be defined in the linkcmds file and point |
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269 | * to the correct location. |
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270 | */ |
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271 | |
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272 | extern LEON_Register_Map LEON_REG; |
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273 | |
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274 | /* |
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275 | * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask, |
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276 | * and the Interrupt Pending Registers. |
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277 | * |
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278 | * NOTE: For operations which are not atomic, this code disables interrupts |
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279 | * to guarantee there are no intervening accesses to the same register. |
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280 | * The operations which read the register, modify the value and then |
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281 | * store the result back are vulnerable. |
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282 | */ |
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283 | |
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284 | #define LEON_Clear_interrupt( _source ) \ |
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285 | do { \ |
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286 | LEON_REG.Interrupt_Clear = (1 << (_source)); \ |
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287 | } while (0) |
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288 | |
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289 | #define LEON_Force_interrupt( _source ) \ |
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290 | do { \ |
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291 | LEON_REG.Interrupt_Force = (1 << (_source)); \ |
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292 | } while (0) |
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293 | |
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294 | #define LEON_Is_interrupt_pending( _source ) \ |
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295 | (LEON_REG.Interrupt_Pending & (1 << (_source))) |
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296 | |
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297 | #define LEON_Is_interrupt_masked( _source ) \ |
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298 | (LEON_REG.Interrupt_Masked & (1 << (_source))) |
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299 | |
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300 | #define LEON_Mask_interrupt( _source ) \ |
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301 | do { \ |
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302 | uint32_t _level; \ |
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303 | \ |
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304 | _level = sparc_disable_interrupts(); \ |
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305 | LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \ |
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306 | sparc_enable_interrupts( _level ); \ |
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307 | } while (0) |
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308 | |
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309 | #define LEON_Unmask_interrupt( _source ) \ |
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310 | do { \ |
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311 | uint32_t _level; \ |
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312 | \ |
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313 | _level = sparc_disable_interrupts(); \ |
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314 | LEON_REG.Interrupt_Mask |= (1 << (_source)); \ |
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315 | sparc_enable_interrupts( _level ); \ |
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316 | } while (0) |
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317 | |
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318 | #define LEON_Disable_interrupt( _source, _previous ) \ |
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319 | do { \ |
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320 | uint32_t _level; \ |
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321 | uint32_t _mask = 1 << (_source); \ |
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322 | \ |
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323 | _level = sparc_disable_interrupts(); \ |
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324 | (_previous) = LEON_REG.Interrupt_Mask; \ |
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325 | LEON_REG.Interrupt_Mask = _previous & ~_mask; \ |
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326 | sparc_enable_interrupts( _level ); \ |
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327 | (_previous) &= _mask; \ |
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328 | } while (0) |
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329 | |
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330 | #define LEON_Restore_interrupt( _source, _previous ) \ |
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331 | do { \ |
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332 | uint32_t _level; \ |
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333 | uint32_t _mask = 1 << (_source); \ |
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334 | \ |
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335 | _level = sparc_disable_interrupts(); \ |
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336 | LEON_REG.Interrupt_Mask = \ |
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337 | (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \ |
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338 | sparc_enable_interrupts( _level ); \ |
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339 | } while (0) |
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340 | |
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341 | /* |
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342 | * Each timer control register is organized as follows: |
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343 | * |
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344 | * D0 - Enable |
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345 | * 1 = enable counting |
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346 | * 0 = hold scaler and counter |
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347 | * |
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348 | * D1 - Counter Reload |
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349 | * 1 = reload counter at zero and restart |
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350 | * 0 = stop counter at zero |
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351 | * |
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352 | * D2 - Counter Load |
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353 | * 1 = load counter with preset value |
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354 | * 0 = no function |
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355 | * |
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356 | */ |
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357 | |
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358 | #define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 |
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359 | #define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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360 | |
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361 | #define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 |
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362 | |
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363 | #define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 |
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364 | #define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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365 | |
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366 | #define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 |
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367 | #define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 |
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368 | |
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369 | #define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 |
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370 | #define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 |
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371 | |
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372 | #endif /* !ASM */ |
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373 | |
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374 | #ifdef __cplusplus |
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375 | } |
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376 | #endif |
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377 | |
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378 | #endif /* !_INCLUDE_LEON_h */ |
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379 | |
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