source: rtems/c/src/lib/libbsp/sparc/leon2/README @ b1ded240

4.104.115
Last change on this file since b1ded240 was bec7ba52, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jan 9, 2006 at 10:36:06 AM

Backport from rtems-4-6-branch.

  • Property mode set to 100644
File size: 2.3 KB
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1#
2#  Description of SIS as related to this BSP
3#
4#  $Id$
5#
6
7BSP NAME:           sis
8BOARD:              any based on the European Space Agency's ERC32
9BUS:                N/A
10CPU FAMILY:         sparc
11CPU:                ERC32 (SPARC V7 + on-CPU peripherals)
12                    based on Cypress 601/602
13COPROCESSORS:       on-chip 602 compatible FPU
14MODE:               32 bit mode
15
16DEBUG MONITOR:      none
17
18PERIPHERALS
19===========
20TIMERS:
21  NAME:             General Purpose Timer 
22  RESOLUTION:         50 nanoseconds - 12.8 microseconds
23  NAME:             Real Time Clock Timer 
24  RESOLUTION:         50 nanoseconds - 3.2768 milliseconds
25  NAME:             Watchdog Timer 
26  RESOLUTION:         XXX
27SERIAL PORTS:       2 using on-chip UART
28REAL-TIME CLOCK:    none
29DMA:                on-chip
30VIDEO:              none
31SCSI:               none
32NETWORKING:         none
33
34DRIVER INFORMATION
35==================
36CLOCK DRIVER:       ERC32 internal Real Time Clock Timer
37IOSUPP DRIVER:      N/A
38SHMSUPP:            N/A
39TIMER DRIVER:       ERC32 internal General Purpose Timer
40CONSOLE DRIVER:     ERC32 internal UART
41
42STDIO
43=====
44PORT:               Channel A
45ELECTRICAL:         na since using simulator
46BAUD:               na
47BITS PER CHARACTER: na
48PARITY:             na
49STOP BITS:          na
50
51Notes
52=====
53
54ERC32 BSP only supports single processor operations.
55
56A nice feature of this BSP is that the RAM and PROM size are set in the
57linkcmds file and the startup code programs the Memory Configuration
58Register based on those sizes.
59
60The Watchdog Timer is disabled.
61
62This code was developed and tested entirely using the SPARC Instruction
63Simulator (SIS) for the ERC32.  All tests were known to run correctly
64against sis v1.7.
65
66
67Memory Map
68==========
69
700x00000000 - 0x00000000 + _PROM_SIZE      code and initialized data
710x01f80000                                on chip peripherals
720x00000000 - 0x02000000 + _RAM_SIZE       destination for initialized data
73                                          BSS (i.e. unitialized data)
74                                          C Heap (i.e. malloc area)
75                                          RTEMS Workspace
76
77The C heap is assigned all memory between the end of the BSS and the
78RTEMS Workspace.  The size of the RTEMS Workspace is based on that
79specified in the application's configuration table.
80 
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