source: rtems/c/src/lib/libbsp/sparc/leon/include/leon.h @ b21b0ab

4.104.114.84.95
Last change on this file since b21b0ab was b21b0ab, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 13, 2000 at 10:40:29 PM

2000-11-13 Jiri Gaisler <jgais@…>

  • .cvsignore, ChangeLog?, Makefile.am, README, bsp_specs, configure.in, times, clock/.cvsignore, clock/Makefile.am, clock/ckinit.c, console/.cvsignore, console/Makefile.am, console/console.c, console/consolereserveresources.c, console/debugputs.c, gnatsupp/.cvsignore, gnatsupp/Makefile.am, gnatsupp/gnatsupp.c, include/.cvsignore, include/Makefile.am, include/bsp.h, include/coverhd.h, include/leon.h, start/.cvsignore, start/Makefile.am, startup/.cvsignore, startup/Makefile.am, startup/boardinit.S, startup/linkcmds, startup/setvec.c, startup/spurious.c, timer/.cvsignore, timer/Makefile.am, timer/timer.c, tools/.cvsignore, tools/Makefile.am, tools/configure.in, tools/runtest.in, wrapup/.cvsignore, wrapup/Makefile.am: New file.
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File size: 13.5 KB
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1/*  erc32.h
2 *
3 *  This include file contains information pertaining to the LEON-1.
4 *  The LEON-1 is a custom SPARC V7 implementation.
5 *  This CPU has a number of on-board peripherals and
6 *  was developed by the European Space Agency to target space applications.
7 *
8 *  NOTE:  Other than where absolutely required, this version currently
9 *         supports only the peripherals and bits used by the basic board
10 *         support package. This includes at least significant pieces of
11 *         the following items:
12 *
13 *           + UART Channels A and B
14 *           + Real Time Clock
15 *           + Memory Control Register
16 *           + Interrupt Control
17 *
18 *  COPYRIGHT (c) 1989-1998.
19 *  On-Line Applications Research Corporation (OAR).
20 *  Copyright assigned to U.S. Government, 1994.
21 *
22 *  The license and distribution terms for this file may be
23 *  found in the file LICENSE in this distribution or at
24 *  http://www.OARcorp.com/rtems/license.html.
25 *
26 *  Ported to LEON implementation of the SPARC by On-Line Applications
27 *  Research Corporation (OAR) under contract to the European Space
28 *  Agency (ESA).
29 *
30 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
31 *  European Space Agency.
32 *
33 *  $Id$
34 */
35 
36#ifndef _INCLUDE_LEON_h
37#define _INCLUDE_LEON_h
38
39#include <rtems/score/sparc.h>
40 
41#ifdef __cplusplus
42extern "C" {
43#endif
44
45/*
46 *  Interrupt Sources
47 *
48 *  The interrupt source numbers directly map to the trap type and to
49 *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
50 *  and the Interrupt Pending Registers.
51 */
52
53#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR  1
54#define LEON_INTERRUPT_UART_2_RX_TX              2
55#define LEON_INTERRUPT_UART_1_RX_TX              3
56#define LEON_INTERRUPT_EXTERNAL_0                4
57#define LEON_INTERRUPT_EXTERNAL_1                5
58#define LEON_INTERRUPT_EXTERNAL_2                6
59#define LEON_INTERRUPT_EXTERNAL_3                7
60#define LEON_INTERRUPT_TIMER1                    8
61#define LEON_INTERRUPT_TIMER2                    9
62#define LEON_INTERRUPT_EMPTY1                    10
63#define LEON_INTERRUPT_EMPTY2                    11
64#define LEON_INTERRUPT_EMPTY3                    12
65#define LEON_INTERRUPT_EMPTY4                    13
66#define LEON_INTERRUPT_EMPTY5                    14
67#define LEON_INTERRUPT_EMPTY6                    15
68
69#ifndef ASM
70
71/*
72 *  Trap Types for on-chip peripherals
73 *
74 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
75 *
76 *  NOTE: The priority level for each source corresponds to the least
77 *        significant nibble of the trap type.
78 */
79
80#define LEON_TRAP_TYPE( _source ) SPARC_ASYNCHRONOUS_TRAP((_source) + 0x10)
81
82#define LEON_TRAP_SOURCE( _trap ) ((_trap) - 0x10)
83
84#define LEON_INT_TRAP( _trap ) \
85  ( (_trap) >= LEON_TRAP_TYPE( LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR ) && \
86    (_trap) <= LEON_TRAP_TYPE( LEON_INTERRUPT_EMPTY6 ) )
87
88/*
89 *  Structure for LEON memory mapped registers. 
90 *
91 *  Source: Section 6.1 - On-chip registers
92 *
93 *  NOTE:  There is only one of these structures per CPU, its base address
94 *         is 0x80000000, and the variable LEON_REG is placed there by the
95 *         linkcmds file.
96 */
97
98typedef struct {
99        volatile unsigned int Memory_Config_1;
100        volatile unsigned int Memory_Config_2;
101        volatile unsigned int Edac_Control;
102        volatile unsigned int Failed_Address;
103        volatile unsigned int Memory_Status;
104        volatile unsigned int Cache_Control;
105        volatile unsigned int Power_Down;
106        volatile unsigned int Write_Protection_1;
107        volatile unsigned int Write_Protection_2;
108        volatile unsigned int Leon_Configuration;
109        volatile unsigned int dummy2;
110        volatile unsigned int dummy3;
111        volatile unsigned int dummy4;   
112        volatile unsigned int dummy5;
113        volatile unsigned int dummy6;
114        volatile unsigned int dummy7;
115        volatile unsigned int Timer_Counter_1;
116        volatile unsigned int Timer_Reload_1;
117        volatile unsigned int Timer_Control_1;
118        volatile unsigned int Watchdog;
119        volatile unsigned int Timer_Counter_2;
120        volatile unsigned int Timer_Reload_2;
121        volatile unsigned int Timer_Control_2;
122        volatile unsigned int dummy8;
123        volatile unsigned int Scaler_Counter;
124        volatile unsigned int Scaler_Reload;
125        volatile unsigned int dummy9;
126        volatile unsigned int dummy10;
127        volatile unsigned int UART_Channel_1;
128        volatile unsigned int UART_Status_1;
129        volatile unsigned int UART_Control_1;
130        volatile unsigned int UART_Scaler_1;
131        volatile unsigned int UART_Channel_2;
132        volatile unsigned int UART_Status_2;
133        volatile unsigned int UART_Control_2;
134        volatile unsigned int UART_Scaler_2;
135        volatile unsigned int Interrupt_Mask;
136        volatile unsigned int Interrupt_Pending;
137        volatile unsigned int Interrupt_Force;
138        volatile unsigned int Interrupt_Clear;
139        volatile unsigned int PIO_Data;
140        volatile unsigned int PIO_Direction;
141        volatile unsigned int PIO_Interrupt;
142} LEON_Register_Map;
143
144#endif
145
146/*
147 *  The following constants are intended to be used ONLY in assembly
148 *  language files.
149 *
150 *  NOTE:  The intended style of usage is to load the address of LEON REGS
151 *         into a register and then use these as displacements from
152 *         that register.
153 */
154
155#ifdef ASM
156
157#define  LEON_REG_MEMCFG1_OFFSET                                  0x00
158#define  LEON_REG_MEMCFG2_OFFSET                                  0x04
159#define  LEON_REG_EDACCTRL_OFFSET                                 0x08
160#define  LEON_REG_FAILADDR_OFFSET                                 0x0C
161#define  LEON_REG_MEMSTATUS_OFFSET                                0x10
162#define  LEON_REG_CACHECTRL_OFFSET                                0x14
163#define  LEON_REG_POWERDOWN_OFFSET                                0x18
164#define  LEON_REG_WRITEPROT1_OFFSET                               0x1C
165#define  LEON_REG_WRITEPROT2_OFFSET                               0x20
166#define  LEON_REG_LEONCONF_OFFSET                                 0x24
167#define  LEON_REG_UNIMPLEMENTED_2_OFFSET                          0x28
168#define  LEON_REG_UNIMPLEMENTED_3_OFFSET                          0x2C
169#define  LEON_REG_UNIMPLEMENTED_4_OFFSET                          0x30
170#define  LEON_REG_UNIMPLEMENTED_5_OFFSET                          0x34
171#define  LEON_REG_UNIMPLEMENTED_6_OFFSET                          0x38
172#define  LEON_REG_UNIMPLEMENTED_7_OFFSET                          0x3C
173#define  LEON_REG_TIMERCNT1_OFFSET                                0x40
174#define  LEON_REG_TIMERLOAD1_OFFSET                               0x44
175#define  LEON_REG_TIMERCTRL1_OFFSET                               0x48
176#define  LEON_REG_WDOG_OFFSET                                     0x4C
177#define  LEON_REG_TIMERCNT2_OFFSET                                0x50
178#define  LEON_REG_TIMERLOAD2_OFFSET                               0x54
179#define  LEON_REG_TIMERCTRL2_OFFSET                               0x58
180#define  LEON_REG_UNIMPLEMENTED_8_OFFSET                          0x5C
181#define  LEON_REG_SCALERCNT_OFFSET                                0x60
182#define  LEON_REG_SCALER_LOAD_OFFSET                              0x64
183#define  LEON_REG_UNIMPLEMENTED_9_OFFSET                          0x68
184#define  LEON_REG_UNIMPLEMENTED_10_OFFSET                         0x6C
185#define  LEON_REG_UARTDATA1_OFFSET                                0x70
186#define  LEON_REG_UARTSTATUS1_OFFSET                              0x74
187#define  LEON_REG_UARTCTRL1_OFFSET                                0x78
188#define  LEON_REG_UARTSCALER1_OFFSET                              0x7C
189#define  LEON_REG_UARTDATA2_OFFSET                                0x80
190#define  LEON_REG_UARTSTATUS2_OFFSET                              0x84
191#define  LEON_REG_UARTCTRL2_OFFSET                                0x88
192#define  LEON_REG_UARTSCALER2_OFFSET                              0x8C
193#define  LEON_REG_IRQMASK_OFFSET                                  0x90
194#define  LEON_REG_IRQPEND_OFFSET                                  0x94
195#define  LEON_REG_IRQFORCE_OFFSET                                 0x98
196#define  LEON_REG_IRQCLEAR_OFFSET                                 0x9C
197#define  LEON_REG_PIODATA_OFFSET                                  0xA0
198#define  LEON_REG_PIODIR_OFFSET                                   0xA4
199#define  LEON_REG_PIOIRQ_OFFSET                                   0xA8
200#define  LEON_REG_SIM_RAM_SIZE_OFFSET                             0xF4
201#define  LEON_REG_SIM_ROM_SIZE_OFFSET                             0xF8
202
203#endif
204
205/*
206 *  The following defines the bits in Memory Configuration Register 1.
207 */
208
209#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x0003C000
210
211/*
212 *  The following defines the bits in Memory Configuration Register 1.
213 */
214
215#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
216
217 
218/*
219 *  The following defines the bits in the Timer Control Register.
220 */
221
222#define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
223                                                 /* 0 = hold scalar and counter */
224#define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
225                                                 /* 0 = stop at 0 */
226#define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
227                                                 /* 0 = no function */
228
229/*
230 *  The following defines the bits in the UART Control Registers.
231 *
232 */
233
234#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
235 
236/*
237 *  The following defines the bits in the LEON UART Status Registers.
238 */
239
240#define LEON_REG_UART_STATUS_DR   0x00000001 /* Data Ready */
241#define LEON_REG_UART_STATUS_TSE  0x00000002 /* TX Send Register Empty */
242#define LEON_REG_UART_STATUS_THE  0x00000004 /* TX Hold Register Empty */
243#define LEON_REG_UART_STATUS_BR   0x00000008 /* Break Error */
244#define LEON_REG_UART_STATUS_OE   0x00000010 /* RX Overrun Error */
245#define LEON_REG_UART_STATUS_PE   0x00000020 /* RX Parity Error */
246#define LEON_REG_UART_STATUS_FE   0x00000040 /* RX Framing Error */
247#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
248
249 
250/*
251 *  The following defines the bits in the LEON UART Status Registers.
252 */
253
254#define LEON_REG_UART_CTRL_RE     0x00000001 /* Receiver enable */
255#define LEON_REG_UART_CTRL_TE     0x00000002 /* Transmitter enable */
256#define LEON_REG_UART_CTRL_RI     0x00000004 /* Receiver interrupt enable */
257#define LEON_REG_UART_CTRL_TI     0x00000008 /* Transmitter interrupt enable */
258#define LEON_REG_UART_CTRL_PS     0x00000010 /* Parity select */
259#define LEON_REG_UART_CTRL_PE     0x00000020 /* Parity enable */
260#define LEON_REG_UART_CTRL_FL     0x00000040 /* Flow control enable */
261#define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
262
263#ifndef ASM
264
265/*
266 *  This is used to manipulate the on-chip registers.
267 *
268 *  The following symbol must be defined in the linkcmds file and point
269 *  to the correct location.
270 */
271
272extern LEON_Register_Map LEON_REG;
273 
274/*
275 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
276 *  and the Interrupt Pending Registers.
277 *
278 *  NOTE: For operations which are not atomic, this code disables interrupts
279 *        to guarantee there are no intervening accesses to the same register.
280 *        The operations which read the register, modify the value and then
281 *        store the result back are vulnerable.
282 */
283
284#define LEON_Clear_interrupt( _source ) \
285  do { \
286    LEON_REG.Interrupt_Clear = (1 << (_source)); \
287  } while (0)
288
289#define LEON_Force_interrupt( _source ) \
290  do { \
291    LEON_REG.Interrupt_Force = (1 << (_source)); \
292  } while (0)
293 
294#define LEON_Is_interrupt_pending( _source ) \
295  (LEON_REG.Interrupt_Pending & (1 << (_source)))
296 
297#define LEON_Is_interrupt_masked( _source ) \
298  (LEON_REG.Interrupt_Masked & (1 << (_source)))
299 
300#define LEON_Mask_interrupt( _source ) \
301  do { \
302    unsigned32 _level; \
303    \
304    _level = sparc_disable_interrupts(); \
305      LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
306    sparc_enable_interrupts( _level ); \
307  } while (0)
308 
309#define LEON_Unmask_interrupt( _source ) \
310  do { \
311    unsigned32 _level; \
312    \
313    _level = sparc_disable_interrupts(); \
314      LEON_REG.Interrupt_Mask |= (1 << (_source)); \
315    sparc_enable_interrupts( _level ); \
316  } while (0)
317
318#define LEON_Disable_interrupt( _source, _previous ) \
319  do { \
320    unsigned32 _level; \
321    unsigned32 _mask = 1 << (_source); \
322    \
323    _level = sparc_disable_interrupts(); \
324      (_previous) = LEON_REG.Interrupt_Mask; \
325      LEON_REG.Interrupt_Mask = _previous & ~_mask; \
326    sparc_enable_interrupts( _level ); \
327    (_previous) &= _mask; \
328  } while (0)
329 
330#define LEON_Restore_interrupt( _source, _previous ) \
331  do { \
332    unsigned32 _level; \
333    unsigned32 _mask = 1 << (_source); \
334    \
335    _level = sparc_disable_interrupts(); \
336      LEON_REG.Interrupt_Mask = \
337        (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \
338    sparc_enable_interrupts( _level ); \
339  } while (0)
340
341/*
342 *  Each timer control register is organized as follows:
343 *
344 *    D0 - Enable
345 *          1 = enable counting
346 *          0 = hold scaler and counter
347 *
348 *    D1 - Counter Reload
349 *          1 = reload counter at zero and restart
350 *          0 = stop counter at zero
351 *
352 *    D2 - Counter Load
353 *          1 = load counter with preset value
354 *          0 = no function
355 *
356 */
357
358#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO     0x00000002
359#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO       0x00000000
360
361#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER       0x00000004
362
363#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING    0x00000001
364#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING   0x00000000
365
366#define LEON_REG_TIMER_COUNTER_RELOAD_MASK        0x00000002
367#define LEON_REG_TIMER_COUNTER_ENABLE_MASK        0x00000001
368
369#define LEON_REG_TIMER_COUNTER_DEFINED_MASK       0x00000003
370#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK  0x00000003
371
372#endif /* !ASM */
373
374#ifdef __cplusplus
375}
376#endif
377 
378#endif /* !_INCLUDE_LEON_h */
379/* end of include file */
380
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