source:
rtems/c/src/lib/libbsp/sparc/leon/README
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b21b0ab
Last change on this file since b21b0ab was b21b0ab, checked in by Joel Sherrill <joel.sherrill@…>, on 11/13/00 at 22:40:29 | |
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[b21b0ab] | 1 | # |
2 | # Description of SIS as related to this BSP | |
3 | # | |
4 | # $Id$ | |
5 | # | |
6 | ||
7 | BSP NAME: sis | |
8 | BOARD: any based on the European Space Agency's ERC32 | |
9 | BUS: N/A | |
10 | CPU FAMILY: sparc | |
11 | CPU: ERC32 (SPARC V7 + on-CPU peripherals) | |
12 | based on Cypress 601/602 | |
13 | COPROCESSORS: on-chip 602 compatible FPU | |
14 | MODE: 32 bit mode | |
15 | ||
16 | DEBUG MONITOR: none | |
17 | ||
18 | PERIPHERALS | |
19 | =========== | |
20 | TIMERS: | |
21 | NAME: General Purpose Timer | |
22 | RESOLUTION: 50 nanoseconds - 12.8 microseconds | |
23 | NAME: Real Time Clock Timer | |
24 | RESOLUTION: 50 nanoseconds - 3.2768 milliseconds | |
25 | NAME: Watchdog Timer | |
26 | RESOLUTION: XXX | |
27 | SERIAL PORTS: 2 using on-chip UART | |
28 | REAL-TIME CLOCK: none | |
29 | DMA: on-chip | |
30 | VIDEO: none | |
31 | SCSI: none | |
32 | NETWORKING: none | |
33 | ||
34 | DRIVER INFORMATION | |
35 | ================== | |
36 | CLOCK DRIVER: ERC32 internal Real Time Clock Timer | |
37 | IOSUPP DRIVER: N/A | |
38 | SHMSUPP: N/A | |
39 | TIMER DRIVER: ERC32 internal General Purpose Timer | |
40 | CONSOLE DRIVER: ERC32 internal UART | |
41 | ||
42 | STDIO | |
43 | ===== | |
44 | PORT: Channel A | |
45 | ELECTRICAL: na since using simulator | |
46 | BAUD: na | |
47 | BITS PER CHARACTER: na | |
48 | PARITY: na | |
49 | STOP BITS: na | |
50 | ||
51 | Notes | |
52 | ===== | |
53 | ||
54 | ERC32 BSP only supports single processor operations. | |
55 | ||
56 | A nice feature of this BSP is that the RAM and PROM size are set in the | |
57 | linkcmds file and the startup code programs the Memory Configuration | |
58 | Register based on those sizes. | |
59 | ||
60 | The Watchdog Timer is disabled. | |
61 | ||
62 | This code was developed and tested entirely using the SPARC Instruction | |
63 | Simulator (SIS) for the ERC32. All tests were known to run correctly | |
64 | against sis v1.7. | |
65 | ||
66 | ||
67 | Memory Map | |
68 | ========== | |
69 | ||
70 | 0x00000000 - 0x00000000 + _PROM_SIZE code and initialized data | |
71 | 0x01f80000 on chip peripherals | |
72 | 0x00000000 - 0x02000000 + _RAM_SIZE destination for initialized data | |
73 | BSS (i.e. unitialized data) | |
74 | C Heap (i.e. malloc area) | |
75 | RTEMS Workspace | |
76 | ||
77 | The C heap is assigned all memory between the end of the BSS and the | |
78 | RTEMS Workspace. The size of the RTEMS Workspace is based on that | |
79 | specified in the application's configuration table. | |
80 |
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