source: rtems/c/src/lib/libbsp/sparc/erc32/startup/spurious.c @ 815994f

4.11
Last change on this file since 815994f was 815994f, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2012 at 4:48:11 PM

score: Add CPU_Exception_frame

Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().

The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().

Add rtems_exception_frame and rtems_exception_frame_print().

Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.

Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().

Add test sptests/spfatal26.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 *  ERC32 Spurious Trap Handler
3 *
4 *  This is just enough of a trap handler to let us know what
5 *  the likely source of the trap was.
6 *
7 *  Developed as part of the port of RTEMS to the ERC32 implementation
8 *  of the SPARC by On-Line Applications Research Corporation (OAR)
9 *  under contract to the European Space Agency (ESA).
10 *
11 *  COPYRIGHT (c) 1995. European Space Agency.
12 *
13 *  This terms of the RTEMS license apply to this file.
14 */
15
16#include <bsp.h>
17#include <rtems/bspIo.h>
18
19void _BSP_Exception_frame_print( const CPU_Exception_frame *frame )
20{
21  uint32_t                   trap;
22  uint32_t                   real_trap;
23  const CPU_Interrupt_frame *isf;
24
25  trap = frame->trap;
26  real_trap = SPARC_REAL_TRAP_NUMBER(trap);
27  isf = frame->isf;
28
29  printk( "Unexpected trap (%2d) at address 0x%08x\n", real_trap, isf->tpc);
30
31  switch (real_trap) {
32
33    /*
34     *  First the ones defined by the basic architecture
35     */
36
37    case 0x00:
38      printk( "reset\n" );
39      break;
40    case 0x01:
41      printk( "instruction access exception\n" );
42      break;
43    case 0x02:
44      printk( "illegal instruction\n" );
45      break;
46    case 0x03:
47      printk( "privileged instruction\n" );
48      break;
49    case 0x04:
50      printk( "fp disabled\n" );
51      break;
52    case 0x07:
53      printk( "memory address not aligned\n" );
54      break;
55    case 0x08:
56      printk( "fp exception\n" );
57      break;
58    case 0x09:
59      printk("data access exception at 0x%08x\n",
60        ERC32_MEC.First_Failing_Address );
61      break;
62    case 0x0A:
63      printk( "tag overflow\n" );
64      break;
65
66    /*
67     *  Then the ones defined by the ERC32 in particular
68     */
69
70    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_MASKED_ERRORS ):
71      printk( "ERC32_INTERRUPT_MASKED_ERRORS\n" );
72      break;
73    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_1 ):
74      printk( "ERC32_INTERRUPT_EXTERNAL_1\n" );
75      break;
76    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_2 ):
77      printk( "ERC32_INTERRUPT_EXTERNAL_2\n" );
78      break;
79    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_A_RX_TX ):
80      printk( "ERC32_INTERRUPT_UART_A_RX_TX\n" );
81      break;
82    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_B_RX_TX ):
83      printk( "ERC32_INTERRUPT_UART_A_RX_TX\n" );
84      break;
85    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR ):
86      printk( "ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR\n" );
87      break;
88    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_UART_ERROR ):
89      printk( "ERC32_INTERRUPT_UART_ERROR\n" );
90      break;
91    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_DMA_ACCESS_ERROR ):
92      printk( "ERC32_INTERRUPT_DMA_ACCESS_ERROR\n" );
93      break;
94    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_DMA_TIMEOUT ):
95      printk( "ERC32_INTERRUPT_DMA_TIMEOUT\n" );
96      break;
97    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_3 ):
98      printk( "ERC32_INTERRUPT_EXTERNAL_3\n" );
99      break;
100    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_4 ):
101      printk( "ERC32_INTERRUPT_EXTERNAL_4\n" );
102      break;
103    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER ):
104      printk( "ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER\n" );
105      break;
106    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_REAL_TIME_CLOCK ):
107      printk( "ERC32_INTERRUPT_REAL_TIME_CLOCK\n" );
108      break;
109    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_EXTERNAL_5 ):
110      printk( "ERC32_INTERRUPT_EXTERNAL_5\n" );
111      break;
112    case ERC32_TRAP_TYPE( ERC32_INTERRUPT_WATCHDOG_TIMEOUT ):
113      printk( "ERC32_INTERRUPT_WATCHDOG_TIMEOUT\n" );
114      break;
115
116    default:
117      break;
118  }
119}
120
121rtems_isr bsp_spurious_handler(
122   rtems_vector_number trap,
123   CPU_Interrupt_frame *isf
124)
125{
126  CPU_Exception_frame frame = {
127    .trap = trap,
128    .isf = isf
129  };
130
131  rtems_fatal(
132    RTEMS_FATAL_SOURCE_EXCEPTION,
133    (rtems_fatal_code) &frame
134  );
135}
136
137/*
138 *  bsp_spurious_initialize
139 *
140 *  Install the spurious handler for most traps. Note that set_vector()
141 *  will unmask the corresponding asynchronous interrupt, so the initial
142 *  interrupt mask is restored after the handlers are installed.
143 */
144
145void bsp_spurious_initialize()
146{
147  uint32_t   trap;
148  uint32_t   level = 15;
149  uint32_t   mask;
150
151  level = sparc_disable_interrupts();
152  mask = ERC32_MEC.Interrupt_Mask;
153
154  for ( trap=0 ; trap<256 ; trap++ ) {
155
156    /*
157     *  Skip window overflow, underflow, and flush as well as software
158     *  trap 0 which we will use as a shutdown. Also avoid trap 0x70 - 0x7f
159     *  which cannot happen and where some of the space is used to pass
160     *  paramaters to the program.
161     */
162
163     if (( trap == 5 || trap == 6 ) ||
164        (( trap >= 0x11 ) && ( trap <= 0x1f )) ||
165        (( trap >= 0x70 ) && ( trap <= 0x83 )))
166      continue;
167
168    set_vector( (rtems_isr_entry) bsp_spurious_handler,
169         SPARC_SYNCHRONOUS_TRAP( trap ), 1 );
170  }
171
172  ERC32_MEC.Interrupt_Mask = mask;
173  sparc_enable_interrupts(level);
174
175}
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