source: rtems/c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c @ a1c86a4c

4.104.114.84.95
Last change on this file since a1c86a4c was a1c86a4c, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 21, 2000 at 2:02:17 PM

2000-11-21 Jiri Gaisler <jgais@…>

  • erc32sonic/erc32sonic.c: Minor modifications which enable network interface to come up and work for some time before getting an error in the SONIC driver. The error is a bit random, sometimes MCLGET (m, M_WAIT) tries to access memory way outside the available ram (and traps) while sometimes there is a panic due to RBAE/RXEN.
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 *  THARSYS VME SPARC RT board SONIC Configuration Information
3 *
4 *  References:
5 *
6 *  1) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
7 *     DY 4 Systems Inc., Kanata, Ontario, September, 1996.
8 *
9 *  $Id$
10 */
11
12#include <bsp.h>
13#include <libchip/sonic.h>
14#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
15#include <stdio.h>
16#endif
17
18void erc32_sonic_write_register(
19  void       *base,
20  unsigned32  regno,
21  unsigned32  value
22)
23{
24  volatile unsigned32 *p = base;
25
26#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
27  printf( "%p Write 0x%04x to %s (0x%02x)\n",
28      &p[regno], value, SONIC_Reg_name[regno], regno );
29  fflush( stdout );
30#endif
31  p[regno] = 0x0ffff & value;
32}
33
34unsigned32 erc32_sonic_read_register(
35  void       *base,
36  unsigned32  regno
37)
38{
39  volatile unsigned32 *p = base;
40  unsigned32           value;
41
42  value = p[regno];
43#if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS)
44  printf( "%p Read 0x%04x from %s (0x%02x)\n",
45      &p[regno], value, SONIC_Reg_name[regno], regno );
46  fflush( stdout );
47#endif
48  return 0x0ffff & value;
49}
50
51/*
52 * Default sizes of transmit and receive descriptor areas
53 */
54#define RDA_COUNT     20 /* 20 */
55#define TDA_COUNT     20 /* 10 */
56
57/*
58 * Default device configuration register values
59 * Conservative, generic values.
60 * DCR:
61 *      No extended bus mode
62 *      Unlatched bus retry
63 *      Programmable outputs unused
64 *      Asynchronous bus mode
65 *      User definable pins unused
66 *      No wait states (access time controlled by DTACK*)
67 *      32-bit DMA
68 *      Empty/Fill DMA mode
69 *      Maximum Transmit/Receive FIFO
70 * DC2:
71 *      Extended programmable outputs unused
72 *      Normal HOLD request
73 *      Packet compress output unused
74 *      No reject on CAM match
75 */
76#define SONIC_DCR  ( DCR_DW32 | DCR_RFT24 | DCR_TFT28)
77#define SONIC_DC2 (0)
78
79/*
80 * Default location of device registers
81 */
82#define SONIC_BASE_ADDRESS 0x10000100
83
84/*
85 * Default interrupt vector
86 */
87#define SONIC_VECTOR 0x1E
88
89sonic_configuration_t erc32_sonic_configuration = {
90  SONIC_BASE_ADDRESS,        /* base address */ 
91  SONIC_VECTOR,              /* vector number */ 
92  SONIC_DCR,                 /* DCR register value */
93  SONIC_DC2,                 /* DC2 register value */
94  TDA_COUNT,                 /* number of transmit descriptors */
95  RDA_COUNT,                 /* number of receive descriptors */
96  erc32_sonic_write_register,
97  erc32_sonic_read_register
98};
99
100int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config)
101{
102
103  ERC32_MEC.IO_Configuration |= (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
104  ERC32_MEC.Control &= ~0x60001; /* Disable DMA time-out, parity & power-down */
105  ERC32_MEC.Control |= 0x10000;                 /* Enable DMA */
106  ERC32_MEC.Interrupt_Mask &= ~(1 << (SONIC_VECTOR - 0x10));
107  return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration ));
108 
109}
Note: See TracBrowser for help on using the repository browser.