[2700423] | 1 | /* |
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| 2 | * THARSYS VME SPARC RT board SONIC Configuration Information |
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| 3 | * |
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| 4 | * References: |
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| 5 | * |
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| 6 | * 1) SVME/DMV-171 Single Board Computer Documentation Package, #805905, |
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| 7 | * DY 4 Systems Inc., Kanata, Ontario, September, 1996. |
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| 8 | * |
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| 9 | * $Id$ |
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| 10 | */ |
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| 11 | |
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| 12 | #include <bsp.h> |
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| 13 | #include <libchip/sonic.h> |
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| 14 | #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) |
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| 15 | #include <stdio.h> |
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| 16 | #endif |
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| 17 | |
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| 18 | void erc32_sonic_write_register( |
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| 19 | void *base, |
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| 20 | unsigned32 regno, |
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| 21 | unsigned32 value |
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| 22 | ) |
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| 23 | { |
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| 24 | volatile unsigned32 *p = base; |
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| 25 | |
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| 26 | #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) |
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| 27 | printf( "%p Write 0x%04x to %s (0x%02x)\n", |
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| 28 | &p[regno], value, SONIC_Reg_name[regno], regno ); |
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| 29 | fflush( stdout ); |
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| 30 | #endif |
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| 31 | p[regno] = 0x0ffff & value; |
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| 32 | } |
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| 33 | |
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| 34 | unsigned32 erc32_sonic_read_register( |
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| 35 | void *base, |
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| 36 | unsigned32 regno |
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| 37 | ) |
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| 38 | { |
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| 39 | volatile unsigned32 *p = base; |
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| 40 | unsigned32 value; |
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| 41 | |
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| 42 | value = p[regno]; |
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| 43 | #if (SONIC_DEBUG & SONIC_DEBUG_PRINT_REGISTERS) |
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| 44 | printf( "%p Read 0x%04x from %s (0x%02x)\n", |
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| 45 | &p[regno], value, SONIC_Reg_name[regno], regno ); |
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| 46 | fflush( stdout ); |
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| 47 | #endif |
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| 48 | return 0x0ffff & value; |
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| 49 | } |
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| 50 | |
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| 51 | /* |
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| 52 | * Default sizes of transmit and receive descriptor areas |
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| 53 | */ |
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| 54 | #define RDA_COUNT 20 /* 20 */ |
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| 55 | #define TDA_COUNT 20 /* 10 */ |
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| 56 | |
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| 57 | /* |
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| 58 | * Default device configuration register values |
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| 59 | * Conservative, generic values. |
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| 60 | * DCR: |
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| 61 | * No extended bus mode |
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| 62 | * Unlatched bus retry |
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| 63 | * Programmable outputs unused |
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| 64 | * Asynchronous bus mode |
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| 65 | * User definable pins unused |
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| 66 | * No wait states (access time controlled by DTACK*) |
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| 67 | * 32-bit DMA |
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| 68 | * Empty/Fill DMA mode |
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| 69 | * Maximum Transmit/Receive FIFO |
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| 70 | * DC2: |
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| 71 | * Extended programmable outputs unused |
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| 72 | * Normal HOLD request |
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| 73 | * Packet compress output unused |
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| 74 | * No reject on CAM match |
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| 75 | */ |
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| 76 | #define SONIC_DCR ( DCR_DW32 | DCR_RFT24 | DCR_TFT28) |
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| 77 | #define SONIC_DC2 (0) |
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| 78 | |
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| 79 | /* |
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| 80 | * Default location of device registers |
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| 81 | */ |
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| 82 | #define SONIC_BASE_ADDRESS 0x10000100 |
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| 83 | |
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| 84 | /* |
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| 85 | * Default interrupt vector |
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| 86 | */ |
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| 87 | #define SONIC_VECTOR 0x1E |
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| 88 | |
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| 89 | sonic_configuration_t erc32_sonic_configuration = { |
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| 90 | SONIC_BASE_ADDRESS, /* base address */ |
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| 91 | SONIC_VECTOR, /* vector number */ |
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| 92 | SONIC_DCR, /* DCR register value */ |
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| 93 | SONIC_DC2, /* DC2 register value */ |
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| 94 | TDA_COUNT, /* number of transmit descriptors */ |
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| 95 | RDA_COUNT, /* number of receive descriptors */ |
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| 96 | erc32_sonic_write_register, |
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| 97 | erc32_sonic_read_register |
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| 98 | }; |
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| 99 | |
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| 100 | int rtems_erc32_sonic_driver_attach(struct rtems_bsdnet_ifconfig *config) |
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| 101 | { |
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| 102 | |
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| 103 | ERC32_MEC.IO_Configuration |= (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8)); |
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| 104 | ERC32_MEC.Control &= ~0xe0000; /* Disable DMA time-out and parity */ |
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| 105 | ERC32_MEC.Control |= 0x10001; /* Enable DMA */ |
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| 106 | ERC32_MEC.Interrupt_Mask &= ~0x000340; |
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| 107 | *((volatile int *) 0x10000300) = 0; |
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| 108 | return(rtems_sonic_driver_attach( config, &erc32_sonic_configuration )); |
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| 109 | |
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| 110 | } |
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