[7f96eef] | 1 | /* |
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| 2 | * Clock Tick Device Driver |
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| 3 | * |
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| 4 | * This routine initializes the Real Time Clock Counter Timer which is |
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| 5 | * part of the MEC on the ERC32 CPU. |
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| 6 | * |
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| 7 | * The tick frequency is directly programmed to the configured number of |
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| 8 | * microseconds per tick. |
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| 9 | * |
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[0e58c4f] | 10 | * COPYRIGHT (c) 1989-2008. |
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[7f96eef] | 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * |
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[98e4ebf5] | 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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[c499856] | 15 | * http://www.rtems.org/license/LICENSE. |
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[7f96eef] | 16 | * |
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| 17 | * Ported to ERC32 implementation of the SPARC by On-Line Applications |
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[6128a4a] | 18 | * Research Corporation (OAR) under contract to the European Space |
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[7f96eef] | 19 | * Agency (ESA). |
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| 20 | * |
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[6128a4a] | 21 | * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. |
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[7f96eef] | 22 | * European Space Agency. |
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| 23 | */ |
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| 24 | |
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| 25 | #include <bsp.h> |
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[74b09f1] | 26 | #include <bspopts.h> |
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[a4bc90af] | 27 | #include <rtems/counter.h> |
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[74b09f1] | 28 | |
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| 29 | #if SIMSPARC_FAST_IDLE==1 |
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[d473dc0] | 30 | #define CLOCK_DRIVER_USE_FAST_IDLE 1 |
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[74b09f1] | 31 | #endif |
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[7f96eef] | 32 | |
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| 33 | /* |
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| 34 | * The Real Time Clock Counter Timer uses this trap type. |
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| 35 | */ |
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| 36 | |
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| 37 | #define CLOCK_VECTOR ERC32_TRAP_TYPE( ERC32_INTERRUPT_REAL_TIME_CLOCK ) |
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| 38 | |
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[74b09f1] | 39 | #define Clock_driver_support_at_tick() |
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[7f96eef] | 40 | |
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[74b09f1] | 41 | #define Clock_driver_support_install_isr( _new, _old ) \ |
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| 42 | do { \ |
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| 43 | _old = set_vector( _new, CLOCK_VECTOR, 1 ); \ |
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| 44 | } while(0) |
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[7f96eef] | 45 | |
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| 46 | extern int CLOCK_SPEED; |
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| 47 | |
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[e907f7d9] | 48 | uint32_t bsp_clock_nanoseconds_since_last_tick(void) |
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| 49 | { |
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| 50 | uint32_t clicks; |
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[d3210d0] | 51 | uint32_t usecs; |
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[e907f7d9] | 52 | |
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| 53 | clicks = ERC32_MEC.Real_Time_Clock_Counter; |
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| 54 | |
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[d3210d0] | 55 | if ( ERC32_Is_interrupt_pending( ERC32_INTERRUPT_REAL_TIME_CLOCK ) ) { |
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| 56 | clicks = ERC32_MEC.Real_Time_Clock_Counter; |
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| 57 | usecs = (2*rtems_configuration_get_microseconds_per_tick() - clicks); |
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| 58 | } else { |
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| 59 | usecs = (rtems_configuration_get_microseconds_per_tick() - clicks); |
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| 60 | } |
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| 61 | return usecs * 1000; |
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[e907f7d9] | 62 | } |
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| 63 | |
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[b214b1ba] | 64 | #define Clock_driver_nanoseconds_since_last_tick \ |
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| 65 | bsp_clock_nanoseconds_since_last_tick |
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[e907f7d9] | 66 | |
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[a4bc90af] | 67 | static CPU_Counter_ticks erc32_counter_difference( |
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| 68 | CPU_Counter_ticks second, |
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| 69 | CPU_Counter_ticks first |
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| 70 | ) |
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| 71 | { |
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| 72 | CPU_Counter_ticks period = rtems_configuration_get_microseconds_per_tick(); |
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| 73 | |
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| 74 | return (first + period - second) % period; |
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| 75 | } |
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| 76 | |
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[74b09f1] | 77 | #define Clock_driver_support_initialize_hardware() \ |
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| 78 | do { \ |
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| 79 | /* approximately 1 us per countdown */ \ |
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| 80 | ERC32_MEC.Real_Time_Clock_Scalar = CLOCK_SPEED - 1; \ |
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| 81 | ERC32_MEC.Real_Time_Clock_Counter = \ |
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[2d25867] | 82 | rtems_configuration_get_microseconds_per_tick(); \ |
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[74b09f1] | 83 | \ |
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| 84 | ERC32_MEC_Set_Real_Time_Clock_Timer_Control( \ |
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[9f058fb] | 85 | ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | \ |
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| 86 | ERC32_MEC_TIMER_COUNTER_LOAD_SCALER | \ |
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| 87 | ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER \ |
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[74b09f1] | 88 | ); \ |
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| 89 | \ |
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| 90 | ERC32_MEC_Set_Real_Time_Clock_Timer_Control( \ |
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[9f058fb] | 91 | ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING | \ |
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| 92 | ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO \ |
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[74b09f1] | 93 | ); \ |
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[a4bc90af] | 94 | _SPARC_Counter_initialize( \ |
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| 95 | &ERC32_MEC.Real_Time_Clock_Counter, \ |
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| 96 | erc32_counter_difference \ |
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| 97 | ); \ |
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| 98 | rtems_counter_initialize_converter(1000000); \ |
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[74b09f1] | 99 | } while (0) |
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| 100 | |
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| 101 | #define Clock_driver_support_shutdown_hardware() \ |
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| 102 | do { \ |
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| 103 | ERC32_Mask_interrupt( ERC32_INTERRUPT_REAL_TIME_CLOCK ); \ |
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| 104 | \ |
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| 105 | ERC32_MEC_Set_Real_Time_Clock_Timer_Control( \ |
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| 106 | ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING \ |
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| 107 | ); \ |
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| 108 | } while (0) |
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| 109 | |
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[8ce272b] | 110 | #include "../../../shared/clockdrv_shell.h" |
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[6128a4a] | 111 | |
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