[c766cac] | 1 | # |
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| 2 | # Description of SIS as related to this BSP |
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| 3 | # |
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| 4 | # $Id$ |
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| 5 | # |
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| 6 | |
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| 7 | BSP NAME: sis |
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| 8 | BOARD: any based on the European Space Agency's ERC32 |
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| 9 | BUS: N/A |
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| 10 | CPU FAMILY: sparc |
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| 11 | CPU: ERC32 (SPARC V7 + on-CPU peripherals) |
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| 12 | based on Cypress 601/602 |
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| 13 | COPROCESSORS: on-chip 602 compatible FPU |
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| 14 | MODE: 32 bit mode |
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| 15 | |
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| 16 | DEBUG MONITOR: none |
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| 17 | |
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| 18 | PERIPHERALS |
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| 19 | =========== |
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| 20 | TIMERS: |
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| 21 | NAME: General Purpose Timer |
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| 22 | RESOLUTION: 50 nanoseconds - 12.8 microseconds |
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| 23 | NAME: Real Time Clock Timer |
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| 24 | RESOLUTION: 50 nanoseconds - 3.2768 milliseconds |
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| 25 | NAME: Watchdog Timer |
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| 26 | RESOLUTION: XXX |
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| 27 | SERIAL PORTS: 2 using on-chip UART |
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| 28 | REAL-TIME CLOCK: none |
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| 29 | DMA: on-chip |
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| 30 | VIDEO: none |
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| 31 | SCSI: none |
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| 32 | NETWORKING: none |
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| 33 | |
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| 34 | DRIVER INFORMATION |
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| 35 | ================== |
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| 36 | CLOCK DRIVER: ERC32 internal Real Time Clock Timer |
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| 37 | IOSUPP DRIVER: N/A |
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| 38 | SHMSUPP: N/A |
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| 39 | TIMER DRIVER: ERC32 internal General Purpose Timer |
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| 40 | CONSOLE DRIVER: ERC32 internal UART |
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| 41 | |
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| 42 | STDIO |
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| 43 | ===== |
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| 44 | PORT: Channel A |
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| 45 | ELECTRICAL: na since using simulator |
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| 46 | BAUD: na |
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| 47 | BITS PER CHARACTER: na |
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| 48 | PARITY: na |
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| 49 | STOP BITS: na |
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| 50 | |
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| 51 | Notes |
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| 52 | ===== |
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| 53 | |
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| 54 | ERC32 BSP only supports single processor operations. |
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| 55 | |
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| 56 | A nice feature of this BSP is that the RAM and PROM size are set in the |
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| 57 | linkcmds file and the startup code programs the Memory Configuration |
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| 58 | Register based on those sizes. |
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| 59 | |
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| 60 | The Watchdog Timer is disabled. |
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| 61 | |
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| 62 | This code was developed and tested entirely using the SPARC Instruction |
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| 63 | Simulator (SIS) for the ERC32. All tests were known to run correctly |
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| 64 | against sis v1.7. |
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| 65 | |
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| 66 | |
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| 67 | Memory Map |
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| 68 | ========== |
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| 69 | |
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| 70 | 0x00000000 - 0x00000000 + _PROM_SIZE code and initialized data |
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| 71 | 0x01f80000 on chip peripherals |
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| 72 | 0x00000000 - 0x02000000 + _RAM_SIZE destination for initialized data |
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| 73 | BSS (i.e. unitialized data) |
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| 74 | C Heap (i.e. malloc area) |
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| 75 | RTEMS Workspace |
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| 76 | |
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| 77 | The C heap is assigned all memory between the end of the BSS and the |
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| 78 | RTEMS Workspace. The size of the RTEMS Workspace is based on that |
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| 79 | specified in the application's configuration table. |
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| 80 | |
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