source: rtems/c/src/lib/libbsp/shmdr/shm.h @ 3d07c8b

4.104.114.84.95
Last change on this file since 3d07c8b was 3d07c8b, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 8, 1996 at 4:24:13 PM

added mips64orion entries for SHM_LOCK_VALUE and SHM_UNLOCK_VALUE

  • Property mode set to 100644
File size: 19.6 KB
Line 
1/*  shm.h
2 *
3 *  This include file contains all the constants, structures,
4 *  and global variables for this RTEMS based shared memory
5 *  communications interface driver.
6 *
7 *  Processor board dependencies are in other files.
8 *
9 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
10 *  On-Line Applications Research Corporation (OAR).
11 *  All rights assigned to U.S. Government, 1994.
12 *
13 *  This material may be reproduced by or for the U.S. Government pursuant
14 *  to the copyright license under the clause at DFARS 252.227-7013.  This
15 *  notice must appear in all copies of this file and its derivatives.
16 *
17 *  $Id$
18 */
19
20#ifndef __SHM_h
21#define __SHM_h
22
23#include <clockdrv.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/*  The information contained in the Node Status, Locked Queue, and
30 *  Envelope Control Blocks must be maintained in a NEUTRAL format.
31 *  Currently the neutral format may be selected as big or little
32 *  endian by simply defining either NEUTRAL_BIG or NEUTRAL_LITTLE.
33 *
34 *  It is CRITICAL to note that the neutral format can ONLY be
35 *  changed by modifying this file and recompiling the ENTIRE
36 *  SHM driver including ALL target specific support files.
37 *
38 *  The following table details the memory contents for the endian
39 *  field of the Node Status Control Block in the various
40 *  data format configurations (data is in hexadecimal):
41 *
42 *   NEUTRAL NATIVE BYTE 0  BYTE 1  BYTE 2  BYTE 3
43 *   ======= ====== ======  ======  ======  ======
44 *    BIG     BIG     00      00      00      01
45 *    BIG    LITTLE   10      00      00      00
46 *   LITTLE   BIG     01      00      00      00
47 *   LITTLE  LITTLE   00      00      00      10
48 *
49 *
50 *  NOTE: XXX
51 *                PORTABILITY OF LOCKING INSTRUCTIONS
52 *                ===================================
53 *            The locking mechanism described below is not
54 *            general enough.  Where the hardware supports
55 *            it we should use "atomic swap" instructions
56 *            so the values in the lock can be tailored to
57 *            support a CPU with only weak atomic memory
58 *            instructions.  There are combinations of
59 *            CPUs with inflexible atomic memory instructions
60 *            which appear to be incompatible.  For example,
61 *            the SPARClite instruction uses a byte which is
62 *            0xFF when locked.  The PA-RISC uses 1 to indicate
63 *            locked and 0 when unlocked.  These CPUs appear to
64 *            have incompatible lock instructions.  But
65 *            they could be used in a heterogenous system
66 *            with does not mix SPARCs and PA-RISCs.  For
67 *            example, the i386 and SPARC or i386 and SPARC
68 *            could work together.  The bottom line is that
69 *            not every CPU will work together using this
70 *            locking scheme.  There are supposed to be
71 *            algorithms to do this without hardware assist
72 *            and one of these should be incorporated into
73 *            the shared memory driver.
74 *
75 *            The most flexible scheme using the instructions
76 *            of the various CPUs for efficiency would be to use
77 *            "atomic swaps" wherever possible.  Make the lock
78 *            and unlock configurable much like BIG vs LITTLE
79 *            endian use of shared memory is now.  The values
80 *            of the lock could then reflect the "worst"
81 *            CPU in a system.  This still results in mixes
82 *            of CPUs which are incompatible.
83 *
84 *  The current locking mechanism is based upon the MC68020
85 *  "tas" instruction which is atomic.  All ports to other CPUs
86 *  comply with the restrictive placement of lock bit by this
87 *  instruction.  The lock bit is the most significant bit in a
88 *  big-endian rtems_unsigned32.  On other processors, the lock is
89 *  typically implemented via an atomic swap or atomic modify
90 *  bits type instruction.
91 */
92
93#define NEUTRAL_BIG
94
95#ifdef NEUTRAL_BIG
96#define SHM_BIG       0x00000001
97#define SHM_LITTLE    0x10000000
98#endif
99
100#ifdef NEUTRAL_LITTLE
101#define SHM_BIG       0x01000000
102#define SHM_LITTLE    0x00000010
103#endif
104
105/*
106 *  The following are the values used to fill in the lock field.  Some CPUs
107 *  are able to write only a single value into field.  By making the
108 *  lock and unlock values configurable, CPUs which support "atomic swap"
109 *  instructions can generally be made to work in any heterogeneous
110 *  configuration.  However, it is possible for two CPUs to be incompatible
111 *  in regards to the lock field values.  This occurs when two CPUs
112 *  which write only a single value to the field are used in a system
113 *  but the two CPUs write different incompatible values.
114 *
115 *  NOTE:  The following is a first attempt at defining values which
116 *         have a chance at working together.  The m68k should use
117 *         chk2 instead of tas to be less restrictive.  Target endian
118 *         problems (like the Force CPU386 which has (broken) big endian
119 *         view of the VMEbus address space) are not addressed yet.
120 */
121
122#if defined(i960)
123#define SHM_LOCK_VALUE    0x00000080
124#define SHM_UNLOCK_VALUE  0
125#elif defined(m68k)
126#define SHM_LOCK_VALUE    0x80000000
127#define SHM_UNLOCK_VALUE  0
128#define SHM_LOCK_VALUE    0x80000000
129#define SHM_UNLOCK_VALUE  0
130#elif defined(i386)
131#define SHM_LOCK_VALUE    0x80000000
132#define SHM_UNLOCK_VALUE  0
133#elif defined(mips64orion)
134#define SHM_LOCK_VALUE    0x80000000
135#define SHM_UNLOCK_VALUE  0
136#elif defined(hppa1_1)
137#define SHM_LOCK_VALUE    0
138#define SHM_UNLOCK_VALUE  1
139#elif defined(unix)
140#define SHM_LOCK_VALUE    0
141#define SHM_UNLOCK_VALUE  1
142#elif defined(no_cpu)               /* for this values are irrelevant */
143#define SHM_LOCK_VALUE    1
144#define SHM_UNLOCK_VALUE  0
145#else
146#error "shm.h - no SHM_LOCK_VALUE defined for this CPU architecture"
147#endif
148
149#define Shm_Convert( value ) \
150  ((Shm_Configuration->convert) ? \
151    (*Shm_Configuration->convert)(value) : (value))
152
153/* constants */
154
155#define SHM_MASTER                  1     /* master initialization node */
156#define SHM_FIRST_NODE              1
157
158/* size constants */
159
160#define KILOBYTE          (1024)
161#define MEGABYTE          (1024*1024)
162
163/* inter-node interrupt values */
164
165#define NO_INTERRUPT            0     /* used for polled nodes */
166#define BYTE                    1
167#define WORD                    2
168#define LONG                    4
169
170/* operational mode constants -- used in SHM Configuration Table */
171#define POLLED_MODE             0
172#define INTR_MODE               1
173
174/* error codes */
175
176#define NO_ERROR                0
177#define SHM_NO_FREE_PKTS        0xf0000
178
179/* null pointers of different types */
180
181#define NULL_ENV_CB             ((Shm_Envelope_control *) 0)
182#define NULL_CONVERT            0
183
184/*
185 * size of stuff before preamble in envelope.
186 * It must be a constant since we will use it to generate MAX_PACKET_SIZE
187 */
188 
189#define SHM_ENVELOPE_PREFIX_OVERHEAD    (4 * sizeof(vol_u32))
190
191/*
192 *  The following is adjusted so envelopes are MAX_ENVELOPE_SIZE bytes long.
193 *  It must be >= RTEMS_MINIMUM_PACKET_SIZE in mppkt.h.
194 */
195 
196#ifndef MAX_ENVELOPE_SIZE
197#define MAX_ENVELOPE_SIZE 0x180
198#endif
199
200#define MAX_PACKET_SIZE  (MAX_ENVELOPE_SIZE -               \
201                          SHM_ENVELOPE_PREFIX_OVERHEAD +    \
202                          sizeof(Shm_Envelope_preamble) +   \
203                          sizeof(Shm_Envelope_postamble))
204
205
206/* constants pertinent to Locked Queue routines */
207
208#define LQ_UNLOCKED              SHM_UNLOCK_VALUE
209#define LQ_LOCKED                SHM_LOCK_VALUE
210
211/* constants related to the Free Envelope Pool */
212
213#define FREE_ENV_POOL            0
214#define FREE_ENV_CB              (&Shm_Locked_queues[ FREE_ENV_POOL ])
215
216/*  The following are important when dealing with
217 *  the shared memory communications interface area.
218 *
219 *  NOTE: The starting address and length of the shared memory
220 *        is defined in a system dependent file.
221 */
222
223#define START_NS_CBS     ((void *)Shm_Configuration->base)
224#define START_LQ_CBS     ((START_NS_CBS) + \
225        ( (sizeof (Shm_Node_status_control)) * (Shm_Maximum_nodes + 1) ) )
226#define START_ENVELOPES  ( ((void *) START_LQ_CBS) + \
227        ( (sizeof (Shm_Locked_queue_Control)) * (Shm_Maximum_nodes + 1) ) )
228#define END_SHMCI_AREA    ( (void *) START_ENVELOPES + \
229        ( (sizeof (Shm_Envelope_control)) * Shm_Maximum_envelopes ) )
230#define END_SHARED_MEM   (START_NS_CBS+Shm_Configuration->length)
231
232/* macros */
233
234#define Shm_Is_master_node()  \
235  ( SHM_MASTER == Shm_Local_node )
236
237#define Shm_Free_envelope( ecb ) \
238  Shm_Locked_queue_Add( FREE_ENV_CB, (ecb) )
239#define Shm_Allocate_envelope() \
240  Shm_Locked_queue_Get(FREE_ENV_CB)
241
242#define Shm_Initialize_receive_queue(node) \
243  Shm_Locked_queue_Initialize( &Shm_Locked_queues[node], node )
244
245#define Shm_Append_to_receive_queue(node, ecb) \
246  Shm_Locked_queue_Add( &Shm_Locked_queues[node], (ecb) )
247
248#define Shm_Envelope_control_to_packet_prefix_pointer(ecb)  \
249   ((void *)(ecb)->packet)
250
251#define Shm_Packet_prefix_to_envelope_control_pointer( pkt )   \
252   ((Shm_Envelope_control *)((rtems_unsigned8 *)(pkt) - \
253   (sizeof(Shm_Envelope_preamble) + SHM_ENVELOPE_PREFIX_OVERHEAD)))
254
255#define Shm_Build_preamble(ecb, node) \
256       (ecb)->Preamble.endian = Shm_Configuration->format
257
258#define Shm_Build_postamble( ecb )
259
260/* volatile types */
261
262typedef volatile rtems_unsigned8  vol_u8;
263typedef volatile rtems_unsigned32 vol_u32;
264
265/* shm control information */
266
267struct shm_info {
268  vol_u32 not_currently_used_0;
269  vol_u32 not_currently_used_1;
270  vol_u32 not_currently_used_2;
271  vol_u32 not_currently_used_3;
272};
273
274typedef struct {
275  /*byte start_of_text;*/
276  vol_u32 endian;
277  vol_u32 not_currently_used_0;
278  vol_u32 not_currently_used_1;
279  vol_u32 not_currently_used_2;
280} Shm_Envelope_preamble;
281
282typedef struct {
283} Shm_Envelope_postamble;
284
285/* WARNING! If you change this structure, don't forget to change
286 *          SHM_ENVELOPE_PREFIX_OVERHEAD and
287 *          Shm_Packet_prefix_to_envelope_control_pointer() above.
288 */
289
290/*  This comment block describes the contents of each field
291 *  of the Envelope Control Block:
292 *
293 *  next      - The index of the next envelope on this queue.
294 *  queue     - The index of the queue this envelope is on.
295 *  index     - The index of this envelope.
296 *  Preamble  - Generic packet preamble.  One day this structure
297 *              could be enhanced to contain routing information.
298 *  packet    - RTEMS MPCI packet.  Untouched by SHM Driver
299 *              other than copying and format conversion as
300 *              documented in the RTEMS User's Guide.
301 *  Postamble - Generic packet postamble.  One day this structure
302 *              could be enhanced to contain checksum information.
303 */
304
305typedef struct {
306  vol_u32           next;     /* next envelope on queue       */
307  vol_u32           queue;    /* queue on which this resides  */
308  vol_u32           index;    /* index into array of envelopes*/
309  vol_u32           pad0;     /* insure the next one is aligned */
310  Shm_Envelope_preamble    Preamble; /* header information           */
311  vol_u8            packet[MAX_PACKET_SIZE]; /* RTEMS INFO    */
312  Shm_Envelope_postamble   Postamble;/* trailer information          */
313} Shm_Envelope_control;
314
315/*  This comment block describes the contents of each field
316 *  of the Locked Queue Control Block:
317 *
318 *  lock      - Lock used to insure mutually exclusive access.
319 *  front     - Index of first envelope on queue.  This field
320 *              is used to remove head of queue (receive).
321 *  rear      - Index of last envelope on queue.  This field
322 *              is used to add evelope to queue (send).
323 *  owner     - The node number of the recipient (owning) node.
324 *              RTEMS does not use the node number zero (0).
325 *              The zero node is used by the SHM Driver for the
326 *              Free Envelope Queue shared by all nodes.
327 */
328
329typedef struct {
330  vol_u32 lock;  /* lock field for this queue    */
331  vol_u32 front; /* first envelope on queue      */
332  vol_u32 rear;  /* last envelope on queue       */
333  vol_u32 owner; /* receiving (i.e. owning) node */
334} Shm_Locked_queue_Control;
335
336/*  This comment block describes the contents of each field
337 *  of the Node Status Control Block:
338 *
339 *  status    - Node status.  Current values are Pending Initialization,
340 *              Initialization Complete, and Active Node.  Other values
341 *              could be added to enhance fault tolerance.
342 *  error     - Zero if the node has not failed.  Otherwise,
343 *              this field contains a status indicating the
344 *              failure reason.
345 *  int_address, int_value, and int_length
346 *            - These field are the Interrupt Information table
347 *              for this node in neutral format.  This is how
348 *              each node knows how to generate interrupts.
349 */
350
351typedef struct {
352  vol_u32  status;         /* node status information     */
353  vol_u32  error;          /* fatal error code            */
354  vol_u32  int_address;    /* write here for interrupt    */
355  vol_u32  int_value;      /* this value causes interrupt */
356  vol_u32  int_length;     /* for this length (0,1,2,4)   */
357  vol_u32  not_currently_used_0;
358  vol_u32  not_currently_used_1;
359  vol_u32  not_currently_used_2;
360} Shm_Node_status_control;
361
362/*  This comment block describes the contents of each field
363 *  of the Interrupt Information Table.  This table describes
364 *  how another node can generate an interrupt to this node.
365 *  This information is target board dependent.  If the
366 *  SHM Driver is in POLLED_MODE, then all fields should
367 *  be initialized to NO_INTERRUPT.
368 *
369 *  address   - The address to which another node should
370 *              write to cause an interrupt.
371 *  value     - The value which must be written
372 *  length    - The size of the value to write.  Valid
373 *              values are BYTE, WORD, and LONG.
374 *
375 *  NOTE:  The Node Status Control Block contains this
376 *         information in neutral format and not in a
377 *         structure to avoid potential alignment problems.
378 */
379
380typedef struct {
381  vol_u32 *address;        /* write here for interrupt    */
382  vol_u32  value;          /* this value causes interrupt */
383  vol_u32  length;         /* for this length (0,1,2,4)   */
384} Shm_Interrupt_information;
385
386/*  SHM Configuration Table
387 *
388 *  This comment block describes the contents of each field
389 *  of the SHM Configuration Table.
390 *
391 *  base       - The base address of the shared memory.  This
392 *               address may be specific to this node.
393 *  length     - The length of the shared memory in bytes.
394 *  format     - The natural format for rtems_unsigned32's in the
395 *               shared memory.  Valid values are currently
396 *               only SHM_LITTLE and SHM_BIG.
397 *  convert    - The address of the routine which converts
398 *               between neutral and local format.
399 *  poll_intr  - The operational mode of the driver.  Some
400 *               target boards may not provide hardware for
401 *               an interprocessor interrupt.  If POLLED_MODE
402 *               is selected, the SHM driver will install a
403 *               wrapper around the Clock_isr() to poll for
404 *               incoming packets.  Throughput is dependent
405 *               on the time between clock interrupts.
406 *               Valid values are POLLED_MODE and INTR_MODE.
407 *  cause_intr - This is the address of the routine used to
408 *               write to a particular address and cause an
409 *               interrupt on another node.  This routine
410 *               may need to be target dependent if something
411 *               other than a normal write from C does not work.
412 *  Intr       - This structure describes the operation required
413 *               to cause an interrupt to this node.  The actual
414 *               contents of this structure are described above.
415 */
416
417struct shm_config_info {
418  vol_u32           *base;     /* base address of SHM         */
419  vol_u32            length;   /* length (in bytes) of SHM    */
420  vol_u32            format;   /* SHM is big or little endian */
421  vol_u32          (*convert)();/* neutral conversion routine */
422  vol_u32            poll_intr;/* POLLED or INTR driven mode  */
423  void             (*cause_intr)( rtems_unsigned32 );
424  Shm_Interrupt_information   Intr;     /* cause intr information      */
425};
426
427typedef struct shm_config_info shm_config_table;
428
429/* global variables */
430
431#ifdef _SHM_INIT
432#define SHM_EXTERN
433#else
434#define SHM_EXTERN extern
435#endif
436
437SHM_EXTERN shm_config_table             *Shm_Configuration;
438SHM_EXTERN Shm_Interrupt_information    *Shm_Interrupt_table;
439SHM_EXTERN Shm_Node_status_control      *Shm_Node_statuses;
440SHM_EXTERN Shm_Locked_queue_Control     *Shm_Locked_queues;
441SHM_EXTERN Shm_Envelope_control         *Shm_Envelopes;
442SHM_EXTERN rtems_configuration_table    *Shm_RTEMS_Configuration;
443SHM_EXTERN rtems_multiprocessing_table  *Shm_RTEMS_MP_Configuration;
444SHM_EXTERN rtems_unsigned32              Shm_Receive_message_count;
445SHM_EXTERN rtems_unsigned32              Shm_Null_message_count;
446SHM_EXTERN rtems_unsigned32              Shm_Interrupt_count;
447SHM_EXTERN rtems_unsigned32              Shm_Local_node;
448SHM_EXTERN Shm_Locked_queue_Control      *Shm_Local_receive_queue;
449SHM_EXTERN Shm_Node_status_control       *Shm_Local_node_status;
450SHM_EXTERN rtems_unsigned32              Shm_isrstat;
451                                                     /* reported by shmdr */
452
453SHM_EXTERN rtems_unsigned32 Shm_Pending_initialization;
454SHM_EXTERN rtems_unsigned32 Shm_Initialization_complete;
455SHM_EXTERN rtems_unsigned32 Shm_Active_node;
456
457SHM_EXTERN rtems_unsigned32 Shm_Maximum_nodes;
458SHM_EXTERN rtems_unsigned32 Shm_Maximum_envelopes;
459
460SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_End_of_list;
461SHM_EXTERN rtems_unsigned32 Shm_Locked_queue_Not_on_list;
462
463/* functions */
464
465/* locked queue routines */
466void           Shm_Locked_queue_Add(
467                  Shm_Locked_queue_Control *, Shm_Envelope_control * );
468Shm_Envelope_control *Shm_Locked_queue_Get( Shm_Locked_queue_Control * );
469void           Shm_Locked_queue_Initialize(
470                  Shm_Locked_queue_Control *, rtems_unsigned32 );
471            /* Shm_Initialize_lock is CPU dependent */
472            /* Shm_Lock is CPU dependent */
473            /* Shm_Unlock is CPU dependent */
474
475/* portable routines */
476void           Init_env_pool();
477void           Shm_Print_statistics( void );
478void           MPCI_Fatal( Internal_errors_Source, boolean, rtems_unsigned32 );
479rtems_task     Shm_Cause_interrupt( rtems_unsigned32 );
480void           Shm_Poll();
481void           Shm_setclockvec();
482void           Shm_Convert_packet( rtems_packet_prefix * );
483
484/* CPU specific routines are inlined in shmcpu.h */
485
486/* target specific routines */
487void          *Shm_Convert_address( void * );
488void           Shm_Get_configuration( rtems_unsigned32, shm_config_table ** );
489void           Shm_isr();
490void           Shm_setvec( void );
491
492void           Shm_Initialize_lock( Shm_Locked_queue_Control * );
493void           Shm_Lock( Shm_Locked_queue_Control * );
494void           Shm_Unlock( Shm_Locked_queue_Control * );
495
496/* MPCI entry points */
497rtems_mpci_entry Shm_Get_packet(
498  rtems_packet_prefix **
499);
500
501rtems_mpci_entry Shm_Initialization( void );
502
503rtems_mpci_entry Shm_Receive_packet(
504  rtems_packet_prefix **
505);
506
507rtems_mpci_entry Shm_Return_packet(
508  rtems_packet_prefix *
509);
510
511rtems_mpci_entry Shm_Send_packet(
512  rtems_unsigned32,
513  rtems_packet_prefix *
514);
515
516extern rtems_mpci_table MPCI_table;
517
518#ifdef _SHM_INIT
519
520/* multiprocessor communications interface (MPCI) table */
521
522rtems_mpci_table MPCI_table  = {
523  100000,                     /* default timeout value in ticks */
524  MAX_PACKET_SIZE,            /* maximum packet size */
525  Shm_Initialization,         /* initialization procedure   */
526  Shm_Get_packet,             /* get packet procedure       */
527  Shm_Return_packet,          /* return packet procedure    */
528  Shm_Send_packet,            /* packet send procedure      */
529  Shm_Receive_packet          /* packet receive procedure   */
530};
531
532#endif
533
534#ifdef __cplusplus
535}
536#endif
537
538#endif
539/* end of include file */
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