source: rtems/c/src/lib/libbsp/shared/vmeUniverse/vmeUniverse.h @ afd4c7b

4.104.114.84.95
Last change on this file since afd4c7b was afd4c7b, checked in by Till Straumann <strauman@…>, on 12/13/06 at 20:04:05
  • vmeUniverse/vme_am_defs.h: Added address modifiers for 2eVME. Added flags for 2eSST and DBW16.
  • vmeUniverse/vmeUniverse.h: Removed AM definitions and include vme_am_defs.h instead. Declare new routine vmeUniverseMapCRG(). Export 'irq manager' API only if INSIDE_RTEMS_BSP defined. Renamed 'shared' argument to vmeUniverseInstallIrqMgrAlt() to 'flags' since now more options are available. Added new flag to install 'posted-write' workaround.
  • vmeUniverse/vmeUniverse.c: Allow BSP to override BSP_PCI2LOCAL_ADDR() macro. Data width of outbound port can now be restricted to 16-bit (if new DBW16 flag set in address modifier). Added vmeUniverseMapCRG() for mapping local registers onto VME. Interrupt manager now implements a workaround (enabled at installation time) which flushes the write-fifo after user ISR returns. This requires the universe's registers to be accessible from VME (either CSR space or CRG mapped to A16/A24/A32), though.
  • vmeUniverse/vmeTsi148.h: vmeTsi148ClearVMEBusErrors() now returns the fault address as a 32-bit address (not ulonglong anymore). The driver only supports 32-bit addresses. Declare new routine vmeTsi148MapCRG(). Export 'irq manager' API only if INSIDE_RTEMS_BSP defined. Renamed 'shared' argument to vmeTsi148InstallIrqMgrAlt() to 'flags' to allow more options to be supported. Added comments explaining the 'posted-write' workaround implemented by the interrupt manager.
  • vmeUniverse/vmeTsi148.c: Clear 'SYSFAIL' during initialization. Allow BSP to override BSP_PCI2LOCAL_ADDR() macro. Added support for 2eSST when configuring windows (untested - I have no 2eSST). Added vmeTsi148MapCRG() for mapping local registers onto VME. Implemented 'posted-write' workaround for interrupt manager (consult source for details).
  • Property mode set to 100644
File size: 41.0 KB
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1/* $Id$ */
2#ifndef VME_UNIVERSE_UTIL_H
3#define VME_UNIVERSE_UTIL_H
4
5/* Routines to configure and use the Tundra Universe VME bridge
6 * Author: Till Straumann <strauman@slac.stanford.edu>
7 *         Nov 2000, July 2001
8 */
9
10/* Register definitions */
11/* NOTE: all registers contents in PCI space are LITTLE ENDIAN */
12
13#ifdef __vxworks
14#include <vme.h>
15#else
16
17#include <bsp/vme_am_defs.h>
18
19#endif
20
21/* These bits can be or'ed with the address-modifier when calling
22 * the 'XlateAddr' routine below to further qualify the
23 * search criteria.
24 */
25#define VME_MODE_MATCH_MASK                                     (3<<30)
26#define VME_MODE_EXACT_MATCH                            (2<<30) /* all bits must match */
27#define VME_MODE_AS_MATCH                                       (1<<30) /* only A16/24/32 must match */
28
29
30typedef unsigned long LERegister; /* emphasize contents are little endian */
31
32/* NOTE: DMA packet descriptors MUST be 32 byte aligned */
33typedef struct VmeUniverseDMAPacketRec_ {
34        LERegister      dctl    __attribute__((aligned(32)));
35        LERegister      dtbc    __attribute__((packed));
36        LERegister      dla             __attribute__((packed));
37        LERegister      dummy1  __attribute__((packed));
38        LERegister      dva             __attribute__((packed));
39        LERegister      dummy2  __attribute__((packed));
40        LERegister      dcpp    __attribute__((packed));
41        LERegister      dummy3  __attribute__((packed));
42} VmeUniverseDMAPacketRec, *VmeUniverseDMAPacket;
43
44/* PCI CSR register */
45#define         UNIV_REGOFF_PCI_CSR             0x4
46# define        UNIV_PCI_CSR_D_PE               (1<<31) /* detected parity error; write 1 to clear */
47# define        UNIV_PCI_CSR_S_SERR             (1<<30) /* SERR (signalled error) asserted; write 1 to clear */
48# define        UNIV_PCI_CSR_R_MA               (1<<29) /* received master abort; write 1 to clear */
49# define        UNIV_PCI_CSR_R_TA               (1<<28) /* received target abort; write 1 to clear */
50# define        UNIV_PCI_CSR_S_TA               (1<<27) /* signalled target abort; write 1 to clear */
51# define        UNIV_PCI_CSR_DEVSEL_MASK (3<<25)        /* device select timing (RO) */
52# define        UNIV_PCI_CSR_DP_D               (1<<24) /* data parity error detected; write 1 to clear */
53# define        UNIV_PCI_CSR_TFBBC              (1<<23) /* target fast back to back capable (RO) */
54# define        UNIV_PCI_CSR_MFBBC              (1<<9)  /* master fast back to back capable (RO) */
55# define        UNIV_PCI_CSR_SERR_EN    (1<<8)  /* enable SERR driver */
56# define        UNIV_PCI_CSR_WAIT               (1<<7)  /* wait cycle control (RO) */
57# define        UNIV_PCI_CSR_PERESP             (1<<6)  /* parity error response enable */
58# define        UNIV_PCI_CSR_VGAPS              (1<<5)  /* VGA palette snoop (RO) */
59# define        UNIV_PCI_CSR_MWI_EN             (1<<4)  /* Memory write and invalidate enable (RO) */
60# define        UNIV_PCI_CSR_SC                 (1<<3)  /* special cycles (RO) */
61# define        UNIV_PCI_CSR_BM                 (1<<2)  /* master enable (MUST SET TO ENABLE VME SLAVES) */
62# define        UNIV_PCI_CSR_MS                 (1<<1)  /* target memory enable */
63# define        UNIV_PCI_CSR_IOS                (1<<0)  /* target IO enable */
64
65/* Special cycle (ADOH, RMW) control register */
66#define         UNIV_REGOFF_SCYC_CTL    0x170   /* write 0 to disable */
67# define        UNIV_SCYC_CTL_LAS_IO    (1<<2)  /* PCI address space (1: IO, 0: mem) */
68# define        UNIV_SCYC_CTL_SCYC_RMW  (1<<0)  /* do a RMW cycle when reading  PCI address */
69# define        UNIV_SCYC_CTL_SCYC_ADOH (2<<0)  /* do a ADOH cycle when reading/writing  PCI address */
70
71/* Special cycle address register */
72#define         UNIV_REGOFF_SCYC_ADDR   0x174   /* PCI address (must be long word aligned) */
73
74/* Special cycle Swap/Compare/Enable */
75#define         UNIV_REGOFF_SCYC_EN     0x178   /* mask determining the bits involved in the compare and swap operations for VME RMW cycles */
76
77/* Special cycle compare data register */
78#define         UNIV_REGOFF_SCYC_CMP    0x17c   /* data to compare with word returned from VME RMW read */
79
80/* Special cycle swap data register */
81#define         UNIV_REGOFF_SCYC_SWP    0x180   /* If enabled bits of CMP match, corresponding SWP bits are written back to VME (under control of EN) */
82
83/* PCI miscellaneous register */
84#define         UNIV_REGOFF_LMISC       0x184
85# define        UNIV_LMISC_CRT_MASK     (7<<28) /* Univ. I only, not used on II */
86# define        UNIV_LMISC_CRT_INF      (0<<28) /* Coupled Request Timeout */
87# define        UNIV_LMISC_CRT_128_US   (1<<28) /* Coupled Request Timeout */
88# define        UNIV_LMISC_CRT_256_US   (2<<28) /* Coupled Request Timeout */
89# define        UNIV_LMISC_CRT_512_US   (3<<28) /* Coupled Request Timeout */
90# define        UNIV_LMISC_CRT_1024_US  (4<<28) /* Coupled Request Timeout */
91# define        UNIV_LMISC_CRT_2048_US  (5<<28) /* Coupled Request Timeout */
92# define        UNIV_LMISC_CRT_4096_US  (6<<28) /* Coupled Request Timeout */
93
94# define        UNIV_LMISC_CWT_MASK     (7<<24) /* coupled window timer */
95# define        UNIV_LMISC_CWT_DISABLE  0       /* disabled (release VME after 1 coupled xaction) */
96# define        UNIV_LMISC_CWT_16       (1<<24) /* 16 PCI clock cycles */
97# define        UNIV_LMISC_CWT_32       (2<<24) /* 32 PCI clock cycles */
98# define        UNIV_LMISC_CWT_64       (3<<24) /* 64 PCI clock cycles */
99# define        UNIV_LMISC_CWT_128      (4<<24) /* 128 PCI clock cycles */
100# define        UNIV_LMISC_CWT_256      (5<<24) /* 256 PCI clock cycles */
101# define        UNIV_LMISC_CWT_512      (6<<24) /* 512 PCI clock cycles */
102
103/* PCI Command Error Log Register */
104#define         UNIV_REGOFF_L_CMDERR    0x18c
105# define        UNIV_L_CMDERR_CMDERR(reg) (((reg)>>28)&0xf) /* extract PCI cmd error log */
106# define        UNIV_L_CMDERR_M_ERR     (1<<27) /* multiple errors have occurred */
107# define        UNIV_L_CMDERR_L_STAT    (1<<23) /* PCI error log status valid (write 1 to clear and enable logging) */
108
109/* PCI Address Error Log */
110#define         UNIV_REGOFF_LAERR       0x190   /* PCI fault address (if L_CMDERR_L_STAT valid) */
111/* DMA Xfer Control Register */
112#define         UNIV_REGOFF_DCTL        0x200
113# define        UNIV_DCTL_L2V           (1<<31) /* PCI->VME if set */
114# define        UNIV_DCTL_VDW_MSK       (3<<22) /* VME max. width mask 0x00c00000 */
115# define        UNIV_DCTL_VDW_8         (0<<22) /* VME max. width 8 */
116# define        UNIV_DCTL_VDW_16        (1<<22) /* VME max. width 16 */
117# define        UNIV_DCTL_VDW_32        (2<<22) /* VME max. width 32 */
118# define        UNIV_DCTL_VDW_64        (3<<22) /* VME max. width 64 */
119# define        UNIV_DCTL_VAS_MSK       (7<<16) /* VME AS mask 0x00070000 */
120# define        UNIV_DCTL_VAS_A16       (0<<16) /* VME A16 */
121# define        UNIV_DCTL_VAS_A24       (1<<16) /* VME A24 */
122# define        UNIV_DCTL_VAS_A32       (2<<16) /* VME A32 */
123# define        UNIV_DCTL_PGM_MSK       (3<<14) /* VME PGM/DATA mask 0x0000c000 */
124# define        UNIV_DCTL_PGM           (1<<14) /* VME PGM(1)/DATA(0) */
125# define        UNIV_DCTL_SUPER_MSK     (3<<12) /* VME SUPER/USR mask 0x00003000 */
126# define        UNIV_DCTL_SUPER         (1<<12) /* VME SUPER(1)/USR(0) */
127# define        UNIV_DCTL_VCT           (1<<8)  /* VME enable BLT */
128# define        UNIV_DCTL_LD64EN        (1<<7)  /* PCI 64 enable  */
129
130/* DMA Xfer byte count register (is updated by DMA) */
131#define         UNIV_REGOFF_DTBC        0x204
132/* DMA Xfer local (PCI) address (direction is  set in DCTL) */
133#define         UNIV_REGOFF_DLA         0x208
134/* DMA Xfer VME address (direction is  set in DCTL)
135 * NOTE: (*UNIV_DVA) & ~7 == (*UNIV_DLA) & ~7 MUST HOLD
136 */
137#define         UNIV_REGOFF_DVA         0x210
138
139/* DMA Xfer VME command packet pointer
140 * NOTE: The address stored here MUST be 32-byte aligned
141 */
142#define         UNIV_REGOFF_DCPP        0x218
143/* these bits are only used in linked lists */
144# define        UNIV_DCPP_IMG_NULL      (1<<0)  /* last packet in list */
145# define        UNIV_DCPP_IMG_PROCESSED (1<<1)  /* packet processed */
146
147/* DMA Xfer General Control/Status register */
148#define         UNIV_REGOFF_DGCS        0x220
149# define        UNIV_DGCS_GO            (1<<31) /* start xfer */
150# define        UNIV_DGCS_STOP_REQ      (1<<30) /* stop xfer (immediate abort) */
151# define        UNIV_DGCS_HALT_REQ      (1<<29) /* halt xfer (abort after current packet) */
152# define        UNIV_DGCS_CHAIN         (1<<27) /* enable linked list mode */
153# define        UNIV_DGCS_VON_MSK       (7<<20) /* VON mask */
154# define        UNIV_DGCS_VON_DONE      (0<<20) /* VON counter disabled (do until done) */
155# define        UNIV_DGCS_VON_256       (1<<20) /* VON yield bus after 256 bytes */
156# define        UNIV_DGCS_VON_512       (2<<20) /* VON yield bus after 512 bytes */
157# define        UNIV_DGCS_VON_1024      (3<<20) /* VON yield bus after 512 bytes */
158# define        UNIV_DGCS_VON_2048      (4<<20) /* VON yield bus after 1024 bytes */
159# define        UNIV_DGCS_VON_4096      (5<<20) /* VON yield bus after 4096 bytes */
160# define        UNIV_DGCS_VON_8192      (6<<20) /* VON yield bus after 8192 bytes */
161# define        UNIV_DGCS_VOFF_MSK      (15<<16) /* VOFF mask */
162# define        UNIV_DGCS_VOFF_0_US     (0<<16) /* re-request VME master after 0 us */
163# define        UNIV_DGCS_VOFF_2_US     (8<<16) /* re-request VME master after 2 us */
164# define        UNIV_DGCS_VOFF_4_US     (9<<16) /* re-request VME master after 4 us */
165# define        UNIV_DGCS_VOFF_8_US     (10<<16)/* re-request VME master after 8 us */
166# define        UNIV_DGCS_VOFF_16_US    (1<<16) /* re-request VME master after 16 us */
167# define        UNIV_DGCS_VOFF_32_US    (2<<16) /* re-request VME master after 32 us */
168# define        UNIV_DGCS_VOFF_64_US    (3<<16) /* re-request VME master after 64 us */
169# define        UNIV_DGCS_VOFF_128_US   (4<<16) /* re-request VME master after 128 us */
170# define        UNIV_DGCS_VOFF_256_US   (5<<16) /* re-request VME master after 256 us */
171# define        UNIV_DGCS_VOFF_512_US   (6<<16) /* re-request VME master after 512 us */
172# define        UNIV_DGCS_VOFF_1024_US  (7<<16) /* re-request VME master after 1024 us */
173/* Status Bits (write 1 to clear) */
174# define        UNIV_DGCS_ACT           (1<<15) /* DMA active */
175# define        UNIV_DGCS_STOP          (1<<14) /* DMA stopped */
176# define        UNIV_DGCS_HALT          (1<<13) /* DMA halted */
177# define        UNIV_DGCS_DONE          (1<<11) /* DMA done (OK) */
178# define        UNIV_DGCS_LERR          (1<<10) /* PCI bus error */
179# define        UNIV_DGCS_VERR          (1<<9)  /* VME bus error */
180# define        UNIV_DGCS_P_ERR         (1<<8)  /* programming protocol error (e.g. PCI master disabled) */
181# define        UNIV_DGCS_STATUS_CLEAR\
182        (UNIV_DGCS_ACT|UNIV_DGCS_STOP|UNIV_DGCS_HALT|\
183         UNIV_DGCS_DONE|UNIV_DGCS_LERR|UNIV_DGCS_VERR|UNIV_DGCS_P_ERR)
184# define        UNIV_DGCS_P_ERR         (1<<8)  /* programming protocol error (e.g. PCI master disabled) */
185/* Interrupt Mask Bits */
186# define        UNIV_DGCS_INT_STOP      (1<<6)  /* interrupt when stopped */
187# define        UNIV_DGCS_INT_HALT      (1<<5)  /* interrupt when halted */
188# define        UNIV_DGCS_INT_DONE      (1<<3)  /* interrupt when done */
189# define        UNIV_DGCS_INT_LERR      (1<<2)  /* interrupt on LERR */
190# define        UNIV_DGCS_INT_VERR      (1<<1)  /* interrupt on VERR */
191# define        UNIV_DGCS_INT_P_ERR     (1<<0)  /* interrupt on P_ERR */
192# define        UNIV_DGCS_INT_MSK       (0x0000006f) /* interrupt mask */
193
194/* DMA Linked List Update Enable Register */
195#define         UNIV_REGOFF_D_LLUE      0x224
196# define        UNIV_D_LLUE_UPDATE      (1<<31)
197
198
199/* PCI (local) interrupt enable register */
200#define         UNIV_REGOFF_LINT_EN     0x300
201# define        UNIV_LINT_EN_LM3        (1<<23) /* location monitor 3 mask */
202# define        UNIV_LINT_EN_LM2        (1<<22) /* location monitor 2 mask */
203# define        UNIV_LINT_EN_LM1        (1<<21) /* location monitor 1 mask */
204# define        UNIV_LINT_EN_LM0        (1<<20) /* location monitor 0 mask */
205# define        UNIV_LINT_EN_MBOX3      (1<<19) /* mailbox 3 mask */
206# define        UNIV_LINT_EN_MBOX2      (1<<18) /* mailbox 2 mask */
207# define        UNIV_LINT_EN_MBOX1      (1<<17) /* mailbox 1 mask */
208# define        UNIV_LINT_EN_MBOX0      (1<<16) /* mailbox 0 mask */
209# define        UNIV_LINT_EN_ACFAIL     (1<<15) /* ACFAIL irq mask */
210# define        UNIV_LINT_EN_SYSFAIL    (1<<14) /* SYSFAIL irq mask */
211# define        UNIV_LINT_EN_SW_INT     (1<<13) /* PCI (local) software irq */
212# define        UNIV_LINT_EN_SW_IACK    (1<<12) /* VME software IACK mask */
213# define        UNIV_LINT_EN_VERR       (1<<10) /* PCI VERR irq mask */
214# define        UNIV_LINT_EN_LERR       (1<<9)  /* PCI LERR irq mask */
215# define        UNIV_LINT_EN_DMA        (1<<8)  /* PCI DMA irq mask */
216# define        UNIV_LINT_EN_VIRQ7      (1<<7)  /* VIRQ7 mask (universe does IACK automatically) */
217# define        UNIV_LINT_EN_VIRQ6      (1<<6)  /* VIRQ6 mask */
218# define        UNIV_LINT_EN_VIRQ5      (1<<5)  /* VIRQ5 mask */
219# define        UNIV_LINT_EN_VIRQ4      (1<<4)  /* VIRQ4 mask */
220# define        UNIV_LINT_EN_VIRQ3      (1<<3)  /* VIRQ3 mask */
221# define        UNIV_LINT_EN_VIRQ2      (1<<2)  /* VIRQ2 mask */
222# define        UNIV_LINT_EN_VIRQ1      (1<<1)  /* VIRQ1 mask */
223# define        UNIV_LINT_EN_VOWN       (1<<0)  /* VOWN mask */
224
225/* PCI (local) interrupt status register */
226#define         UNIV_REGOFF_LINT_STAT   0x304
227# define        UNIV_LINT_STAT_LM3      (1<<23) /* location monitor 3 status */
228# define        UNIV_LINT_STAT_LM2      (1<<22) /* location monitor 2 status */
229# define        UNIV_LINT_STAT_LM1      (1<<21) /* location monitor 1 status */
230# define        UNIV_LINT_STAT_LM0      (1<<20) /* location monitor 0 status */
231# define        UNIV_LINT_STAT_MBOX3    (1<<19) /* mailbox 3 status */
232# define        UNIV_LINT_STAT_MBOX2    (1<<18) /* mailbox 2 status */
233# define        UNIV_LINT_STAT_MBOX1    (1<<17) /* mailbox 1 status */
234# define        UNIV_LINT_STAT_MBOX0    (1<<16) /* mailbox 0 status */
235# define        UNIV_LINT_STAT_ACFAIL   (1<<15) /* ACFAIL irq status */
236# define        UNIV_LINT_STAT_SYSFAIL  (1<<14) /* SYSFAIL irq status */
237# define        UNIV_LINT_STAT_SW_INT   (1<<13) /* PCI (local) software irq */
238# define        UNIV_LINT_STAT_SW_IACK  (1<<12) /* VME software IACK status */
239# define        UNIV_LINT_STAT_VERR             (1<<10) /* PCI VERR irq status */
240# define        UNIV_LINT_STAT_LERR             (1<<9)  /* PCI LERR irq status */
241# define        UNIV_LINT_STAT_DMA              (1<<8)  /* PCI DMA irq status */
242# define        UNIV_LINT_STAT_VIRQ7    (1<<7)  /* VIRQ7 status */
243# define        UNIV_LINT_STAT_VIRQ6    (1<<6)  /* VIRQ6 status */
244# define        UNIV_LINT_STAT_VIRQ5    (1<<5)  /* VIRQ5 status */
245# define        UNIV_LINT_STAT_VIRQ4    (1<<4)  /* VIRQ4 status */
246# define        UNIV_LINT_STAT_VIRQ3    (1<<3)  /* VIRQ3 status */
247# define        UNIV_LINT_STAT_VIRQ2    (1<<2)  /* VIRQ2 status */
248# define        UNIV_LINT_STAT_VIRQ1    (1<<1)  /* VIRQ1 status */
249# define        UNIV_LINT_STAT_VOWN             (1<<0)  /* VOWN status */
250# define        UNIV_LINT_STAT_CLR              (0xfff7ff)/* Clear all status bits */
251
252/* PCI (local) interrupt map 0 register */
253#define         UNIV_REGOFF_LINT_MAP0   0x308   /* mapping of VME IRQ sources to PCI irqs */
254# define        UNIV_LINT_MAP0_VIRQ7(lint)      (((lint)&0x7)<<(7*4))
255# define        UNIV_LINT_MAP0_VIRQ6(lint)      (((lint)&0x7)<<(6*4))
256# define        UNIV_LINT_MAP0_VIRQ5(lint)      (((lint)&0x7)<<(5*4))
257# define        UNIV_LINT_MAP0_VIRQ4(lint)      (((lint)&0x7)<<(4*4))
258# define        UNIV_LINT_MAP0_VIRQ3(lint)      (((lint)&0x7)<<(3*4))
259# define        UNIV_LINT_MAP0_VIRQ2(lint)      (((lint)&0x7)<<(2*4))
260# define        UNIV_LINT_MAP0_VIRQ1(lint)      (((lint)&0x7)<<(1*4))
261# define        UNIV_LINT_MAP0_VOWN(lint)       (((lint)&0x7)<<(0*4))
262
263#define         UNIV_REGOFF_LINT_MAP1   0x30c   /* mapping of internal / VME IRQ sources to PCI irqs */
264# define        UNIV_LINT_MAP1_ACFAIL(lint)     (((lint)&0x7)<<(7*4))
265# define        UNIV_LINT_MAP1_SYSFAIL(lint)    (((lint)&0x7)<<(6*4))
266# define        UNIV_LINT_MAP1_SW_INT(lint)     (((lint)&0x7)<<(5*4))
267# define        UNIV_LINT_MAP1_SW_IACK(lint)    (((lint)&0x7)<<(4*4))
268# define        UNIV_LINT_MAP1_VERR(lint)       (((lint)&0x7)<<(2*4))
269# define        UNIV_LINT_MAP1_LERR(lint)       (((lint)&0x7)<<(1*4))
270# define        UNIV_LINT_MAP1_DMA(lint)        (((lint)&0x7)<<(0*4))
271
272/* enabling of generation of VME bus IRQs, TODO */
273#define         UNIV_REGOFF_VINT_EN             0x310
274# define        UNIV_VINT_EN_DISABLE_ALL    0
275# define        UNIV_VINT_EN_SWINT                      (1<<12)
276# define        UNIV_VINT_EN_SWINT_LVL(l)       (1<<(((l)&7)+24))       /* universe II only */
277
278
279/* status of generation of VME bus IRQs */
280#define         UNIV_REGOFF_VINT_STAT   0x314
281# define        UNIV_VINT_STAT_LINT(lint)       (1<<((lint)&7))
282# define        UNIV_VINT_STAT_LINT_MASK        (0xff)
283# define        UNIV_VINT_STAT_CLR                      (0xfe0f17ff)
284# define        UNIV_VINT_STAT_SWINT(l)     (1<<(((l)&7)+24))
285
286#define         UNIV_REGOFF_VINT_MAP0   0x318   /* VME destination of PCI IRQ source, TODO */
287
288#define         UNIV_REGOFF_VINT_MAP1   0x31c   /* VME destination of PCI IRQ source, TODO */
289# define        UNIV_VINT_MAP1_SWINT(level)     (((level)&0x7)<<16)
290
291/* NOTE: The universe seems to always set LSB (which has a special purpose in
292 *       the STATID register: enable raising a SW_INT on IACK) on the
293 *               vector it puts out on the bus...
294 */
295#define         UNIV_REGOFF_VINT_STATID 0x320   /* our status/id response to IACK, TODO */
296# define        UNIV_VINT_STATID(id)        ((id)<<24)
297
298#define         UNIV_REGOFF_VIRQ1_STATID 0x324  /* status/id of VME IRQ level 1 */
299#define         UNIV_REGOFF_VIRQ2_STATID 0x328  /* status/id of VME IRQ level 2 */
300#define         UNIV_REGOFF_VIRQ3_STATID 0x32c  /* status/id of VME IRQ level 3 */
301#define         UNIV_REGOFF_VIRQ4_STATID 0x330  /* status/id of VME IRQ level 4 */
302#define         UNIV_REGOFF_VIRQ5_STATID 0x334  /* status/id of VME IRQ level 5 */
303#define         UNIV_REGOFF_VIRQ6_STATID 0x338  /* status/id of VME IRQ level 6 */
304#define         UNIV_REGOFF_VIRQ7_STATID 0x33c  /* status/id of VME IRQ level 7 */
305# define        UNIV_VIRQ_ERR                   (1<<8)  /* set if universe encountered a bus error when doing IACK */
306# define        UNIV_VIRQ_STATID_MASK           (0xff)
307
308#define         UNIV_REGOFF_LINT_MAP2   0x340   /* mapping of internal sources to PCI irqs */
309# define        UNIV_LINT_MAP2_LM3(lint)        (((lint)&0x7)<<7*4)     /* location monitor 3 */
310# define        UNIV_LINT_MAP2_LM2(lint)        (((lint)&0x7)<<6*4)     /* location monitor 2 */
311# define        UNIV_LINT_MAP2_LM1(lint)        (((lint)&0x7)<<5*4)     /* location monitor 1 */
312# define        UNIV_LINT_MAP2_LM0(lint)        (((lint)&0x7)<<4*4)     /* location monitor 0 */
313# define        UNIV_LINT_MAP2_MBOX3(lint)      (((lint)&0x7)<<3*4)     /* mailbox 3 */
314# define        UNIV_LINT_MAP2_MBOX2(lint)      (((lint)&0x7)<<2*4)     /* mailbox 2 */
315# define        UNIV_LINT_MAP2_MBOX1(lint)      (((lint)&0x7)<<1*4)     /* mailbox 1 */
316# define        UNIV_LINT_MAP2_MBOX0(lint)      (((lint)&0x7)<<0*4)     /* mailbox 0 */
317
318#define         UNIV_REGOFF_VINT_MAP2   0x344   /* mapping of internal sources to VME irqs */
319# define        UNIV_VINT_MAP2_MBOX3(vint)      (((vint)&0x7)<<3*4)     /* mailbox 3 */
320# define        UNIV_VINT_MAP2_MBOX2(vint)      (((vint)&0x7)<<2*4)     /* mailbox 2 */
321# define        UNIV_VINT_MAP2_MBOX1(vint)      (((vint)&0x7)<<1*4)     /* mailbox 1 */
322# define        UNIV_VINT_MAP2_MBOX0(vint)      (((vint)&0x7)<<0*4)     /* mailbox 0 */
323
324#define         UNIV_REGOFF_MBOX0       0x348   /* mailbox 0 */
325#define         UNIV_REGOFF_MBOX1       0x34c   /* mailbox 1 */
326#define         UNIV_REGOFF_MBOX2       0x350   /* mailbox 2 */
327#define         UNIV_REGOFF_MBOX3       0x354   /* mailbox 3 */
328
329#define         UNIV_REGOFF_SEMA0       0x358   /* semaphore 0 */
330#define         UNIV_REGOFF_SEMA1       0x35c   /* semaphore 0 */
331/* TODO define semaphore register bits */
332
333#define         UNIV_REGOFF_MAST_CTL    0x400   /* master control register */
334# define        UNIV_MAST_CTL_MAXRTRY(val)      (((val)&0xf)<<7*4)      /* max # of pci master retries */
335# define        UNIV_MAST_CTL_PWON(val)         (((val)&0xf)<<6*4)      /* posted write xfer count */
336# define        UNIV_MAST_CTL_VRL(val)          (((val)&0x3)<<22)       /* VME bus request level */
337# define        UNIV_MAST_CTL_VRM                       (1<<21) /* bus request mode (demand = 0, fair = 1) */
338# define        UNIV_MAST_CTL_VREL                      (1<<20) /* bus release mode (when done = 0, on request = 1) */
339# define        UNIV_MAST_CTL_VOWN                      (1<<19) /* bus ownership (release = 0, acquire/hold = 1) */
340# define        UNIV_MAST_CTL_VOWN_ACK          (1<<18) /* bus ownership (not owned = 0, acquired/held = 1) */
341# define        UNIV_MAST_CTL_PABS(val)         (((val)&0x3)<<3*4)      /* PCI aligned burst size (32,64,128 byte / 0x3 is reserved) */
342# define        UNIV_MAST_CTL_BUS_NO(val)       (((val)&0xff)<<0*4)     /* PCI bus number */
343
344#define         UNIV_REGOFF_MISC_CTL    0x404   /* misc control register */
345# define        UNIV_MISC_CTL_VBTO(val)         (((val)&0x7)<<7*4)      /* VME bus timeout (0=disable, 16*2^(val-1) us) */
346# define        UNIV_MISC_CTL_VARB                      (1<<26) /* VME bus arbitration mode (0=round robin, 1= priority) */
347# define        UNIV_MISC_CTL_VARBTO(val)       (((val)&0x3)<<6*4)      /* arbitration time out: disable, 16us, 256us, reserved */
348# define        UNIV_MISC_CTL_SW_LRST           (1<<23) /* software PCI reset */
349# define        UNIV_MISC_CTL_SW_SYSRST         (1<<22) /* software VME reset */
350# define        UNIV_MISC_CTL_BI                        (1<<20) /* BI mode */
351# define        UNIV_MISC_CTL_ENGBI                     (1<<19) /* enable global BI mode initiator */
352# define        UNIV_MISC_CTL_SYSCON            (1<<17) /* (R/W) 1:universe is system controller */
353# define        UNIV_MISC_CTL_V64AUTO           (1<<16) /* (R/W) 1:initiate VME64 auto id slave participation */
354
355/* U2SPEC described in VGM manual */
356/* NOTE: the Joerger vtr10012_8 needs the timing to be tweaked!!!! READt27 must be _no_delay_
357 */
358#define         UNIV_REGOFF_U2SPEC              0x4fc
359# define        UNIV_U2SPEC_DTKFLTR                     (1<<12) /* DTAck filter: 0: slow, better filter; 1: fast, poorer filter */
360# define        UNIV_U2SPEC_MASt11                      (1<<10) /* Master parameter t11 (DS hi time during BLT and MBLTs) */
361# define        UNIV_U2SPEC_READt27_DEFAULT     (0<<8)  /* VME master parameter t27: (latch data after DTAck + 25ns) */
362# define        UNIV_U2SPEC_READt27_FAST        (1<<8)  /* VME master parameter t27: (latch data faster than 25ns)  */
363# define        UNIV_U2SPEC_READt27_NODELAY     (2<<8)  /* VME master parameter t27: (latch data without any delay)  */
364# define        UNIV_U2SPEC_POSt28_FAST         (1<<2)  /* VME slave parameter t28: (faster time of DS to DTAck for posted write) */
365# define        UNIV_U2SPEC_PREt28_FAST         (1<<0)  /* VME slave parameter t28: (faster time of DS to DTAck for prefetch read) */
366
367/* Location Monitor control register */
368#define         UNIV_REGOFF_LM_CTL              0xf64
369# define        UNIV_LM_CTL_EN                          (1<<31) /* image enable */
370# define        UNIV_LM_CTL_PGM                         (1<<23) /* program AM */
371# define        UNIV_LM_CTL_DATA                        (1<<22) /* data AM */
372# define        UNIV_LM_CTL_SUPER                       (1<<21) /* supervisor AM */
373# define        UNIV_LM_CTL_USER                        (1<<20) /* user AM */
374# define        UNIV_LM_CTL_VAS_A16                     (0<<16) /* A16 */
375# define        UNIV_LM_CTL_VAS_A24                     (1<<16) /* A16 */
376# define        UNIV_LM_CTL_VAS_A32                     (2<<16) /* A16 */
377
378/* Location Monitor base address */
379#define         UNIV_REGOFF_LM_BS               0xf68
380
381/* VMEbus register access image control register */
382#define         UNIV_REGOFF_VRAI_CTL    0xf70
383# define        UNIV_VRAI_CTL_EN                        (1<<31) /* image enable */
384# define        UNIV_VRAI_CTL_PGM                       (1<<23) /* program AM */
385# define        UNIV_VRAI_CTL_DATA                      (1<<22) /* data AM */
386# define        UNIV_VRAI_CTL_SUPER                     (1<<21) /* supervisor AM */
387# define        UNIV_VRAI_CTL_USER                      (1<<20) /* user AM */
388# define        UNIV_VRAI_CTL_VAS_A16           (0<<16) /* A16 */
389# define        UNIV_VRAI_CTL_VAS_A24           (1<<16) /* A14 */
390# define        UNIV_VRAI_CTL_VAS_A32           (2<<16) /* A32 */
391# define        UNIV_VRAI_CTL_VAS_MSK           (3<<16)
392
393/* VMEbus register acces image base address register */
394#define         UNIV_REGOFF_VRAI_BS             0xf74
395
396/* VMEbus CSR control register */
397#define         UNIV_REGOFF_VCSR_CTL    0xf80
398# define        UNIV_VCSR_CTL_EN                        (1<<31) /* image enable */
399# define        UNIV_VCSR_CTL_LAS_PCI_MEM       (0<<0)  /* pci mem space */
400# define        UNIV_VCSR_CTL_LAS_PCI_IO        (1<<0)  /* pci IO space */
401# define        UNIV_VCSR_CTL_LAS_PCI_CFG       (2<<0)  /* pci config space */
402
403/* VMEbus CSR translation offset */
404#define         UNIV_REGOFF_VCSR_TO             0xf84
405
406/* VMEbus AM code error log */
407#define         UNIV_REGOFF_V_AMERR             0xf88
408# define        UNIV_V_AMERR_AMERR(reg)         (((reg)>>26)&0x3f)      /* extract error log code */
409# define        UNIV_V_AMERR_IACK                       (1<<25) /* VMEbus IACK signal */
410# define        UNIV_V_AMERR_M_ERR                      (1<<24) /* multiple errors occurred */
411# define        UNIV_V_AMERR_V_STAT                     (1<<23) /* log status valid (write 1 to clear) */
412
413/* VMEbus address error log */
414#define         UNIV_REGOFF_VAERR               0xf8c           /* address of fault address (if MERR_V_STAT valid) */
415
416/* VMEbus CSR bit clear register */
417#define         UNIV_REGOFF_VCSR_CLR    0xff4
418# define        UNIV_VCSR_CLR_RESET                     (1<<31) /* read/negate LRST (can only be written from VME bus */
419# define        UNIV_VCSR_CLR_SYSFAIL           (1<<30) /* read/negate SYSFAIL */
420# define        UNIV_VCSR_CLR_FAIL                      (1<<29) /* read: board has failed */
421
422/* VMEbus CSR bit set register */
423#define         UNIV_REGOFF_VCSR_SET            (0xff8)
424# define        UNIV_VCSR_SET_RESET                     (1<<31) /* read/assert LRST (can only be written from VME bus */
425# define        UNIV_VCSR_SET_SYSFAIL           (1<<30) /* read/assert SYSFAIL */
426# define        UNIV_VCSR_SET_FAIL                      (1<<29) /* read: board has failed */
427
428/* VMEbus CSR base address register */
429#define         UNIV_REGOFF_VCSR_BS             0xffc
430#define         UNIV_VCSR_BS_MASK                       (0xf8000000)
431
432/* offset of universe registers in VME-CSR slot */
433#define         UNIV_CSR_OFFSET                         0x7f000
434
435#ifdef __cplusplus
436extern "C" {
437#endif
438
439/* base address and IRQ line of 1st universe bridge
440 * NOTE: vmeUniverseInit() must be called before
441 *       these may be used.
442 */
443extern volatile LERegister *vmeUniverse0BaseAddr;
444extern int vmeUniverse0PciIrqLine;
445
446
447/* Initialize the driver */
448int
449vmeUniverseInit(void);
450
451/* setup the universe chip, i.e. disable most of its
452 * mappings, reset interrupts etc.
453 */
454void
455vmeUniverseReset(void);
456
457/* avoid pulling stdio.h into this header.
458 * Applications that want a declaration of the
459 * following routines should
460 *  #include <stdio.h>
461 *  #define _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
462 *  #include <vmeUniverse.h>
463 */
464#ifdef _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
465/* print the current configuration of all master ports to
466 * f (stderr if NULL)
467 */
468void
469vmeUniverseMasterPortsShow(FILE *f);
470
471/* print the current configuration of all slave ports to
472 * f (stderr if NULL)
473 */
474void
475vmeUniverseSlavePortsShow(FILE *f);
476#else
477void
478vmeUniverseMasterPortsShow();
479void
480vmeUniverseSlavePortsShow();
481#endif
482
483/* disable all master or slave ports, respectively */
484void
485vmeUniverseDisableAllMasters(void);
486
487void
488vmeUniverseDisableAllSlaves(void);
489
490/* configure a master port
491 *
492 *   port:          port number 0..3  (0..7 for a UniverseII)
493 *
494 *   address_space: vxWorks compliant addressing mode identifier
495 *                  (see vme.h). The most important are:
496 *                    0x0d - A32, Sup, Data
497 *                    0x3d - A24, Sup, Data
498 *                    0x2d - A16, Sup, Data
499 *                  additionally, the value 0 is accepted; it will
500 *                  disable this port.
501 *   vme_address:   address on the vme_bus of this port.
502 *   local_address: address on the pci_bus of this port.
503 *   length:        size of this port.
504 *
505 *   NOTE: the addresses and length parameters must be aligned on a
506 *         2^16 byte (0x10000) boundary, except for port 4 (only available
507 *         on a UniverseII), where the alignment can be 4k (4096).
508 *
509 *   RETURNS: 0 on success, -1 on failure. Error messages printed to stderr.
510 */
511
512int
513vmeUniverseMasterPortCfg(
514        unsigned long   port,
515        unsigned long   address_space,
516        unsigned long   vme_address,
517        unsigned long   local_address,
518        unsigned long   length);
519
520/* translate an address through the bridge
521 *
522 * vmeUniverseXlateAddr(0,0,as,addr,&result)
523 * yields a VME a address that reflects
524 * a local memory location as seen from the VME bus through the universe
525 * VME slave.
526 *
527 * likewise does vmeUniverseXlateAddr(1,0,as,addr,&result)
528 * translate a VME bus addr (through the VME master) to the
529 * PCI side of the bridge.
530 *
531 * a valid address space modifier must be specified.
532 *
533 * The 'reverse' parameter may be used to find a reverse
534 * mapping, i.e. the pci address in a master window can be
535 * found if the respective vme address is known etc.
536 *
537 * RETURNS: translated address in *pbusAdrs / *plocalAdrs
538 *
539 *          0:  success
540 *          -1: address/modifier not found in any bridge port
541 *          -2: invalid modifier
542 */
543int
544vmeUniverseXlateAddr(
545        int master,             /* look in the master windows */
546        int reverse,            /* reverse mapping; for masters: map local to VME */
547        unsigned long as,       /* address space */
548        unsigned long addr,     /* address to look up */
549        unsigned long *paOut/* where to put result */
550        );
551
552/* configure a VME slave (PCI master) port */
553int
554vmeUniverseSlavePortCfg(
555        unsigned long   port,
556        unsigned long   address_space,
557        unsigned long   vme_address,
558        unsigned long   local_address,
559        unsigned long   length);
560
561/* start a (direct, not linked) DMA transfer
562 *
563 * NOTE:  DCTL and DGCS must be set up
564 *        prior to calling this routine
565 */
566int
567vmeUniverseStartDMA(
568        unsigned long local_addr,
569        unsigned long vme_addr,
570        unsigned long count);
571
572/* read a register in PCI memory space
573 * (offset being one of the declared constants)
574 */
575unsigned long
576vmeUniverseReadReg(unsigned long offset);
577
578/* write a register in PCI memory space */
579void
580vmeUniverseWriteReg(unsigned long value, unsigned long offset);
581
582/* convert an array of unsigned long values to LE (as needed
583 * when the universe reads e.g. DMA descriptors from PCI)
584 */
585void
586vmeUniverseCvtToLE(unsigned long *ptr, unsigned long num);
587
588/* reset the VME bus */
589void
590vmeUniverseResetBus(void);
591
592/* The ...XX routines take the universe base address as an additional
593 * argument - this allows for programming secondary devices.
594 */
595
596unsigned long
597vmeUniverseReadRegXX(volatile LERegister *ubase, unsigned long offset);
598
599void
600vmeUniverseWriteRegXX(volatile LERegister *ubase, unsigned long value, unsigned long offset);
601
602int
603vmeUniverseXlateAddrXX(
604        volatile LERegister *ubase,
605        int master,
606        int reverse,
607        unsigned long as,
608        unsigned long addr,
609        unsigned long *paOut
610        );
611
612int
613vmeUniverseMasterPortCfgXX(
614        volatile LERegister *ubase,
615        unsigned long   port,
616        unsigned long   address_space,
617        unsigned long   vme_address,
618        unsigned long   local_address,
619        unsigned long   length);
620
621int
622vmeUniverseSlavePortCfgXX(
623        volatile LERegister *ubase,
624        unsigned long   port,
625        unsigned long   address_space,
626        unsigned long   vme_address,
627        unsigned long   local_address,
628        unsigned long   length);
629
630void
631vmeUniverseDisableAllMastersXX(volatile LERegister *ubase);
632
633void
634vmeUniverseDisableAllSlavesXX(volatile LERegister *ubase);
635
636#ifdef _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
637/* print the current configuration of all master ports to
638 * f (stderr if NULL)
639 */
640void
641vmeUniverseMasterPortsShowXX(
642        volatile LERegister *ubase,FILE *f);
643
644/* print the current configuration of all slave ports to
645 * f (stderr if NULL)
646 */
647void
648vmeUniverseSlavePortsShowXX(
649        volatile LERegister *ubase,FILE *f);
650#else
651void
652vmeUniverseMasterPortsShowXX();
653void
654vmeUniverseSlavePortsShowXX();
655#endif
656
657int
658vmeUniverseStartDMAXX(
659        volatile LERegister *ubase,
660        unsigned long local_addr,
661        unsigned long vme_addr,
662        unsigned long count);
663
664/* Raise a VME Interrupt at 'level' and respond with 'vector' to a
665 * handler on the VME bus. (The handler could be a different board
666 * or the universe itself - [only works with universe II]).
667 *
668 * Note that you could install a interrupt handler at UNIV_VME_SW_IACK_INT_VEC
669 * to be notified of an IACK cycle having completed.
670 *
671 * This routine is mainly FOR TESTING.
672 *
673 * NOTES:
674 *   - several registers are modified: the vector is written to VINT_STATID
675 *     and (universe 1 chip only) the level is written to the SW_INT bits
676 *     int VINT_MAP1
677 *   - NO MUTUAL EXCLUSION PROTECTION (reads VINT_EN, modifies then writes back).
678 *     If several users need access to VINT_EN and/or VINT_STATID (and VINT_MAP1
679 *     on the universe 1) it is their responsibility to serialize access.
680 *
681 * Arguments:
682 *  'level':  interrupt level, 1..7
683 *  'vector': vector number (0..254) that the universe puts on the bus in response to
684 *            an IACK cycle. NOTE: the vector number *must be even* (hardware restriction
685 *            of the universe -- it always clears the LSB when the interrupter is
686 *            a software interrupt).
687 *
688 * RETURNS:
689 *        0:  Success
690 *       -1:  Invalid argument (level not 1..7, vector odd or >= 256)
691 *       -2:  Interrupt 'level' already asserted (maybe nobody handles it).
692 *            You can manually clear it be writing the respective bit in
693 *            VINT_STAT. Make sure really nobody responds to avoid spurious
694 *            interrupts (consult universe docs).
695 */
696
697int
698vmeUniverseIntRaiseXX(volatile LERegister *base, int level, unsigned vector);
699
700int
701vmeUniverseIntRaise(int level, unsigned vector);
702
703/* Map internal register block to VME.
704 *
705 * This routine is intended for BSP implementors. The registers can be
706 * made accessible from VME so that the interrupt handler can flush the
707 * bridge FIFO (see below). The preferred method is by accessing VME CSR,
708 * though, if these are mapped [and the BSP provides an outbound window].
709 * On the universe we can also disable posted writes in the 'ordinary'
710 * outbound windows.
711 *
712 *            vme_base: VME address where the universe registers (4k) can be mapped.
713 *                      This VME address must fall into a range covered by
714 *                      any pre-configured outbound window.
715 *       address_space: The desired VME address space.
716 *                      (all of SUP/USR/PGM/DATA are always accepted).
717 *
718 * See NOTES [vmeUniverseInstallIrqMgrAlt()] below for further information.
719 *
720 * RETURNS: 0 on success, nonzero on error. It is not possible (and results
721 *          in a non-zero return code) to change the CRG VME address after
722 *          initializing the interrupt manager as it uses the CRG.
723 */
724int
725vmeUniverseMapCRGXX(volatile LERegister *base, unsigned long vme_base, unsigned long address_space);
726
727int
728vmeUniverseMapCRG(unsigned long vme_base, unsigned long address_space);
729
730
731#ifdef __rtems__
732
733/* VME Interrupt Handler functionality */
734
735/* we dont use the current RTEMS/BSP interrupt API for the
736 * following reasons:
737 *
738 *    - RTEMS/BSP API does not pass an argument to the ISR :-( :-(
739 *    - no separate vector space for VME vectors. Some vectors would
740 *      have to overlap with existing PCI/ISA vectors.
741 *    - RTEMS/BSP API allocates a structure for every possible vector
742 *    - the irq_on(), irq_off() functions add more bloat than helping.
743 *      They are (currently) only used by the framework to disable
744 *      interrupts at the device level before removing a handler
745 *      and to enable interrupts after installing a handler.
746 *      These operations may as well be done by the driver itself.
747 *
748 * Hence, we maintain our own (VME) handler table and hook our PCI
749 * handler into the standard RTEMS/BSP environment. Our handler then
750 * dispatches VME interrupts.
751 */
752
753typedef void (*VmeUniverseISR) (void *usrArg, unsigned long vector);
754
755/* use these special vectors to connect a handler to the
756 * universe specific interrupts (such as "DMA done",
757 * VOWN, error irqs etc.)
758 * NOTE: The wrapper clears all status LINT bits (except
759 * for regular VME irqs). Also note that it is the user's
760 * responsibility to enable the necessary interrupts in
761 * LINT_EN
762 *
763 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
764 * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER
765 * DEPENDS ON IT
766 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
767 *
768 */
769#define UNIV_VOWN_INT_VEC                       256
770#define UNIV_DMA_INT_VEC                        257
771#define UNIV_LERR_INT_VEC                       258
772#define UNIV_VERR_INT_VEC                       259
773/* 260 is reserved */
774#define UNIV_VME_SW_IACK_INT_VEC        261
775#define UNIV_PCI_SW_INT_VEC                     262
776#define UNIV_SYSFAIL_INT_VEC            263
777#define UNIV_ACFAIL_INT_VEC                     264
778#define UNIV_MBOX0_INT_VEC                      265
779#define UNIV_MBOX1_INT_VEC                      266
780#define UNIV_MBOX2_INT_VEC                      267
781#define UNIV_MBOX3_INT_VEC                      268
782#define UNIV_LM0_INT_VEC                        269
783#define UNIV_LM1_INT_VEC                        270
784#define UNIV_LM2_INT_VEC                        271
785#define UNIV_LM3_INT_VEC                        272
786
787#define UNIV_NUM_INT_VECS                       273
788
789
790/* install a handler for a VME vector
791 * RETURNS 0 on success, nonzero on failure.
792 */
793int
794vmeUniverseInstallISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
795
796/* remove a handler for a VME vector. The vector and usrArg parameters
797 * must match the respective parameters used when installing the handler.
798 * RETURNS 0 on success, nonzero on failure.
799 */
800int
801vmeUniverseRemoveISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
802
803/* query for the currently installed ISR and usr parameter at a given vector
804 * RETURNS: ISR or 0 (vector too big or no ISR installed)
805 */
806VmeUniverseISR
807vmeUniverseISRGet(unsigned long vector, void **parg);
808
809/* utility routines to enable/disable a VME IRQ level.
810 *
811 * To enable/disable the internal interrupt sources (special vectors above)
812 * pass a vector argument > 255.
813 *
814 * RETURNS 0 on success, nonzero on failure
815 */
816int
817vmeUniverseIntEnable(unsigned int level);
818int
819vmeUniverseIntDisable(unsigned int level);
820
821/* Check if an interrupt level or internal source is enabled:
822 *
823 * 'level': VME level 1..7 or internal special vector > 255
824 *
825 * RETURNS: value > 0 if interrupt is currently enabled,
826 *          zero      if interrupt is currently disabled,
827 *          -1        on error (invalid argument).
828 */
829int
830vmeUniverseIntIsEnabled(unsigned int level);
831
832
833/* Change the routing of IRQ 'level' to 'pin'.
834 * If the BSP connects more than one of the eight
835 * physical interrupt lines from the universe to
836 * the board's PIC then you may change the physical
837 * line a given 'level' is using. By default,
838 * all 7 VME levels use the first wire (pin==0) and
839 * all internal sources use the (optional) second
840 * wire (pin==1) [The driver doesn't support more than
841 * to wires].
842 * This feature is useful if you want to make use of
843 * different hardware priorities of the PIC. Let's
844 * say you want to give IRQ level 7 the highest priority.
845 * You could then give 'pin 0' a higher priority (at the
846 * PIC) and 'pin 1' a lower priority and issue.
847 *
848 *   for ( i=1; i<7; i++ ) vmeUniverseIntRoute(i, 1);
849 *
850 * PARAMETERS:
851 *    'level' : VME interrupt level '1..7' or one of
852 *              the internal sources. Pass the internal
853 *              source's vector number (>=256).
854 *    'pin'   : a value of 0 routes the requested IRQ to
855 *              the first line registered with the manager
856 *              (vmeIrqUnivOut parameter), a value of 1
857 *              routes it to the alternate wire
858 *              (specialIrqUnivOut)
859 * RETURNS: 0 on success, nonzero on error (invalid arguments)
860 *
861 * NOTES:       - DONT change the universe 'map' registers
862 *            directly. The driver caches routing internally.
863 *          - support for the 'specialIrqUnivOut' wire is
864 *            board dependent. If the board only provides
865 *            a single physical wire from the universe to
866 *            the PIC then the feature might not be available.
867 */
868int
869vmeUniverseIntRoute(unsigned int level, unsigned int pin);
870
871/* Loopback test of the VME interrupt subsystem.
872 *  - installs ISRs on 'vector' and on UNIV_VME_SW_IACK_INT_VEC
873 *  - asserts VME interrupt 'level'
874 *  - waits for both interrupts: 'ordinary' VME interrupt of 'level' and
875 *    IACK completion interrupt ('special' vector UNIV_VME_SW_IACK_INT_VEC).
876 *
877 * NOTES:
878 *  - make sure no other handler responds to 'level'.
879 *  - make sure no ISR is installed on both vectors yet.
880 *  - ISRs installed by this routine are removed after completion.
881 *  - no concurrent access protection of all involved resources
882 *    (levels, vectors and registers  [see vmeUniverseIntRaise()])
883 *    is implemented.
884 *  - this routine is intended for TESTING (when implementing new BSPs etc.).
885 *  - one RTEMS message queue is temporarily used (created/deleted).
886 *  - the universe 1 always yields a zero vector (VIRQx_STATID) in response
887 *    to a self-generated VME interrupt. As a workaround, the routine
888 *    only accepts a zero vector when running on a universe 1.
889 *
890 * RETURNS:
891 *                 0: Success.
892 *                -1: Invalid arguments.
893 *                 1: Test failed (outstanding interrupts).
894 * rtems_status_code: Failed RTEMS directive.
895 */
896int
897vmeUniverseIntLoopbackTst(int level, unsigned vector);
898
899
900/* the universe interrupt handler is capable of routing all sorts of
901 * (VME) interrupts to 8 different lines (some of) which may be hooked up
902 * in a (board specific) way to a PIC.
903 *
904 * This driver only supports at most two lines. By default, it routes the
905 * 7 VME interrupts to the main line and optionally, it routes the 'special'
906 * interrupts generated by the universe itself (DMA done, VOWN etc.)
907 * to a second line. If no second line is available, all IRQs are routed
908 * to the main line.
909 *
910 * The routing of interrupts to the two lines can be modified (using
911 * the vmeUniverseIntRoute() call - see above - i.e., to make use of
912 * different hardware priorities of the two pins.
913 *
914 * Because the driver has no way to figure out which lines are actually
915 * wired to the PIC, this information has to be provided when installing
916 * the manager.
917 *
918 * Hence the manager sets up routing VME interrupts to 1 or 2 universe
919 * OUTPUTS. However, it must also be told to which PIC INPUTS they
920 * are wired.
921 * Optionally, the first PIC input line can be read from PCI config space
922 * but the second must be passed to this routine. Note that the info read
923 * from PCI config space is wrong for many boards!
924 *
925 * PARAMETERS:
926 *       vmeIrqUnivOut: to which output pin (of the universe) should the 7
927 *                                      VME irq levels be routed.
928 *       vmeIrqPicLine: specifies to which PIC input the 'main' output is
929 *                      wired. If passed a value < 0, the driver reads this
930 *                      information from PCI config space ("IRQ line").
931 *   specialIrqUnivOut: to which output pin (of the universe) should the
932 *                      internally irqs be routed. Use 'vmeIRQunivOut'
933 *                      if < 0.
934 *   specialIrqPicLine: specifies to which PIC input the 'special' output
935 *                      pin is wired. The wiring of the 'vmeIRQunivOut' to
936 *                      the PIC is determined by reading PCI config space.
937 *
938 * RETURNS: 0 on success, -1 on failure.
939 *                                             
940 */
941
942/* This routine is outside of the __INSIDE_RTEMS_BSP__ test for bwrds compatibility ONLY */
943int
944vmeUniverseInstallIrqMgr(int vmeIrqUnivOut,
945                                                 int vmeIrqPicLine,
946                                                 int specialIrqUnivOut,
947                                                 int specialIrqPicLine);
948
949
950#if defined(__INSIDE_RTEMS_BSP__)
951#include <stdarg.h>
952
953/* up to 4 universe outputs are now supported by this alternate
954 * entry point.
955 * Terminate the vararg list (uni_pin/pic_pin pairs) with a
956 * '-1' uni_pin.
957 * E.g., the old interface is now just a wrapper to
958 *   vmeUniverseInstallIrqMgrAlt(0, vmeUnivOut, vmePicLint, specUnivOut, specPicLine, -1);
959 *
960 * The 'IRQ_MGR_SHARED' flag uses the BSP_install_rtems_shared_irq_handler()
961 * API. CAVEAT: shared interrupts need RTEMS workspace, i.e., the
962 * VME interrupt manager can only be installed *after workspace is initialized*
963 * if 'shared' is nonzero (i.e., *not* from bspstart()).
964 *
965 * If 'PW_WORKAROUND' flag is set then the interrupt manager will try to
966 * find a way to access the control registers from VME so that the universe's
967 * posted write FIFO can be flushed after the user ISR returns:
968 *
969 * The installation routine looks first for CSR registers in CSR space (this
970 * requires:
971 *      - a VME64 crate with autoid or geographical addressing
972 *      - the firmware or BSP to figure out the slot number and program the CSR base
973 *        in the universe.
974 *      - the BSP to open an outbound window to CSR space.
975 *
976 * If CSR registers cannot be found then the installation routine looks for CRG registers:
977 *      - BSP must map CRG on VME
978 *      - CRG must be visible in outbound window
979 *      CAVEAT: multiple boards with same BSP on single backplane must not map their CRG
980 *              to the same address!
981 */
982
983#define VMEUNIVERSE_IRQ_MGR_FLAG_SHARED                 1       /* use shared interrupts */
984#define VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND  2       /* use shared interrupts */
985
986int
987vmeUniverseInstallIrqMgrAlt(int flags, int uni_pin0, int pic_pin0, ...);
988
989int
990vmeUniverseInstallIrqMgrVa(int flags, int uni_pin0, int pic_pin0, va_list ap);
991
992#endif /* __INSIDE_RTEMS_BSP__ */
993#endif /* __rtems__ */
994
995#ifdef __cplusplus
996}
997#endif
998
999#endif
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