source: rtems/c/src/lib/libbsp/shared/vmeUniverse/vmeUniverse.h @ adac8ab

4.104.114.84.9
Last change on this file since adac8ab was adac8ab, checked in by Till Straumann <strauman@…>, on Jan 17, 2007 at 6:33:29 AM

2007-01-16 Till Straumann <strauman@…>

  • vmeUniverse/vmeTsi148.c, vmeUniverse/vmeTsi148.h,
  • vmeUniverse/vmeUniverse.c, vmeUniverse/vmeUniverse.h,
  • vmeUniverse/vme_am_defs.h: Added SLAC/Stanford Authorship Note / Copyright + Liability Disclaimer.
  • Property mode set to 100644
File size: 42.7 KB
Line 
1/* $Id$ */
2#ifndef VME_UNIVERSE_UTIL_H
3#define VME_UNIVERSE_UTIL_H
4
5/* Driver for the Tundra Universe II pci-vme bridge */
6
7/*
8 * Authorship
9 * ----------
10 * This software was created by
11 *     Till Straumann <strauman@slac.stanford.edu>, 2000-2007,
12 *         Stanford Linear Accelerator Center, Stanford University.
13 *
14 * Acknowledgement of sponsorship
15 * ------------------------------
16 * This software was produced by
17 *     the Stanford Linear Accelerator Center, Stanford University,
18 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
19 *
20 * Government disclaimer of liability
21 * ----------------------------------
22 * Neither the United States nor the United States Department of Energy,
23 * nor any of their employees, makes any warranty, express or implied, or
24 * assumes any legal liability or responsibility for the accuracy,
25 * completeness, or usefulness of any data, apparatus, product, or process
26 * disclosed, or represents that its use would not infringe privately owned
27 * rights.
28 *
29 * Stanford disclaimer of liability
30 * --------------------------------
31 * Stanford University makes no representations or warranties, express or
32 * implied, nor assumes any liability for the use of this software.
33 *
34 * Stanford disclaimer of copyright
35 * --------------------------------
36 * Stanford University, owner of the copyright, hereby disclaims its
37 * copyright and all other rights in this software.  Hence, anyone may
38 * freely use it for any purpose without restriction. 
39 *
40 * Maintenance of notices
41 * ----------------------
42 * In the interest of clarity regarding the origin and status of this
43 * SLAC software, this and all the preceding Stanford University notices
44 * are to remain affixed to any copy or derivative of this software made
45 * or distributed by the recipient and are to be affixed to any copy of
46 * software made or distributed by the recipient that contains a copy or
47 * derivative of this software.
48 *
49 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
50 */ 
51
52/* Register definitions */
53/* NOTE: all registers contents in PCI space are LITTLE ENDIAN */
54
55#ifdef __vxworks
56#include <vme.h>
57#else
58
59#include <bsp/vme_am_defs.h>
60
61#endif
62
63/* These bits can be or'ed with the address-modifier when calling
64 * the 'XlateAddr' routine below to further qualify the
65 * search criteria.
66 */
67#define VME_MODE_MATCH_MASK                                     (3<<30)
68#define VME_MODE_EXACT_MATCH                            (2<<30) /* all bits must match */
69#define VME_MODE_AS_MATCH                                       (1<<30) /* only A16/24/32 must match */
70
71
72typedef unsigned long LERegister; /* emphasize contents are little endian */
73
74/* NOTE: DMA packet descriptors MUST be 32 byte aligned */
75typedef struct VmeUniverseDMAPacketRec_ {
76        LERegister      dctl    __attribute__((aligned(32)));
77        LERegister      dtbc    __attribute__((packed));
78        LERegister      dla             __attribute__((packed));
79        LERegister      dummy1  __attribute__((packed));
80        LERegister      dva             __attribute__((packed));
81        LERegister      dummy2  __attribute__((packed));
82        LERegister      dcpp    __attribute__((packed));
83        LERegister      dummy3  __attribute__((packed));
84} VmeUniverseDMAPacketRec, *VmeUniverseDMAPacket;
85
86/* PCI CSR register */
87#define         UNIV_REGOFF_PCI_CSR             0x4
88# define        UNIV_PCI_CSR_D_PE               (1<<31) /* detected parity error; write 1 to clear */
89# define        UNIV_PCI_CSR_S_SERR             (1<<30) /* SERR (signalled error) asserted; write 1 to clear */
90# define        UNIV_PCI_CSR_R_MA               (1<<29) /* received master abort; write 1 to clear */
91# define        UNIV_PCI_CSR_R_TA               (1<<28) /* received target abort; write 1 to clear */
92# define        UNIV_PCI_CSR_S_TA               (1<<27) /* signalled target abort; write 1 to clear */
93# define        UNIV_PCI_CSR_DEVSEL_MASK (3<<25)        /* device select timing (RO) */
94# define        UNIV_PCI_CSR_DP_D               (1<<24) /* data parity error detected; write 1 to clear */
95# define        UNIV_PCI_CSR_TFBBC              (1<<23) /* target fast back to back capable (RO) */
96# define        UNIV_PCI_CSR_MFBBC              (1<<9)  /* master fast back to back capable (RO) */
97# define        UNIV_PCI_CSR_SERR_EN    (1<<8)  /* enable SERR driver */
98# define        UNIV_PCI_CSR_WAIT               (1<<7)  /* wait cycle control (RO) */
99# define        UNIV_PCI_CSR_PERESP             (1<<6)  /* parity error response enable */
100# define        UNIV_PCI_CSR_VGAPS              (1<<5)  /* VGA palette snoop (RO) */
101# define        UNIV_PCI_CSR_MWI_EN             (1<<4)  /* Memory write and invalidate enable (RO) */
102# define        UNIV_PCI_CSR_SC                 (1<<3)  /* special cycles (RO) */
103# define        UNIV_PCI_CSR_BM                 (1<<2)  /* master enable (MUST SET TO ENABLE VME SLAVES) */
104# define        UNIV_PCI_CSR_MS                 (1<<1)  /* target memory enable */
105# define        UNIV_PCI_CSR_IOS                (1<<0)  /* target IO enable */
106
107/* Special cycle (ADOH, RMW) control register */
108#define         UNIV_REGOFF_SCYC_CTL    0x170   /* write 0 to disable */
109# define        UNIV_SCYC_CTL_LAS_IO    (1<<2)  /* PCI address space (1: IO, 0: mem) */
110# define        UNIV_SCYC_CTL_SCYC_RMW  (1<<0)  /* do a RMW cycle when reading  PCI address */
111# define        UNIV_SCYC_CTL_SCYC_ADOH (2<<0)  /* do a ADOH cycle when reading/writing  PCI address */
112
113/* Special cycle address register */
114#define         UNIV_REGOFF_SCYC_ADDR   0x174   /* PCI address (must be long word aligned) */
115
116/* Special cycle Swap/Compare/Enable */
117#define         UNIV_REGOFF_SCYC_EN     0x178   /* mask determining the bits involved in the compare and swap operations for VME RMW cycles */
118
119/* Special cycle compare data register */
120#define         UNIV_REGOFF_SCYC_CMP    0x17c   /* data to compare with word returned from VME RMW read */
121
122/* Special cycle swap data register */
123#define         UNIV_REGOFF_SCYC_SWP    0x180   /* If enabled bits of CMP match, corresponding SWP bits are written back to VME (under control of EN) */
124
125/* PCI miscellaneous register */
126#define         UNIV_REGOFF_LMISC       0x184
127# define        UNIV_LMISC_CRT_MASK     (7<<28) /* Univ. I only, not used on II */
128# define        UNIV_LMISC_CRT_INF      (0<<28) /* Coupled Request Timeout */
129# define        UNIV_LMISC_CRT_128_US   (1<<28) /* Coupled Request Timeout */
130# define        UNIV_LMISC_CRT_256_US   (2<<28) /* Coupled Request Timeout */
131# define        UNIV_LMISC_CRT_512_US   (3<<28) /* Coupled Request Timeout */
132# define        UNIV_LMISC_CRT_1024_US  (4<<28) /* Coupled Request Timeout */
133# define        UNIV_LMISC_CRT_2048_US  (5<<28) /* Coupled Request Timeout */
134# define        UNIV_LMISC_CRT_4096_US  (6<<28) /* Coupled Request Timeout */
135
136# define        UNIV_LMISC_CWT_MASK     (7<<24) /* coupled window timer */
137# define        UNIV_LMISC_CWT_DISABLE  0       /* disabled (release VME after 1 coupled xaction) */
138# define        UNIV_LMISC_CWT_16       (1<<24) /* 16 PCI clock cycles */
139# define        UNIV_LMISC_CWT_32       (2<<24) /* 32 PCI clock cycles */
140# define        UNIV_LMISC_CWT_64       (3<<24) /* 64 PCI clock cycles */
141# define        UNIV_LMISC_CWT_128      (4<<24) /* 128 PCI clock cycles */
142# define        UNIV_LMISC_CWT_256      (5<<24) /* 256 PCI clock cycles */
143# define        UNIV_LMISC_CWT_512      (6<<24) /* 512 PCI clock cycles */
144
145/* PCI Command Error Log Register */
146#define         UNIV_REGOFF_L_CMDERR    0x18c
147# define        UNIV_L_CMDERR_CMDERR(reg) (((reg)>>28)&0xf) /* extract PCI cmd error log */
148# define        UNIV_L_CMDERR_M_ERR     (1<<27) /* multiple errors have occurred */
149# define        UNIV_L_CMDERR_L_STAT    (1<<23) /* PCI error log status valid (write 1 to clear and enable logging) */
150
151/* PCI Address Error Log */
152#define         UNIV_REGOFF_LAERR       0x190   /* PCI fault address (if L_CMDERR_L_STAT valid) */
153/* DMA Xfer Control Register */
154#define         UNIV_REGOFF_DCTL        0x200
155# define        UNIV_DCTL_L2V           (1<<31) /* PCI->VME if set */
156# define        UNIV_DCTL_VDW_MSK       (3<<22) /* VME max. width mask 0x00c00000 */
157# define        UNIV_DCTL_VDW_8         (0<<22) /* VME max. width 8 */
158# define        UNIV_DCTL_VDW_16        (1<<22) /* VME max. width 16 */
159# define        UNIV_DCTL_VDW_32        (2<<22) /* VME max. width 32 */
160# define        UNIV_DCTL_VDW_64        (3<<22) /* VME max. width 64 */
161# define        UNIV_DCTL_VAS_MSK       (7<<16) /* VME AS mask 0x00070000 */
162# define        UNIV_DCTL_VAS_A16       (0<<16) /* VME A16 */
163# define        UNIV_DCTL_VAS_A24       (1<<16) /* VME A24 */
164# define        UNIV_DCTL_VAS_A32       (2<<16) /* VME A32 */
165# define        UNIV_DCTL_PGM_MSK       (3<<14) /* VME PGM/DATA mask 0x0000c000 */
166# define        UNIV_DCTL_PGM           (1<<14) /* VME PGM(1)/DATA(0) */
167# define        UNIV_DCTL_SUPER_MSK     (3<<12) /* VME SUPER/USR mask 0x00003000 */
168# define        UNIV_DCTL_SUPER         (1<<12) /* VME SUPER(1)/USR(0) */
169# define        UNIV_DCTL_VCT           (1<<8)  /* VME enable BLT */
170# define        UNIV_DCTL_LD64EN        (1<<7)  /* PCI 64 enable  */
171
172/* DMA Xfer byte count register (is updated by DMA) */
173#define         UNIV_REGOFF_DTBC        0x204
174/* DMA Xfer local (PCI) address (direction is  set in DCTL) */
175#define         UNIV_REGOFF_DLA         0x208
176/* DMA Xfer VME address (direction is  set in DCTL)
177 * NOTE: (*UNIV_DVA) & ~7 == (*UNIV_DLA) & ~7 MUST HOLD
178 */
179#define         UNIV_REGOFF_DVA         0x210
180
181/* DMA Xfer VME command packet pointer
182 * NOTE: The address stored here MUST be 32-byte aligned
183 */
184#define         UNIV_REGOFF_DCPP        0x218
185/* these bits are only used in linked lists */
186# define        UNIV_DCPP_IMG_NULL      (1<<0)  /* last packet in list */
187# define        UNIV_DCPP_IMG_PROCESSED (1<<1)  /* packet processed */
188
189/* DMA Xfer General Control/Status register */
190#define         UNIV_REGOFF_DGCS        0x220
191# define        UNIV_DGCS_GO            (1<<31) /* start xfer */
192# define        UNIV_DGCS_STOP_REQ      (1<<30) /* stop xfer (immediate abort) */
193# define        UNIV_DGCS_HALT_REQ      (1<<29) /* halt xfer (abort after current packet) */
194# define        UNIV_DGCS_CHAIN         (1<<27) /* enable linked list mode */
195# define        UNIV_DGCS_VON_MSK       (7<<20) /* VON mask */
196# define        UNIV_DGCS_VON_DONE      (0<<20) /* VON counter disabled (do until done) */
197# define        UNIV_DGCS_VON_256       (1<<20) /* VON yield bus after 256 bytes */
198# define        UNIV_DGCS_VON_512       (2<<20) /* VON yield bus after 512 bytes */
199# define        UNIV_DGCS_VON_1024      (3<<20) /* VON yield bus after 512 bytes */
200# define        UNIV_DGCS_VON_2048      (4<<20) /* VON yield bus after 1024 bytes */
201# define        UNIV_DGCS_VON_4096      (5<<20) /* VON yield bus after 4096 bytes */
202# define        UNIV_DGCS_VON_8192      (6<<20) /* VON yield bus after 8192 bytes */
203# define        UNIV_DGCS_VOFF_MSK      (15<<16) /* VOFF mask */
204# define        UNIV_DGCS_VOFF_0_US     (0<<16) /* re-request VME master after 0 us */
205# define        UNIV_DGCS_VOFF_2_US     (8<<16) /* re-request VME master after 2 us */
206# define        UNIV_DGCS_VOFF_4_US     (9<<16) /* re-request VME master after 4 us */
207# define        UNIV_DGCS_VOFF_8_US     (10<<16)/* re-request VME master after 8 us */
208# define        UNIV_DGCS_VOFF_16_US    (1<<16) /* re-request VME master after 16 us */
209# define        UNIV_DGCS_VOFF_32_US    (2<<16) /* re-request VME master after 32 us */
210# define        UNIV_DGCS_VOFF_64_US    (3<<16) /* re-request VME master after 64 us */
211# define        UNIV_DGCS_VOFF_128_US   (4<<16) /* re-request VME master after 128 us */
212# define        UNIV_DGCS_VOFF_256_US   (5<<16) /* re-request VME master after 256 us */
213# define        UNIV_DGCS_VOFF_512_US   (6<<16) /* re-request VME master after 512 us */
214# define        UNIV_DGCS_VOFF_1024_US  (7<<16) /* re-request VME master after 1024 us */
215/* Status Bits (write 1 to clear) */
216# define        UNIV_DGCS_ACT           (1<<15) /* DMA active */
217# define        UNIV_DGCS_STOP          (1<<14) /* DMA stopped */
218# define        UNIV_DGCS_HALT          (1<<13) /* DMA halted */
219# define        UNIV_DGCS_DONE          (1<<11) /* DMA done (OK) */
220# define        UNIV_DGCS_LERR          (1<<10) /* PCI bus error */
221# define        UNIV_DGCS_VERR          (1<<9)  /* VME bus error */
222# define        UNIV_DGCS_P_ERR         (1<<8)  /* programming protocol error (e.g. PCI master disabled) */
223# define        UNIV_DGCS_STATUS_CLEAR\
224        (UNIV_DGCS_ACT|UNIV_DGCS_STOP|UNIV_DGCS_HALT|\
225         UNIV_DGCS_DONE|UNIV_DGCS_LERR|UNIV_DGCS_VERR|UNIV_DGCS_P_ERR)
226# define        UNIV_DGCS_P_ERR         (1<<8)  /* programming protocol error (e.g. PCI master disabled) */
227/* Interrupt Mask Bits */
228# define        UNIV_DGCS_INT_STOP      (1<<6)  /* interrupt when stopped */
229# define        UNIV_DGCS_INT_HALT      (1<<5)  /* interrupt when halted */
230# define        UNIV_DGCS_INT_DONE      (1<<3)  /* interrupt when done */
231# define        UNIV_DGCS_INT_LERR      (1<<2)  /* interrupt on LERR */
232# define        UNIV_DGCS_INT_VERR      (1<<1)  /* interrupt on VERR */
233# define        UNIV_DGCS_INT_P_ERR     (1<<0)  /* interrupt on P_ERR */
234# define        UNIV_DGCS_INT_MSK       (0x0000006f) /* interrupt mask */
235
236/* DMA Linked List Update Enable Register */
237#define         UNIV_REGOFF_D_LLUE      0x224
238# define        UNIV_D_LLUE_UPDATE      (1<<31)
239
240
241/* PCI (local) interrupt enable register */
242#define         UNIV_REGOFF_LINT_EN     0x300
243# define        UNIV_LINT_EN_LM3        (1<<23) /* location monitor 3 mask */
244# define        UNIV_LINT_EN_LM2        (1<<22) /* location monitor 2 mask */
245# define        UNIV_LINT_EN_LM1        (1<<21) /* location monitor 1 mask */
246# define        UNIV_LINT_EN_LM0        (1<<20) /* location monitor 0 mask */
247# define        UNIV_LINT_EN_MBOX3      (1<<19) /* mailbox 3 mask */
248# define        UNIV_LINT_EN_MBOX2      (1<<18) /* mailbox 2 mask */
249# define        UNIV_LINT_EN_MBOX1      (1<<17) /* mailbox 1 mask */
250# define        UNIV_LINT_EN_MBOX0      (1<<16) /* mailbox 0 mask */
251# define        UNIV_LINT_EN_ACFAIL     (1<<15) /* ACFAIL irq mask */
252# define        UNIV_LINT_EN_SYSFAIL    (1<<14) /* SYSFAIL irq mask */
253# define        UNIV_LINT_EN_SW_INT     (1<<13) /* PCI (local) software irq */
254# define        UNIV_LINT_EN_SW_IACK    (1<<12) /* VME software IACK mask */
255# define        UNIV_LINT_EN_VERR       (1<<10) /* PCI VERR irq mask */
256# define        UNIV_LINT_EN_LERR       (1<<9)  /* PCI LERR irq mask */
257# define        UNIV_LINT_EN_DMA        (1<<8)  /* PCI DMA irq mask */
258# define        UNIV_LINT_EN_VIRQ7      (1<<7)  /* VIRQ7 mask (universe does IACK automatically) */
259# define        UNIV_LINT_EN_VIRQ6      (1<<6)  /* VIRQ6 mask */
260# define        UNIV_LINT_EN_VIRQ5      (1<<5)  /* VIRQ5 mask */
261# define        UNIV_LINT_EN_VIRQ4      (1<<4)  /* VIRQ4 mask */
262# define        UNIV_LINT_EN_VIRQ3      (1<<3)  /* VIRQ3 mask */
263# define        UNIV_LINT_EN_VIRQ2      (1<<2)  /* VIRQ2 mask */
264# define        UNIV_LINT_EN_VIRQ1      (1<<1)  /* VIRQ1 mask */
265# define        UNIV_LINT_EN_VOWN       (1<<0)  /* VOWN mask */
266
267/* PCI (local) interrupt status register */
268#define         UNIV_REGOFF_LINT_STAT   0x304
269# define        UNIV_LINT_STAT_LM3      (1<<23) /* location monitor 3 status */
270# define        UNIV_LINT_STAT_LM2      (1<<22) /* location monitor 2 status */
271# define        UNIV_LINT_STAT_LM1      (1<<21) /* location monitor 1 status */
272# define        UNIV_LINT_STAT_LM0      (1<<20) /* location monitor 0 status */
273# define        UNIV_LINT_STAT_MBOX3    (1<<19) /* mailbox 3 status */
274# define        UNIV_LINT_STAT_MBOX2    (1<<18) /* mailbox 2 status */
275# define        UNIV_LINT_STAT_MBOX1    (1<<17) /* mailbox 1 status */
276# define        UNIV_LINT_STAT_MBOX0    (1<<16) /* mailbox 0 status */
277# define        UNIV_LINT_STAT_ACFAIL   (1<<15) /* ACFAIL irq status */
278# define        UNIV_LINT_STAT_SYSFAIL  (1<<14) /* SYSFAIL irq status */
279# define        UNIV_LINT_STAT_SW_INT   (1<<13) /* PCI (local) software irq */
280# define        UNIV_LINT_STAT_SW_IACK  (1<<12) /* VME software IACK status */
281# define        UNIV_LINT_STAT_VERR             (1<<10) /* PCI VERR irq status */
282# define        UNIV_LINT_STAT_LERR             (1<<9)  /* PCI LERR irq status */
283# define        UNIV_LINT_STAT_DMA              (1<<8)  /* PCI DMA irq status */
284# define        UNIV_LINT_STAT_VIRQ7    (1<<7)  /* VIRQ7 status */
285# define        UNIV_LINT_STAT_VIRQ6    (1<<6)  /* VIRQ6 status */
286# define        UNIV_LINT_STAT_VIRQ5    (1<<5)  /* VIRQ5 status */
287# define        UNIV_LINT_STAT_VIRQ4    (1<<4)  /* VIRQ4 status */
288# define        UNIV_LINT_STAT_VIRQ3    (1<<3)  /* VIRQ3 status */
289# define        UNIV_LINT_STAT_VIRQ2    (1<<2)  /* VIRQ2 status */
290# define        UNIV_LINT_STAT_VIRQ1    (1<<1)  /* VIRQ1 status */
291# define        UNIV_LINT_STAT_VOWN             (1<<0)  /* VOWN status */
292# define        UNIV_LINT_STAT_CLR              (0xfff7ff)/* Clear all status bits */
293
294/* PCI (local) interrupt map 0 register */
295#define         UNIV_REGOFF_LINT_MAP0   0x308   /* mapping of VME IRQ sources to PCI irqs */
296# define        UNIV_LINT_MAP0_VIRQ7(lint)      (((lint)&0x7)<<(7*4))
297# define        UNIV_LINT_MAP0_VIRQ6(lint)      (((lint)&0x7)<<(6*4))
298# define        UNIV_LINT_MAP0_VIRQ5(lint)      (((lint)&0x7)<<(5*4))
299# define        UNIV_LINT_MAP0_VIRQ4(lint)      (((lint)&0x7)<<(4*4))
300# define        UNIV_LINT_MAP0_VIRQ3(lint)      (((lint)&0x7)<<(3*4))
301# define        UNIV_LINT_MAP0_VIRQ2(lint)      (((lint)&0x7)<<(2*4))
302# define        UNIV_LINT_MAP0_VIRQ1(lint)      (((lint)&0x7)<<(1*4))
303# define        UNIV_LINT_MAP0_VOWN(lint)       (((lint)&0x7)<<(0*4))
304
305#define         UNIV_REGOFF_LINT_MAP1   0x30c   /* mapping of internal / VME IRQ sources to PCI irqs */
306# define        UNIV_LINT_MAP1_ACFAIL(lint)     (((lint)&0x7)<<(7*4))
307# define        UNIV_LINT_MAP1_SYSFAIL(lint)    (((lint)&0x7)<<(6*4))
308# define        UNIV_LINT_MAP1_SW_INT(lint)     (((lint)&0x7)<<(5*4))
309# define        UNIV_LINT_MAP1_SW_IACK(lint)    (((lint)&0x7)<<(4*4))
310# define        UNIV_LINT_MAP1_VERR(lint)       (((lint)&0x7)<<(2*4))
311# define        UNIV_LINT_MAP1_LERR(lint)       (((lint)&0x7)<<(1*4))
312# define        UNIV_LINT_MAP1_DMA(lint)        (((lint)&0x7)<<(0*4))
313
314/* enabling of generation of VME bus IRQs, TODO */
315#define         UNIV_REGOFF_VINT_EN             0x310
316# define        UNIV_VINT_EN_DISABLE_ALL    0
317# define        UNIV_VINT_EN_SWINT                      (1<<12)
318# define        UNIV_VINT_EN_SWINT_LVL(l)       (1<<(((l)&7)+24))       /* universe II only */
319
320
321/* status of generation of VME bus IRQs */
322#define         UNIV_REGOFF_VINT_STAT   0x314
323# define        UNIV_VINT_STAT_LINT(lint)       (1<<((lint)&7))
324# define        UNIV_VINT_STAT_LINT_MASK        (0xff)
325# define        UNIV_VINT_STAT_CLR                      (0xfe0f17ff)
326# define        UNIV_VINT_STAT_SWINT(l)     (1<<(((l)&7)+24))
327
328#define         UNIV_REGOFF_VINT_MAP0   0x318   /* VME destination of PCI IRQ source, TODO */
329
330#define         UNIV_REGOFF_VINT_MAP1   0x31c   /* VME destination of PCI IRQ source, TODO */
331# define        UNIV_VINT_MAP1_SWINT(level)     (((level)&0x7)<<16)
332
333/* NOTE: The universe seems to always set LSB (which has a special purpose in
334 *       the STATID register: enable raising a SW_INT on IACK) on the
335 *               vector it puts out on the bus...
336 */
337#define         UNIV_REGOFF_VINT_STATID 0x320   /* our status/id response to IACK, TODO */
338# define        UNIV_VINT_STATID(id)        ((id)<<24)
339
340#define         UNIV_REGOFF_VIRQ1_STATID 0x324  /* status/id of VME IRQ level 1 */
341#define         UNIV_REGOFF_VIRQ2_STATID 0x328  /* status/id of VME IRQ level 2 */
342#define         UNIV_REGOFF_VIRQ3_STATID 0x32c  /* status/id of VME IRQ level 3 */
343#define         UNIV_REGOFF_VIRQ4_STATID 0x330  /* status/id of VME IRQ level 4 */
344#define         UNIV_REGOFF_VIRQ5_STATID 0x334  /* status/id of VME IRQ level 5 */
345#define         UNIV_REGOFF_VIRQ6_STATID 0x338  /* status/id of VME IRQ level 6 */
346#define         UNIV_REGOFF_VIRQ7_STATID 0x33c  /* status/id of VME IRQ level 7 */
347# define        UNIV_VIRQ_ERR                   (1<<8)  /* set if universe encountered a bus error when doing IACK */
348# define        UNIV_VIRQ_STATID_MASK           (0xff)
349
350#define         UNIV_REGOFF_LINT_MAP2   0x340   /* mapping of internal sources to PCI irqs */
351# define        UNIV_LINT_MAP2_LM3(lint)        (((lint)&0x7)<<7*4)     /* location monitor 3 */
352# define        UNIV_LINT_MAP2_LM2(lint)        (((lint)&0x7)<<6*4)     /* location monitor 2 */
353# define        UNIV_LINT_MAP2_LM1(lint)        (((lint)&0x7)<<5*4)     /* location monitor 1 */
354# define        UNIV_LINT_MAP2_LM0(lint)        (((lint)&0x7)<<4*4)     /* location monitor 0 */
355# define        UNIV_LINT_MAP2_MBOX3(lint)      (((lint)&0x7)<<3*4)     /* mailbox 3 */
356# define        UNIV_LINT_MAP2_MBOX2(lint)      (((lint)&0x7)<<2*4)     /* mailbox 2 */
357# define        UNIV_LINT_MAP2_MBOX1(lint)      (((lint)&0x7)<<1*4)     /* mailbox 1 */
358# define        UNIV_LINT_MAP2_MBOX0(lint)      (((lint)&0x7)<<0*4)     /* mailbox 0 */
359
360#define         UNIV_REGOFF_VINT_MAP2   0x344   /* mapping of internal sources to VME irqs */
361# define        UNIV_VINT_MAP2_MBOX3(vint)      (((vint)&0x7)<<3*4)     /* mailbox 3 */
362# define        UNIV_VINT_MAP2_MBOX2(vint)      (((vint)&0x7)<<2*4)     /* mailbox 2 */
363# define        UNIV_VINT_MAP2_MBOX1(vint)      (((vint)&0x7)<<1*4)     /* mailbox 1 */
364# define        UNIV_VINT_MAP2_MBOX0(vint)      (((vint)&0x7)<<0*4)     /* mailbox 0 */
365
366#define         UNIV_REGOFF_MBOX0       0x348   /* mailbox 0 */
367#define         UNIV_REGOFF_MBOX1       0x34c   /* mailbox 1 */
368#define         UNIV_REGOFF_MBOX2       0x350   /* mailbox 2 */
369#define         UNIV_REGOFF_MBOX3       0x354   /* mailbox 3 */
370
371#define         UNIV_REGOFF_SEMA0       0x358   /* semaphore 0 */
372#define         UNIV_REGOFF_SEMA1       0x35c   /* semaphore 0 */
373/* TODO define semaphore register bits */
374
375#define         UNIV_REGOFF_MAST_CTL    0x400   /* master control register */
376# define        UNIV_MAST_CTL_MAXRTRY(val)      (((val)&0xf)<<7*4)      /* max # of pci master retries */
377# define        UNIV_MAST_CTL_PWON(val)         (((val)&0xf)<<6*4)      /* posted write xfer count */
378# define        UNIV_MAST_CTL_VRL(val)          (((val)&0x3)<<22)       /* VME bus request level */
379# define        UNIV_MAST_CTL_VRM                       (1<<21) /* bus request mode (demand = 0, fair = 1) */
380# define        UNIV_MAST_CTL_VREL                      (1<<20) /* bus release mode (when done = 0, on request = 1) */
381# define        UNIV_MAST_CTL_VOWN                      (1<<19) /* bus ownership (release = 0, acquire/hold = 1) */
382# define        UNIV_MAST_CTL_VOWN_ACK          (1<<18) /* bus ownership (not owned = 0, acquired/held = 1) */
383# define        UNIV_MAST_CTL_PABS(val)         (((val)&0x3)<<3*4)      /* PCI aligned burst size (32,64,128 byte / 0x3 is reserved) */
384# define        UNIV_MAST_CTL_BUS_NO(val)       (((val)&0xff)<<0*4)     /* PCI bus number */
385
386#define         UNIV_REGOFF_MISC_CTL    0x404   /* misc control register */
387# define        UNIV_MISC_CTL_VBTO(val)         (((val)&0x7)<<7*4)      /* VME bus timeout (0=disable, 16*2^(val-1) us) */
388# define        UNIV_MISC_CTL_VARB                      (1<<26) /* VME bus arbitration mode (0=round robin, 1= priority) */
389# define        UNIV_MISC_CTL_VARBTO(val)       (((val)&0x3)<<6*4)      /* arbitration time out: disable, 16us, 256us, reserved */
390# define        UNIV_MISC_CTL_SW_LRST           (1<<23) /* software PCI reset */
391# define        UNIV_MISC_CTL_SW_SYSRST         (1<<22) /* software VME reset */
392# define        UNIV_MISC_CTL_BI                        (1<<20) /* BI mode */
393# define        UNIV_MISC_CTL_ENGBI                     (1<<19) /* enable global BI mode initiator */
394# define        UNIV_MISC_CTL_SYSCON            (1<<17) /* (R/W) 1:universe is system controller */
395# define        UNIV_MISC_CTL_V64AUTO           (1<<16) /* (R/W) 1:initiate VME64 auto id slave participation */
396
397/* U2SPEC described in VGM manual */
398/* NOTE: the Joerger vtr10012_8 needs the timing to be tweaked!!!! READt27 must be _no_delay_
399 */
400#define         UNIV_REGOFF_U2SPEC              0x4fc
401# define        UNIV_U2SPEC_DTKFLTR                     (1<<12) /* DTAck filter: 0: slow, better filter; 1: fast, poorer filter */
402# define        UNIV_U2SPEC_MASt11                      (1<<10) /* Master parameter t11 (DS hi time during BLT and MBLTs) */
403# define        UNIV_U2SPEC_READt27_DEFAULT     (0<<8)  /* VME master parameter t27: (latch data after DTAck + 25ns) */
404# define        UNIV_U2SPEC_READt27_FAST        (1<<8)  /* VME master parameter t27: (latch data faster than 25ns)  */
405# define        UNIV_U2SPEC_READt27_NODELAY     (2<<8)  /* VME master parameter t27: (latch data without any delay)  */
406# define        UNIV_U2SPEC_POSt28_FAST         (1<<2)  /* VME slave parameter t28: (faster time of DS to DTAck for posted write) */
407# define        UNIV_U2SPEC_PREt28_FAST         (1<<0)  /* VME slave parameter t28: (faster time of DS to DTAck for prefetch read) */
408
409/* Location Monitor control register */
410#define         UNIV_REGOFF_LM_CTL              0xf64
411# define        UNIV_LM_CTL_EN                          (1<<31) /* image enable */ 
412# define        UNIV_LM_CTL_PGM                         (1<<23) /* program AM */
413# define        UNIV_LM_CTL_DATA                        (1<<22) /* data AM */
414# define        UNIV_LM_CTL_SUPER                       (1<<21) /* supervisor AM */
415# define        UNIV_LM_CTL_USER                        (1<<20) /* user AM */
416# define        UNIV_LM_CTL_VAS_A16                     (0<<16) /* A16 */
417# define        UNIV_LM_CTL_VAS_A24                     (1<<16) /* A16 */
418# define        UNIV_LM_CTL_VAS_A32                     (2<<16) /* A16 */
419
420/* Location Monitor base address */
421#define         UNIV_REGOFF_LM_BS               0xf68
422
423/* VMEbus register access image control register */
424#define         UNIV_REGOFF_VRAI_CTL    0xf70
425# define        UNIV_VRAI_CTL_EN                        (1<<31) /* image enable */ 
426# define        UNIV_VRAI_CTL_PGM                       (1<<23) /* program AM */
427# define        UNIV_VRAI_CTL_DATA                      (1<<22) /* data AM */
428# define        UNIV_VRAI_CTL_SUPER                     (1<<21) /* supervisor AM */
429# define        UNIV_VRAI_CTL_USER                      (1<<20) /* user AM */
430# define        UNIV_VRAI_CTL_VAS_A16           (0<<16) /* A16 */
431# define        UNIV_VRAI_CTL_VAS_A24           (1<<16) /* A14 */
432# define        UNIV_VRAI_CTL_VAS_A32           (2<<16) /* A32 */
433# define        UNIV_VRAI_CTL_VAS_MSK           (3<<16)
434
435/* VMEbus register acces image base address register */
436#define         UNIV_REGOFF_VRAI_BS             0xf74
437
438/* VMEbus CSR control register */
439#define         UNIV_REGOFF_VCSR_CTL    0xf80
440# define        UNIV_VCSR_CTL_EN                        (1<<31) /* image enable */
441# define        UNIV_VCSR_CTL_LAS_PCI_MEM       (0<<0)  /* pci mem space */
442# define        UNIV_VCSR_CTL_LAS_PCI_IO        (1<<0)  /* pci IO space */
443# define        UNIV_VCSR_CTL_LAS_PCI_CFG       (2<<0)  /* pci config space */
444
445/* VMEbus CSR translation offset */
446#define         UNIV_REGOFF_VCSR_TO             0xf84
447
448/* VMEbus AM code error log */
449#define         UNIV_REGOFF_V_AMERR             0xf88
450# define        UNIV_V_AMERR_AMERR(reg)         (((reg)>>26)&0x3f)      /* extract error log code */
451# define        UNIV_V_AMERR_IACK                       (1<<25) /* VMEbus IACK signal */
452# define        UNIV_V_AMERR_M_ERR                      (1<<24) /* multiple errors occurred */
453# define        UNIV_V_AMERR_V_STAT                     (1<<23) /* log status valid (write 1 to clear) */
454
455/* VMEbus address error log */
456#define         UNIV_REGOFF_VAERR               0xf8c           /* address of fault address (if MERR_V_STAT valid) */
457
458/* VMEbus CSR bit clear register */
459#define         UNIV_REGOFF_VCSR_CLR    0xff4
460# define        UNIV_VCSR_CLR_RESET                     (1<<31) /* read/negate LRST (can only be written from VME bus */
461# define        UNIV_VCSR_CLR_SYSFAIL           (1<<30) /* read/negate SYSFAIL */
462# define        UNIV_VCSR_CLR_FAIL                      (1<<29) /* read: board has failed */
463
464/* VMEbus CSR bit set register */
465#define         UNIV_REGOFF_VCSR_SET            (0xff8)
466# define        UNIV_VCSR_SET_RESET                     (1<<31) /* read/assert LRST (can only be written from VME bus */
467# define        UNIV_VCSR_SET_SYSFAIL           (1<<30) /* read/assert SYSFAIL */
468# define        UNIV_VCSR_SET_FAIL                      (1<<29) /* read: board has failed */
469
470/* VMEbus CSR base address register */
471#define         UNIV_REGOFF_VCSR_BS             0xffc
472#define         UNIV_VCSR_BS_MASK                       (0xf8000000)
473
474/* offset of universe registers in VME-CSR slot */
475#define         UNIV_CSR_OFFSET                         0x7f000
476
477#ifdef __cplusplus
478extern "C" {
479#endif
480
481/* base address and IRQ line of 1st universe bridge
482 * NOTE: vmeUniverseInit() must be called before
483 *       these may be used.
484 */
485extern volatile LERegister *vmeUniverse0BaseAddr;
486extern int vmeUniverse0PciIrqLine;
487
488
489/* Initialize the driver */
490int
491vmeUniverseInit(void);
492
493/* setup the universe chip, i.e. disable most of its
494 * mappings, reset interrupts etc.
495 */
496void
497vmeUniverseReset(void);
498
499/* avoid pulling stdio.h into this header.
500 * Applications that want a declaration of the
501 * following routines should
502 *  #include <stdio.h>
503 *  #define _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
504 *  #include <vmeUniverse.h>
505 */
506#ifdef _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
507/* print the current configuration of all master ports to
508 * f (stderr if NULL)
509 */
510void
511vmeUniverseMasterPortsShow(FILE *f);
512
513/* print the current configuration of all slave ports to
514 * f (stderr if NULL)
515 */
516void
517vmeUniverseSlavePortsShow(FILE *f);
518#else
519void
520vmeUniverseMasterPortsShow();
521void
522vmeUniverseSlavePortsShow();
523#endif
524
525/* disable all master or slave ports, respectively */
526void
527vmeUniverseDisableAllMasters(void);
528
529void
530vmeUniverseDisableAllSlaves(void);
531
532/* configure a master port
533 *
534 *   port:          port number 0..3  (0..7 for a UniverseII)
535 *
536 *   address_space: vxWorks compliant addressing mode identifier
537 *                  (see vme.h). The most important are:
538 *                    0x0d - A32, Sup, Data
539 *                    0x3d - A24, Sup, Data
540 *                    0x2d - A16, Sup, Data
541 *                  additionally, the value 0 is accepted; it will
542 *                  disable this port.
543 *   vme_address:   address on the vme_bus of this port.
544 *   local_address: address on the pci_bus of this port.
545 *   length:        size of this port.
546 *
547 *   NOTE: the addresses and length parameters must be aligned on a
548 *         2^16 byte (0x10000) boundary, except for port 4 (only available
549 *         on a UniverseII), where the alignment can be 4k (4096).
550 *
551 *   RETURNS: 0 on success, -1 on failure. Error messages printed to stderr.
552 */
553
554int
555vmeUniverseMasterPortCfg(
556        unsigned long   port,
557        unsigned long   address_space,
558        unsigned long   vme_address,
559        unsigned long   local_address,
560        unsigned long   length);
561
562/* translate an address through the bridge
563 *
564 * vmeUniverseXlateAddr(0,0,as,addr,&result)
565 * yields a VME a address that reflects
566 * a local memory location as seen from the VME bus through the universe
567 * VME slave.
568 *
569 * likewise does vmeUniverseXlateAddr(1,0,as,addr,&result)
570 * translate a VME bus addr (through the VME master) to the
571 * PCI side of the bridge.
572 *
573 * a valid address space modifier must be specified.
574 *
575 * The 'reverse' parameter may be used to find a reverse
576 * mapping, i.e. the pci address in a master window can be
577 * found if the respective vme address is known etc.
578 *
579 * RETURNS: translated address in *pbusAdrs / *plocalAdrs
580 *
581 *          0:  success
582 *          -1: address/modifier not found in any bridge port
583 *          -2: invalid modifier
584 */
585int
586vmeUniverseXlateAddr(
587        int master,             /* look in the master windows */
588        int reverse,            /* reverse mapping; for masters: map local to VME */
589        unsigned long as,       /* address space */
590        unsigned long addr,     /* address to look up */
591        unsigned long *paOut/* where to put result */
592        );
593
594/* configure a VME slave (PCI master) port */
595int
596vmeUniverseSlavePortCfg(
597        unsigned long   port,
598        unsigned long   address_space,
599        unsigned long   vme_address,
600        unsigned long   local_address,
601        unsigned long   length);
602
603/* start a (direct, not linked) DMA transfer
604 *
605 * NOTE:  DCTL and DGCS must be set up
606 *        prior to calling this routine
607 */
608int
609vmeUniverseStartDMA(
610        unsigned long local_addr,
611        unsigned long vme_addr,
612        unsigned long count);
613
614/* read a register in PCI memory space
615 * (offset being one of the declared constants)
616 */
617unsigned long
618vmeUniverseReadReg(unsigned long offset);
619
620/* write a register in PCI memory space */
621void
622vmeUniverseWriteReg(unsigned long value, unsigned long offset);
623
624/* convert an array of unsigned long values to LE (as needed
625 * when the universe reads e.g. DMA descriptors from PCI)
626 */
627void
628vmeUniverseCvtToLE(unsigned long *ptr, unsigned long num);
629
630/* reset the VME bus */
631void
632vmeUniverseResetBus(void);
633
634/* The ...XX routines take the universe base address as an additional
635 * argument - this allows for programming secondary devices.
636 */
637
638unsigned long
639vmeUniverseReadRegXX(volatile LERegister *ubase, unsigned long offset);
640
641void
642vmeUniverseWriteRegXX(volatile LERegister *ubase, unsigned long value, unsigned long offset);
643
644int
645vmeUniverseXlateAddrXX(
646        volatile LERegister *ubase,
647        int master,
648        int reverse,
649        unsigned long as,
650        unsigned long addr,
651        unsigned long *paOut
652        );
653
654int
655vmeUniverseMasterPortCfgXX(
656        volatile LERegister *ubase,
657        unsigned long   port,
658        unsigned long   address_space,
659        unsigned long   vme_address,
660        unsigned long   local_address,
661        unsigned long   length);
662
663int
664vmeUniverseSlavePortCfgXX(
665        volatile LERegister *ubase,
666        unsigned long   port,
667        unsigned long   address_space,
668        unsigned long   vme_address,
669        unsigned long   local_address,
670        unsigned long   length);
671
672void
673vmeUniverseDisableAllMastersXX(volatile LERegister *ubase);
674
675void
676vmeUniverseDisableAllSlavesXX(volatile LERegister *ubase);
677
678#ifdef _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
679/* print the current configuration of all master ports to
680 * f (stderr if NULL)
681 */
682void
683vmeUniverseMasterPortsShowXX(
684        volatile LERegister *ubase,FILE *f);
685
686/* print the current configuration of all slave ports to
687 * f (stderr if NULL)
688 */
689void
690vmeUniverseSlavePortsShowXX(
691        volatile LERegister *ubase,FILE *f);
692#else
693void
694vmeUniverseMasterPortsShowXX();
695void
696vmeUniverseSlavePortsShowXX();
697#endif
698
699int
700vmeUniverseStartDMAXX(
701        volatile LERegister *ubase,
702        unsigned long local_addr,
703        unsigned long vme_addr,
704        unsigned long count);
705
706/* Raise a VME Interrupt at 'level' and respond with 'vector' to a
707 * handler on the VME bus. (The handler could be a different board
708 * or the universe itself - [only works with universe II]).
709 *
710 * Note that you could install a interrupt handler at UNIV_VME_SW_IACK_INT_VEC
711 * to be notified of an IACK cycle having completed.
712 *
713 * This routine is mainly FOR TESTING.
714 *
715 * NOTES:
716 *   - several registers are modified: the vector is written to VINT_STATID
717 *     and (universe 1 chip only) the level is written to the SW_INT bits
718 *     int VINT_MAP1
719 *   - NO MUTUAL EXCLUSION PROTECTION (reads VINT_EN, modifies then writes back).
720 *     If several users need access to VINT_EN and/or VINT_STATID (and VINT_MAP1
721 *     on the universe 1) it is their responsibility to serialize access.
722 *
723 * Arguments:
724 *  'level':  interrupt level, 1..7
725 *  'vector': vector number (0..254) that the universe puts on the bus in response to
726 *            an IACK cycle. NOTE: the vector number *must be even* (hardware restriction
727 *            of the universe -- it always clears the LSB when the interrupter is
728 *            a software interrupt).
729 *
730 * RETURNS:
731 *        0:  Success
732 *       -1:  Invalid argument (level not 1..7, vector odd or >= 256)
733 *       -2:  Interrupt 'level' already asserted (maybe nobody handles it).
734 *            You can manually clear it be writing the respective bit in
735 *            VINT_STAT. Make sure really nobody responds to avoid spurious
736 *            interrupts (consult universe docs).
737 */
738
739int
740vmeUniverseIntRaiseXX(volatile LERegister *base, int level, unsigned vector);
741
742int
743vmeUniverseIntRaise(int level, unsigned vector);
744
745/* Map internal register block to VME.
746 *
747 * This routine is intended for BSP implementors. The registers can be
748 * made accessible from VME so that the interrupt handler can flush the
749 * bridge FIFO (see below). The preferred method is by accessing VME CSR,
750 * though, if these are mapped [and the BSP provides an outbound window].
751 * On the universe we can also disable posted writes in the 'ordinary'
752 * outbound windows.
753 *
754 *            vme_base: VME address where the universe registers (4k) can be mapped.
755 *                      This VME address must fall into a range covered by
756 *                      any pre-configured outbound window.
757 *       address_space: The desired VME address space.
758 *                      (all of SUP/USR/PGM/DATA are always accepted).
759 *
760 * See NOTES [vmeUniverseInstallIrqMgrAlt()] below for further information.
761 *
762 * RETURNS: 0 on success, nonzero on error. It is not possible (and results
763 *          in a non-zero return code) to change the CRG VME address after
764 *          initializing the interrupt manager as it uses the CRG.
765 */
766int
767vmeUniverseMapCRGXX(volatile LERegister *base, unsigned long vme_base, unsigned long address_space);
768
769int
770vmeUniverseMapCRG(unsigned long vme_base, unsigned long address_space);
771
772
773#ifdef __rtems__
774
775/* VME Interrupt Handler functionality */
776
777/* we dont use the current RTEMS/BSP interrupt API for the
778 * following reasons:
779 *
780 *    - RTEMS/BSP API does not pass an argument to the ISR :-( :-(
781 *    - no separate vector space for VME vectors. Some vectors would
782 *      have to overlap with existing PCI/ISA vectors.
783 *    - RTEMS/BSP API allocates a structure for every possible vector
784 *    - the irq_on(), irq_off() functions add more bloat than helping.
785 *      They are (currently) only used by the framework to disable
786 *      interrupts at the device level before removing a handler
787 *      and to enable interrupts after installing a handler.
788 *      These operations may as well be done by the driver itself.
789 *
790 * Hence, we maintain our own (VME) handler table and hook our PCI
791 * handler into the standard RTEMS/BSP environment. Our handler then
792 * dispatches VME interrupts.
793 */
794
795typedef void (*VmeUniverseISR) (void *usrArg, unsigned long vector);
796
797/* use these special vectors to connect a handler to the
798 * universe specific interrupts (such as "DMA done",
799 * VOWN, error irqs etc.)
800 * NOTE: The wrapper clears all status LINT bits (except
801 * for regular VME irqs). Also note that it is the user's
802 * responsibility to enable the necessary interrupts in
803 * LINT_EN
804 *
805 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
806 * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER
807 * DEPENDS ON IT
808 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
809 *
810 */
811#define UNIV_VOWN_INT_VEC                       256
812#define UNIV_DMA_INT_VEC                        257
813#define UNIV_LERR_INT_VEC                       258
814#define UNIV_VERR_INT_VEC                       259
815/* 260 is reserved */
816#define UNIV_VME_SW_IACK_INT_VEC        261
817#define UNIV_PCI_SW_INT_VEC                     262
818#define UNIV_SYSFAIL_INT_VEC            263
819#define UNIV_ACFAIL_INT_VEC                     264
820#define UNIV_MBOX0_INT_VEC                      265
821#define UNIV_MBOX1_INT_VEC                      266
822#define UNIV_MBOX2_INT_VEC                      267
823#define UNIV_MBOX3_INT_VEC                      268
824#define UNIV_LM0_INT_VEC                        269
825#define UNIV_LM1_INT_VEC                        270
826#define UNIV_LM2_INT_VEC                        271
827#define UNIV_LM3_INT_VEC                        272
828
829#define UNIV_NUM_INT_VECS                       273
830
831
832/* install a handler for a VME vector
833 * RETURNS 0 on success, nonzero on failure.
834 */
835int
836vmeUniverseInstallISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
837
838/* remove a handler for a VME vector. The vector and usrArg parameters
839 * must match the respective parameters used when installing the handler.
840 * RETURNS 0 on success, nonzero on failure.
841 */
842int
843vmeUniverseRemoveISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
844
845/* query for the currently installed ISR and usr parameter at a given vector
846 * RETURNS: ISR or 0 (vector too big or no ISR installed)
847 */
848VmeUniverseISR
849vmeUniverseISRGet(unsigned long vector, void **parg);
850
851/* utility routines to enable/disable a VME IRQ level.
852 *
853 * To enable/disable the internal interrupt sources (special vectors above)
854 * pass a vector argument > 255.
855 *
856 * RETURNS 0 on success, nonzero on failure
857 */
858int
859vmeUniverseIntEnable(unsigned int level);
860int
861vmeUniverseIntDisable(unsigned int level);
862
863/* Check if an interrupt level or internal source is enabled:
864 *
865 * 'level': VME level 1..7 or internal special vector > 255
866 *
867 * RETURNS: value > 0 if interrupt is currently enabled,
868 *          zero      if interrupt is currently disabled,
869 *          -1        on error (invalid argument).
870 */
871int
872vmeUniverseIntIsEnabled(unsigned int level);
873
874
875/* Change the routing of IRQ 'level' to 'pin'.
876 * If the BSP connects more than one of the eight
877 * physical interrupt lines from the universe to
878 * the board's PIC then you may change the physical
879 * line a given 'level' is using. By default,
880 * all 7 VME levels use the first wire (pin==0) and
881 * all internal sources use the (optional) second
882 * wire (pin==1) [The driver doesn't support more than
883 * to wires].
884 * This feature is useful if you want to make use of
885 * different hardware priorities of the PIC. Let's
886 * say you want to give IRQ level 7 the highest priority.
887 * You could then give 'pin 0' a higher priority (at the
888 * PIC) and 'pin 1' a lower priority and issue.
889 *
890 *   for ( i=1; i<7; i++ ) vmeUniverseIntRoute(i, 1);
891 *
892 * PARAMETERS:
893 *    'level' : VME interrupt level '1..7' or one of
894 *              the internal sources. Pass the internal
895 *              source's vector number (>=256).
896 *    'pin'   : a value of 0 routes the requested IRQ to
897 *              the first line registered with the manager
898 *              (vmeIrqUnivOut parameter), a value of 1
899 *              routes it to the alternate wire
900 *              (specialIrqUnivOut)
901 * RETURNS: 0 on success, nonzero on error (invalid arguments)
902 *
903 * NOTES:       - DONT change the universe 'map' registers
904 *            directly. The driver caches routing internally.
905 *          - support for the 'specialIrqUnivOut' wire is
906 *            board dependent. If the board only provides
907 *            a single physical wire from the universe to
908 *            the PIC then the feature might not be available.
909 */
910int
911vmeUniverseIntRoute(unsigned int level, unsigned int pin);
912
913/* Loopback test of the VME interrupt subsystem.
914 *  - installs ISRs on 'vector' and on UNIV_VME_SW_IACK_INT_VEC
915 *  - asserts VME interrupt 'level'
916 *  - waits for both interrupts: 'ordinary' VME interrupt of 'level' and
917 *    IACK completion interrupt ('special' vector UNIV_VME_SW_IACK_INT_VEC).
918 *
919 * NOTES:
920 *  - make sure no other handler responds to 'level'.
921 *  - make sure no ISR is installed on both vectors yet.
922 *  - ISRs installed by this routine are removed after completion.
923 *  - no concurrent access protection of all involved resources
924 *    (levels, vectors and registers  [see vmeUniverseIntRaise()])
925 *    is implemented.
926 *  - this routine is intended for TESTING (when implementing new BSPs etc.).
927 *  - one RTEMS message queue is temporarily used (created/deleted).
928 *  - the universe 1 always yields a zero vector (VIRQx_STATID) in response
929 *    to a self-generated VME interrupt. As a workaround, the routine
930 *    only accepts a zero vector when running on a universe 1.
931 *
932 * RETURNS:
933 *                 0: Success.
934 *                -1: Invalid arguments.
935 *                 1: Test failed (outstanding interrupts).
936 * rtems_status_code: Failed RTEMS directive.
937 */
938int
939vmeUniverseIntLoopbackTst(int level, unsigned vector);
940
941
942/* the universe interrupt handler is capable of routing all sorts of
943 * (VME) interrupts to 8 different lines (some of) which may be hooked up
944 * in a (board specific) way to a PIC.
945 *
946 * This driver only supports at most two lines. By default, it routes the
947 * 7 VME interrupts to the main line and optionally, it routes the 'special'
948 * interrupts generated by the universe itself (DMA done, VOWN etc.)
949 * to a second line. If no second line is available, all IRQs are routed
950 * to the main line.
951 *
952 * The routing of interrupts to the two lines can be modified (using
953 * the vmeUniverseIntRoute() call - see above - i.e., to make use of
954 * different hardware priorities of the two pins.
955 *
956 * Because the driver has no way to figure out which lines are actually
957 * wired to the PIC, this information has to be provided when installing
958 * the manager.
959 *
960 * Hence the manager sets up routing VME interrupts to 1 or 2 universe
961 * OUTPUTS. However, it must also be told to which PIC INPUTS they
962 * are wired.
963 * Optionally, the first PIC input line can be read from PCI config space
964 * but the second must be passed to this routine. Note that the info read
965 * from PCI config space is wrong for many boards!
966 *
967 * PARAMETERS:
968 *       vmeIrqUnivOut: to which output pin (of the universe) should the 7
969 *                                      VME irq levels be routed.
970 *       vmeIrqPicLine: specifies to which PIC input the 'main' output is
971 *                      wired. If passed a value < 0, the driver reads this
972 *                      information from PCI config space ("IRQ line").
973 *   specialIrqUnivOut: to which output pin (of the universe) should the
974 *                      internally irqs be routed. Use 'vmeIRQunivOut'
975 *                      if < 0.
976 *   specialIrqPicLine: specifies to which PIC input the 'special' output
977 *                      pin is wired. The wiring of the 'vmeIRQunivOut' to
978 *                      the PIC is determined by reading PCI config space.
979 *
980 * RETURNS: 0 on success, -1 on failure.
981 *                                             
982 */
983
984/* This routine is outside of the __INSIDE_RTEMS_BSP__ test for bwrds compatibility ONLY */
985int
986vmeUniverseInstallIrqMgr(int vmeIrqUnivOut,
987                                                 int vmeIrqPicLine,
988                                                 int specialIrqUnivOut,
989                                                 int specialIrqPicLine);
990
991
992#if defined(__INSIDE_RTEMS_BSP__)
993#include <stdarg.h>
994
995/* up to 4 universe outputs are now supported by this alternate
996 * entry point.
997 * Terminate the vararg list (uni_pin/pic_pin pairs) with a
998 * '-1' uni_pin.
999 * E.g., the old interface is now just a wrapper to
1000 *   vmeUniverseInstallIrqMgrAlt(0, vmeUnivOut, vmePicLint, specUnivOut, specPicLine, -1);
1001 *
1002 * The 'IRQ_MGR_SHARED' flag uses the BSP_install_rtems_shared_irq_handler()
1003 * API. CAVEAT: shared interrupts need RTEMS workspace, i.e., the
1004 * VME interrupt manager can only be installed *after workspace is initialized*
1005 * if 'shared' is nonzero (i.e., *not* from bspstart()).
1006 *
1007 * If 'PW_WORKAROUND' flag is set then the interrupt manager will try to
1008 * find a way to access the control registers from VME so that the universe's
1009 * posted write FIFO can be flushed after the user ISR returns:
1010 *
1011 * The installation routine looks first for CSR registers in CSR space (this
1012 * requires:
1013 *      - a VME64 crate with autoid or geographical addressing
1014 *      - the firmware or BSP to figure out the slot number and program the CSR base
1015 *        in the universe.
1016 *      - the BSP to open an outbound window to CSR space.
1017 *
1018 * If CSR registers cannot be found then the installation routine looks for CRG registers:
1019 *      - BSP must map CRG on VME
1020 *      - CRG must be visible in outbound window
1021 *      CAVEAT: multiple boards with same BSP on single backplane must not map their CRG
1022 *              to the same address!
1023 */
1024
1025#define VMEUNIVERSE_IRQ_MGR_FLAG_SHARED                 1       /* use shared interrupts */
1026#define VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND  2       /* use shared interrupts */
1027
1028int
1029vmeUniverseInstallIrqMgrAlt(int flags, int uni_pin0, int pic_pin0, ...);
1030
1031int
1032vmeUniverseInstallIrqMgrVa(int flags, int uni_pin0, int pic_pin0, va_list ap);
1033
1034#endif /* __INSIDE_RTEMS_BSP__ */
1035#endif /* __rtems__ */
1036
1037#ifdef __cplusplus
1038}
1039#endif
1040
1041#endif
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