source: rtems/c/src/lib/libbsp/shared/vmeUniverse/vmeUniverse.h @ 2f73363

4.104.114.84.95
Last change on this file since 2f73363 was 2f73363, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 10, 2003 at 4:39:52 PM

2003-04-10 Till Straumann <strauman@…>

PR 380/bsps

  • vmeUniverse/vmeUniverse.c, vmeUniverse/vmeUniverse.h: make printk format strings compliant with libcpu/printk. minor fixes and lazy init bugfix.
  • Property mode set to 100644
File size: 31.0 KB
Line 
1/* $Id$ */
2#ifndef VME_UNIVERSE_UTIL_H
3#define VME_UNIVERSE_UTIL_H
4
5/* Routines to configure and use the Tundra Universe VME bridge
6 * Author: Till Straumann <strauman@slac.stanford.edu>
7 *         Nov 2000, July 2001
8 */
9
10/* Register definitions */
11/* NOTE: all registers contents in PCI space are LITTLE ENDIAN */
12
13#ifdef __vxworks
14#include <vme.h>
15#else
16/* vxworks compatible addressing modes */
17#define VME_AM_STD_SUP_ASCENDING        0x3f
18#define VME_AM_STD_SUP_PGM      0x3e
19#define VME_AM_STD_USR_ASCENDING        0x3b
20#define VME_AM_STD_USR_PGM      0x3a
21#define VME_AM_STD_SUP_DATA     0x3d
22#define VME_AM_STD_USR_DATA     0x39
23#define VME_AM_EXT_SUP_ASCENDING        0x0f
24#define VME_AM_EXT_SUP_PGM      0x0e
25#define VME_AM_EXT_USR_ASCENDING        0x0b
26#define VME_AM_EXT_USR_PGM      0x0a
27#define VME_AM_EXT_SUP_DATA     0x0d
28#define VME_AM_EXT_USR_DATA     0x09
29#define VME_AM_SUP_SHORT_IO     0x2d
30#define VME_AM_USR_SHORT_IO     0x29
31
32#define VME_AM_IS_SHORT(a)      (((a) & 0xf0) == 0x20)
33#define VME_AM_IS_STD(a)        (((a) & 0xf0) == 0x30)
34#define VME_AM_IS_EXT(a)        (((a) & 0xf0) == 0x00)
35
36#endif
37
38typedef unsigned long LERegister; /* emphasize contents are little endian */
39
40/* NOTE: DMA packet descriptors MUST be 32 byte aligned */
41typedef struct VmeUniverseDMAPacketRec_ {
42        LERegister      dctl    __attribute__((aligned(32)));
43        LERegister      dtbc    __attribute__((packed));
44        LERegister      dla             __attribute__((packed));
45        LERegister      dummy1  __attribute__((packed));
46        LERegister      dva             __attribute__((packed));
47        LERegister      dummy2  __attribute__((packed));
48        LERegister      dcpp    __attribute__((packed));
49        LERegister      dummy3  __attribute__((packed));
50} VmeUniverseDMAPacketRec, *VmeUniverseDMAPacket;
51
52/* PCI CSR register */
53#define         UNIV_REGOFF_PCI_CSR             0x4
54# define        UNIV_PCI_CSR_D_PE               (1<<31) /* detected parity error; write 1 to clear */
55# define        UNIV_PCI_CSR_S_SERR             (1<<30) /* SERR (signalled error) asserted; write 1 to clear */
56# define        UNIV_PCI_CSR_R_MA               (1<<29) /* received master abort; write 1 to clear */
57# define        UNIV_PCI_CSR_R_TA               (1<<28) /* received target abort; write 1 to clear */
58# define        UNIV_PCI_CSR_S_TA               (1<<27) /* signalled target abort; write 1 to clear */
59# define        UNIV_PCI_CSR_DEVSEL_MASK (3<<25)        /* device select timing (RO) */
60# define        UNIV_PCI_CSR_DP_D               (1<<24) /* data parity error detected; write 1 to clear */
61# define        UNIV_PCI_CSR_TFBBC              (1<<23) /* target fast back to back capable (RO) */
62# define        UNIV_PCI_CSR_MFBBC              (1<<9)  /* master fast back to back capable (RO) */
63# define        UNIV_PCI_CSR_SERR_EN    (1<<8)  /* enable SERR driver */
64# define        UNIV_PCI_CSR_WAIT               (1<<7)  /* wait cycle control (RO) */
65# define        UNIV_PCI_CSR_PERESP             (1<<6)  /* parity error response enable */
66# define        UNIV_PCI_CSR_VGAPS              (1<<5)  /* VGA palette snoop (RO) */
67# define        UNIV_PCI_CSR_MWI_EN             (1<<4)  /* Memory write and invalidate enable (RO) */
68# define        UNIV_PCI_CSR_SC                 (1<<3)  /* special cycles (RO) */
69# define        UNIV_PCI_CSR_BM                 (1<<2)  /* master enable (MUST SET TO ENABLE VME SLAVES) */
70# define        UNIV_PCI_CSR_MS                 (1<<1)  /* target memory enable */
71# define        UNIV_PCI_CSR_IOS                (1<<0)  /* target IO enable */
72
73/* Special cycle (ADOH, RMW) control register */
74#define         UNIV_REGOFF_SCYC_CTL    0x170   /* write 0 to disable */
75# define        UNIV_SCYC_CTL_LAS_IO    (1<<2)  /* PCI address space (1: IO, 0: mem) */
76# define        UNIV_SCYC_CTL_SCYC_RMW  (1<<0)  /* do a RMW cycle when reading  PCI address */
77# define        UNIV_SCYC_CTL_SCYC_ADOH (2<<0)  /* do a ADOH cycle when reading/writing  PCI address */
78
79/* Special cycle address register */
80#define         UNIV_REGOFF_SCYC_ADDR   0x174   /* PCI address (must be long word aligned) */
81
82/* Special cycle Swap/Compare/Enable */
83#define         UNIV_REGOFF_SCYC_EN     0x178   /* mask determining the bits involved in the compare and swap operations for VME RMW cycles */
84
85/* Special cycle compare data register */
86#define         UNIV_REGOFF_SCYC_CMP    0x17c   /* data to compare with word returned from VME RMW read */
87
88/* Special cycle swap data register */
89#define         UNIV_REGOFF_SCYC_SWP    0x180   /* If enabled bits of CMP match, corresponding SWP bits are written back to VME (under control of EN) */
90
91/* PCI miscellaneous register */
92#define         UNIV_REGOFF_LMISC       0x184
93# define        UNIV_LMISC_CRT_MASK     (7<<28) /* Univ. I only, not used on II */
94# define        UNIV_LMISC_CRT_INF      (0<<28) /* Coupled Request Timeout */
95# define        UNIV_LMISC_CRT_128_US   (1<<28) /* Coupled Request Timeout */
96# define        UNIV_LMISC_CRT_256_US   (2<<28) /* Coupled Request Timeout */
97# define        UNIV_LMISC_CRT_512_US   (3<<28) /* Coupled Request Timeout */
98# define        UNIV_LMISC_CRT_1024_US  (4<<28) /* Coupled Request Timeout */
99# define        UNIV_LMISC_CRT_2048_US  (5<<28) /* Coupled Request Timeout */
100# define        UNIV_LMISC_CRT_4096_US  (6<<28) /* Coupled Request Timeout */
101
102# define        UNIV_LMISC_CWT_MASK     (7<<24) /* coupled window timer */
103# define        UNIV_LMISC_CWT_DISABLE  0       /* disabled (release VME after 1 coupled xaction) */
104# define        UNIV_LMISC_CWT_16       (1<<24) /* 16 PCI clock cycles */
105# define        UNIV_LMISC_CWT_32       (2<<24) /* 32 PCI clock cycles */
106# define        UNIV_LMISC_CWT_64       (3<<24) /* 64 PCI clock cycles */
107# define        UNIV_LMISC_CWT_128      (4<<24) /* 128 PCI clock cycles */
108# define        UNIV_LMISC_CWT_256      (5<<24) /* 256 PCI clock cycles */
109# define        UNIV_LMISC_CWT_512      (6<<24) /* 512 PCI clock cycles */
110
111/* PCI Command Error Log Register */
112#define         UNIV_REGOFF_L_CMDERR    0x18c
113# define        UNIV_L_CMDERR_CMDERR(reg) (((reg)>>28)&0xf) /* extract PCI cmd error log */
114# define        UNIV_L_CMDERR_M_ERR     (1<<27) /* multiple errors have occurred */
115# define        UNIV_L_CMDERR_L_STAT    (1<<23) /* PCI error log status valid (write 1 to clear and enable logging) */
116
117/* PCI Address Error Log */
118#define         UNIV_REGOFF_LAERR       0x190   /* PCI fault address (if L_CMDERR_L_STAT valid) */
119/* DMA Xfer Control Register */
120#define         UNIV_REGOFF_DCTL        0x200
121# define        UNIV_DCTL_L2V           (1<<31) /* PCI->VME if set */
122# define        UNIV_DCTL_VDW_MSK       (3<<22) /* VME max. width mask 0x00c00000 */
123# define        UNIV_DCTL_VDW_8         (0<<22) /* VME max. width 8 */
124# define        UNIV_DCTL_VDW_16        (1<<22) /* VME max. width 16 */
125# define        UNIV_DCTL_VDW_32        (2<<22) /* VME max. width 32 */
126# define        UNIV_DCTL_VDW_64        (3<<22) /* VME max. width 64 */
127# define        UNIV_DCTL_VAS_MSK       (7<<16) /* VME AS mask 0x00070000 */
128# define        UNIV_DCTL_VAS_A16       (0<<16) /* VME A16 */
129# define        UNIV_DCTL_VAS_A24       (1<<16) /* VME A24 */
130# define        UNIV_DCTL_VAS_A32       (2<<16) /* VME A32 */
131# define        UNIV_DCTL_PGM_MSK       (3<<14) /* VME PGM/DATA mask 0x0000c000 */
132# define        UNIV_DCTL_PGM           (1<<14) /* VME PGM(1)/DATA(0) */
133# define        UNIV_DCTL_SUPER_MSK     (3<<12) /* VME SUPER/USR mask 0x00003000 */
134# define        UNIV_DCTL_SUPER         (1<<12) /* VME SUPER(1)/USR(0) */
135# define        UNIV_DCTL_VCT           (1<<8)  /* VME enable BLT */
136# define        UNIV_DCTL_LD64EN        (1<<7)  /* PCI 64 enable  */
137
138/* DMA Xfer byte count register (is updated by DMA) */
139#define         UNIV_REGOFF_DTBC        0x204
140/* DMA Xfer local (PCI) address (direction is  set in DCTL) */
141#define         UNIV_REGOFF_DLA         0x208
142/* DMA Xfer VME address (direction is  set in DCTL)
143 * NOTE: (*UNIV_DVA) & ~7 == (*UNIV_DLA) & ~7 MUST HOLD
144 */
145#define         UNIV_REGOFF_DVA         0x210
146
147/* DMA Xfer VME command packet pointer
148 * NOTE: The address stored here MUST be 32-byte aligned
149 */
150#define         UNIV_REGOFF_DCPP        0x218
151/* these bits are only used in linked lists */
152# define        UNIV_DCPP_IMG_NULL      (1<<0)  /* last packet in list */
153# define        UNIV_DCPP_IMG_PROCESSED (1<<1)  /* packet processed */
154
155/* DMA Xfer General Control/Status register */
156#define         UNIV_REGOFF_DGCS        0x220
157# define        UNIV_DGCS_GO            (1<<31) /* start xfer */
158# define        UNIV_DGCS_STOP_REQ      (1<<30) /* stop xfer (immediate abort) */
159# define        UNIV_DGCS_HALT_REQ      (1<<29) /* halt xfer (abort after current packet) */
160# define        UNIV_DGCS_CHAIN         (1<<27) /* enable linked list mode */
161# define        UNIV_DGCS_VON_MSK       (7<<20) /* VON mask */
162# define        UNIV_DGCS_VON_DONE      (0<<20) /* VON counter disabled (do until done) */
163# define        UNIV_DGCS_VON_256       (1<<20) /* VON yield bus after 256 bytes */
164# define        UNIV_DGCS_VON_512       (2<<20) /* VON yield bus after 512 bytes */
165# define        UNIV_DGCS_VON_1024      (3<<20) /* VON yield bus after 512 bytes */
166# define        UNIV_DGCS_VON_2048      (4<<20) /* VON yield bus after 1024 bytes */
167# define        UNIV_DGCS_VON_4096      (5<<20) /* VON yield bus after 4096 bytes */
168# define        UNIV_DGCS_VON_8192      (6<<20) /* VON yield bus after 8192 bytes */
169# define        UNIV_DGCS_VOFF_MSK      (15<<16) /* VOFF mask */
170# define        UNIV_DGCS_VOFF_0_US     (0<<16) /* re-request VME master after 0 us */
171# define        UNIV_DGCS_VOFF_2_US     (8<<16) /* re-request VME master after 2 us */
172# define        UNIV_DGCS_VOFF_4_US     (9<<16) /* re-request VME master after 4 us */
173# define        UNIV_DGCS_VOFF_8_US     (10<<16)/* re-request VME master after 8 us */
174# define        UNIV_DGCS_VOFF_16_US    (1<<16) /* re-request VME master after 16 us */
175# define        UNIV_DGCS_VOFF_32_US    (2<<16) /* re-request VME master after 32 us */
176# define        UNIV_DGCS_VOFF_64_US    (3<<16) /* re-request VME master after 64 us */
177# define        UNIV_DGCS_VOFF_128_US   (4<<16) /* re-request VME master after 128 us */
178# define        UNIV_DGCS_VOFF_256_US   (5<<16) /* re-request VME master after 256 us */
179# define        UNIV_DGCS_VOFF_512_US   (6<<16) /* re-request VME master after 512 us */
180# define        UNIV_DGCS_VOFF_1024_US  (7<<16) /* re-request VME master after 1024 us */
181/* Status Bits (write 1 to clear) */
182# define        UNIV_DGCS_ACT           (1<<15) /* DMA active */
183# define        UNIV_DGCS_STOP          (1<<14) /* DMA stopped */
184# define        UNIV_DGCS_HALT          (1<<13) /* DMA halted */
185# define        UNIV_DGCS_DONE          (1<<11) /* DMA done (OK) */
186# define        UNIV_DGCS_LERR          (1<<10) /* PCI bus error */
187# define        UNIV_DGCS_VERR          (1<<9)  /* VME bus error */
188# define        UNIV_DGCS_P_ERR         (1<<8)  /* programming protocol error (e.g. PCI master disabled) */
189# define        UNIV_DGCS_STATUS_CLEAR\
190        (UNIV_DGCS_ACT|UNIV_DGCS_STOP|UNIV_DGCS_HALT|\
191         UNIV_DGCS_DONE|UNIV_DGCS_LERR|UNIV_DGCS_VERR|UNIV_DGCS_P_ERR)
192# define        UNIV_DGCS_P_ERR         (1<<8)  /* programming protocol error (e.g. PCI master disabled) */
193/* Interrupt Mask Bits */
194# define        UNIV_DGCS_INT_STOP      (1<<6)  /* interrupt when stopped */
195# define        UNIV_DGCS_INT_HALT      (1<<5)  /* interrupt when halted */
196# define        UNIV_DGCS_INT_DONE      (1<<3)  /* interrupt when done */
197# define        UNIV_DGCS_INT_LERR      (1<<2)  /* interrupt on LERR */
198# define        UNIV_DGCS_INT_VERR      (1<<1)  /* interrupt on VERR */
199# define        UNIV_DGCS_INT_P_ERR     (1<<0)  /* interrupt on P_ERR */
200# define        UNIV_DGCS_INT_MSK       (0x0000006f) /* interrupt mask */
201
202/* DMA Linked List Update Enable Register */
203#define         UNIV_REGOFF_D_LLUE      0x224
204# define        UNIV_D_LLUE_UPDATE      (1<<31)
205
206
207/* PCI (local) interrupt enable register */
208#define         UNIV_REGOFF_LINT_EN     0x300
209# define        UNIV_LINT_EN_LM3        (1<<23) /* location monitor 3 mask */
210# define        UNIV_LINT_EN_LM2        (1<<22) /* location monitor 2 mask */
211# define        UNIV_LINT_EN_LM1        (1<<21) /* location monitor 1 mask */
212# define        UNIV_LINT_EN_LM0        (1<<20) /* location monitor 0 mask */
213# define        UNIV_LINT_EN_MBOX3      (1<<19) /* mailbox 3 mask */
214# define        UNIV_LINT_EN_MBOX2      (1<<18) /* mailbox 2 mask */
215# define        UNIV_LINT_EN_MBOX1      (1<<17) /* mailbox 1 mask */
216# define        UNIV_LINT_EN_MBOX0      (1<<16) /* mailbox 0 mask */
217# define        UNIV_LINT_EN_ACFAIL     (1<<15) /* ACFAIL irq mask */
218# define        UNIV_LINT_EN_SYSFAIL    (1<<14) /* SYSFAIL irq mask */
219# define        UNIV_LINT_EN_SW_INT     (1<<13) /* PCI (local) software irq */
220# define        UNIV_LINT_EN_SW_IACK    (1<<12) /* VME software IACK mask */
221# define        UNIV_LINT_EN_VERR       (1<<10) /* PCI VERR irq mask */
222# define        UNIV_LINT_EN_LERR       (1<<9)  /* PCI LERR irq mask */
223# define        UNIV_LINT_EN_DMA        (1<<8)  /* PCI DMA irq mask */
224# define        UNIV_LINT_EN_VIRQ7      (1<<7)  /* VIRQ7 mask (universe does IACK automatically) */
225# define        UNIV_LINT_EN_VIRQ6      (1<<6)  /* VIRQ6 mask */
226# define        UNIV_LINT_EN_VIRQ5      (1<<5)  /* VIRQ5 mask */
227# define        UNIV_LINT_EN_VIRQ4      (1<<4)  /* VIRQ4 mask */
228# define        UNIV_LINT_EN_VIRQ3      (1<<3)  /* VIRQ3 mask */
229# define        UNIV_LINT_EN_VIRQ2      (1<<2)  /* VIRQ2 mask */
230# define        UNIV_LINT_EN_VIRQ1      (1<<1)  /* VIRQ1 mask */
231# define        UNIV_LINT_EN_VOWN       (1<<0)  /* VOWN mask */
232
233/* PCI (local) interrupt status register */
234#define         UNIV_REGOFF_LINT_STAT   0x304
235# define        UNIV_LINT_STAT_LM3      (1<<23) /* location monitor 3 status */
236# define        UNIV_LINT_STAT_LM2      (1<<22) /* location monitor 2 status */
237# define        UNIV_LINT_STAT_LM1      (1<<21) /* location monitor 1 status */
238# define        UNIV_LINT_STAT_LM0      (1<<20) /* location monitor 0 status */
239# define        UNIV_LINT_STAT_MBOX3    (1<<19) /* mailbox 3 status */
240# define        UNIV_LINT_STAT_MBOX2    (1<<18) /* mailbox 2 status */
241# define        UNIV_LINT_STAT_MBOX1    (1<<17) /* mailbox 1 status */
242# define        UNIV_LINT_STAT_MBOX0    (1<<16) /* mailbox 0 status */
243# define        UNIV_LINT_STAT_ACFAIL   (1<<15) /* ACFAIL irq status */
244# define        UNIV_LINT_STAT_SYSFAIL  (1<<14) /* SYSFAIL irq status */
245# define        UNIV_LINT_STAT_SW_INT   (1<<13) /* PCI (local) software irq */
246# define        UNIV_LINT_STAT_SW_IACK  (1<<12) /* VME software IACK status */
247# define        UNIV_LINT_STAT_VERR             (1<<10) /* PCI VERR irq status */
248# define        UNIV_LINT_STAT_LERR             (1<<9)  /* PCI LERR irq status */
249# define        UNIV_LINT_STAT_DMA              (1<<8)  /* PCI DMA irq status */
250# define        UNIV_LINT_STAT_VIRQ7    (1<<7)  /* VIRQ7 status */
251# define        UNIV_LINT_STAT_VIRQ6    (1<<6)  /* VIRQ6 status */
252# define        UNIV_LINT_STAT_VIRQ5    (1<<5)  /* VIRQ5 status */
253# define        UNIV_LINT_STAT_VIRQ4    (1<<4)  /* VIRQ4 status */
254# define        UNIV_LINT_STAT_VIRQ3    (1<<3)  /* VIRQ3 status */
255# define        UNIV_LINT_STAT_VIRQ2    (1<<2)  /* VIRQ2 status */
256# define        UNIV_LINT_STAT_VIRQ1    (1<<1)  /* VIRQ1 status */
257# define        UNIV_LINT_STAT_VOWN             (1<<0)  /* VOWN status */
258# define        UNIV_LINT_STAT_CLR              (0xfff7ff)/* Clear all status bits */
259
260/* PCI (local) interrupt map 0 register */
261#define         UNIV_REGOFF_LINT_MAP0   0x308   /* mapping of VME IRQ sources to PCI irqs */
262# define        UNIV_LINT_MAP0_VIRQ7(lint)      (((lint)&0x7)<<(7*4))
263# define        UNIV_LINT_MAP0_VIRQ6(lint)      (((lint)&0x7)<<(6*4))
264# define        UNIV_LINT_MAP0_VIRQ5(lint)      (((lint)&0x7)<<(5*4))
265# define        UNIV_LINT_MAP0_VIRQ4(lint)      (((lint)&0x7)<<(4*4))
266# define        UNIV_LINT_MAP0_VIRQ3(lint)      (((lint)&0x7)<<(3*4))
267# define        UNIV_LINT_MAP0_VIRQ2(lint)      (((lint)&0x7)<<(2*4))
268# define        UNIV_LINT_MAP0_VIRQ1(lint)      (((lint)&0x7)<<(1*4))
269# define        UNIV_LINT_MAP0_VOWN(lint)       (((lint)&0x7)<<(0*4))
270
271#define         UNIV_REGOFF_LINT_MAP1   0x30c   /* mapping of internal / VME IRQ sources to PCI irqs */
272# define        UNIV_LINT_MAP1_ACFAIL(lint)     (((lint)&0x7)<<(7*4))
273# define        UNIV_LINT_MAP1_SYSFAIL(lint)    (((lint)&0x7)<<(6*4))
274# define        UNIV_LINT_MAP1_SW_INT(lint)     (((lint)&0x7)<<(5*4))
275# define        UNIV_LINT_MAP1_SW_IACK(lint)    (((lint)&0x7)<<(4*4))
276# define        UNIV_LINT_MAP1_VERR(lint)       (((lint)&0x7)<<(2*4))
277# define        UNIV_LINT_MAP1_LERR(lint)       (((lint)&0x7)<<(1*4))
278# define        UNIV_LINT_MAP1_DMA(lint)        (((lint)&0x7)<<(0*4))
279
280/* enabling of generation of VME bus IRQs, TODO */
281#define         UNIV_REGOFF_VINT_EN             0x310
282# define        UNIV_VINT_EN_DISABLE_ALL    0
283
284/* status of generation of VME bus IRQs, TODO */
285#define         UNIV_REGOFF_VINT_STAT   0x314
286# define        UNIV_VINT_STAT_LINT(lint)       (1<<((lint)&7))
287# define        UNIV_VINT_STAT_LINT_MASK        (0xff)
288# define        UNIV_VINT_STAT_CLR                      (0xfe0f17ff)
289#define         UNIV_REGOFF_VINT_MAP0   0x318   /* VME destination of PCI IRQ source, TODO */
290#define         UNIV_REGOFF_VINT_MAP1   0x31c   /* VME destination of PCI IRQ source, TODO */
291#define         UNIV_REGOFF_VINT_STATID 0x320   /* our status/id response to IACK, TODO */
292
293#define         UNIV_REGOFF_VIRQ1_STATID 0x324  /* status/id of VME IRQ level 1 */
294#define         UNIV_REGOFF_VIRQ2_STATID 0x328  /* status/id of VME IRQ level 2 */
295#define         UNIV_REGOFF_VIRQ3_STATID 0x32c  /* status/id of VME IRQ level 3 */
296#define         UNIV_REGOFF_VIRQ4_STATID 0x330  /* status/id of VME IRQ level 4 */
297#define         UNIV_REGOFF_VIRQ5_STATID 0x334  /* status/id of VME IRQ level 5 */
298#define         UNIV_REGOFF_VIRQ6_STATID 0x338  /* status/id of VME IRQ level 6 */
299#define         UNIV_REGOFF_VIRQ7_STATID 0x33c  /* status/id of VME IRQ level 7 */
300# define        UNIV_VIRQ_ERR                   (1<<8)  /* set if universe encountered a bus error when doing IACK */
301# define        UNIV_VIRQ_STATID_MASK           (0xff)
302
303#define         UNIV_REGOFF_LINT_MAP2   0x340   /* mapping of internal sources to PCI irqs */
304# define        UNIV_LINT_MAP2_LM3(lint)        (((lint)&0x7)<<7*4)     /* location monitor 3 */
305# define        UNIV_LINT_MAP2_LM2(lint)        (((lint)&0x7)<<6*4)     /* location monitor 2 */
306# define        UNIV_LINT_MAP2_LM1(lint)        (((lint)&0x7)<<5*4)     /* location monitor 1 */
307# define        UNIV_LINT_MAP2_LM0(lint)        (((lint)&0x7)<<4*4)     /* location monitor 0 */
308# define        UNIV_LINT_MAP2_MBOX3(lint)      (((lint)&0x7)<<3*4)     /* mailbox 3 */
309# define        UNIV_LINT_MAP2_MBOX2(lint)      (((lint)&0x7)<<2*4)     /* mailbox 2 */
310# define        UNIV_LINT_MAP2_MBOX1(lint)      (((lint)&0x7)<<1*4)     /* mailbox 1 */
311# define        UNIV_LINT_MAP2_MBOX0(lint)      (((lint)&0x7)<<0*4)     /* mailbox 0 */
312
313#define         UNIV_REGOFF_VINT_MAP2   0x344   /* mapping of internal sources to VME irqs */
314# define        UNIV_VINT_MAP2_MBOX3(vint)      (((vint)&0x7)<<3*4)     /* mailbox 3 */
315# define        UNIV_VINT_MAP2_MBOX2(vint)      (((vint)&0x7)<<2*4)     /* mailbox 2 */
316# define        UNIV_VINT_MAP2_MBOX1(vint)      (((vint)&0x7)<<1*4)     /* mailbox 1 */
317# define        UNIV_VINT_MAP2_MBOX0(vint)      (((vint)&0x7)<<0*4)     /* mailbox 0 */
318
319#define         UNIV_REGOFF_MBOX0       0x348   /* mailbox 0 */
320#define         UNIV_REGOFF_MBOX1       0x34c   /* mailbox 1 */
321#define         UNIV_REGOFF_MBOX2       0x350   /* mailbox 2 */
322#define         UNIV_REGOFF_MBOX3       0x354   /* mailbox 3 */
323
324#define         UNIV_REGOFF_SEMA0       0x358   /* semaphore 0 */
325#define         UNIV_REGOFF_SEMA1       0x35c   /* semaphore 0 */
326/* TODO define semaphore register bits */
327
328#define         UNIV_REGOFF_MAST_CTL    0x400   /* master control register */
329# define        UNIV_MAST_CTL_MAXRTRY(val)      (((val)&0xf)<<7*4)      /* max # of pci master retries */
330# define        UNIV_MAST_CTL_PWON(val)         (((val)&0xf)<<6*4)      /* posted write xfer count */
331# define        UNIV_MAST_CTL_VRL(val)          (((val)&0x3)<<22)       /* VME bus request level */
332# define        UNIV_MAST_CTL_VRM                       (1<<21) /* bus request mode (demand = 0, fair = 1) */
333# define        UNIV_MAST_CTL_VREL                      (1<<20) /* bus release mode (when done = 0, on request = 1) */
334# define        UNIV_MAST_CTL_VOWN                      (1<<19) /* bus ownership (release = 0, acquire/hold = 1) */
335# define        UNIV_MAST_CTL_VOWN_ACK          (1<<18) /* bus ownership (not owned = 0, acquired/held = 1) */
336# define        UNIV_MAST_CTL_PABS(val)         (((val)&0x3)<<3*4)      /* PCI aligned burst size (32,64,128 byte / 0x3 is reserved) */
337# define        UNIV_MAST_CTL_BUS_NO(val)       (((val)&0xff)<<0*4)     /* PCI bus number */
338
339#define         UNIV_REGOFF_MISC_CTL    0x404   /* misc control register */
340# define        UNIV_MISC_CTL_VBTO(val)         (((val)&0x7)<<7*4)      /* VME bus timeout (0=disable, 16*2^(val-1) us) */
341# define        UNIV_MISC_CTL_VARB                      (1<<26) /* VME bus arbitration mode (0=round robin, 1= priority) */
342# define        UNIV_MISC_CTL_VARBTO(val)       (((val)&0x3)<<6*4)      /* arbitration time out: disable, 16us, 256us, reserved */
343# define        UNIV_MISC_CTL_SW_LRST           (1<<23) /* software PCI reset */
344# define        UNIV_MISC_CTL_SW_SYSRST         (1<<22) /* software VME reset */
345# define        UNIV_MISC_CTL_BI                        (1<<20) /* BI mode */
346# define        UNIV_MISC_CTL_ENGBI                     (1<<19) /* enable global BI mode initiator */
347# define        UNIV_MISC_CTL_SYSCON            (1<<17) /* (R/W) 1:universe is system controller */
348# define        UNIV_MISC_CTL_V64AUTO           (1<<16) /* (R/W) 1:initiate VME64 auto id slave participation */
349
350/* U2SPEC described in VGM manual */
351/* NOTE: the Joerger vtr10012_8 needs the timing to be tweaked!!!! READt27 must be _no_delay_
352 */
353#define         UNIV_REGOFF_U2SPEC              0x4fc
354# define        UNIV_U2SPEC_DTKFLTR                     (1<<12) /* DTAck filter: 0: slow, better filter; 1: fast, poorer filter */
355# define        UNIV_U2SPEC_MASt11                      (1<<10) /* Master parameter t11 (DS hi time during BLT and MBLTs) */
356# define        UNIV_U2SPEC_READt27_DEFAULT     (0<<8)  /* VME master parameter t27: (latch data after DTAck + 25ns) */
357# define        UNIV_U2SPEC_READt27_FAST        (1<<8)  /* VME master parameter t27: (latch data faster than 25ns)  */
358# define        UNIV_U2SPEC_READt27_NODELAY     (2<<8)  /* VME master parameter t27: (latch data without any delay)  */
359# define        UNIV_U2SPEC_POSt28_FAST         (1<<2)  /* VME slave parameter t28: (faster time of DS to DTAck for posted write) */
360# define        UNIV_U2SPEC_PREt28_FAST         (1<<0)  /* VME slave parameter t28: (faster time of DS to DTAck for prefetch read) */
361
362/* Location Monitor control register */
363#define         UNIV_REGOFF_LM_CTL              0xf64
364# define        UNIV_LM_CTL_EN                          (1<<31) /* image enable */ 
365# define        UNIV_LM_CTL_PGM                         (1<<23) /* program AM */
366# define        UNIV_LM_CTL_DATA                        (1<<22) /* data AM */
367# define        UNIV_LM_CTL_SUPER                       (1<<21) /* supervisor AM */
368# define        UNIV_LM_CTL_USER                        (1<<20) /* user AM */
369# define        UNIV_LM_CTL_VAS_A16                     (0<<16) /* A16 */
370# define        UNIV_LM_CTL_VAS_A24                     (1<<16) /* A16 */
371# define        UNIV_LM_CTL_VAS_A32                     (2<<16) /* A16 */
372
373/* Location Monitor base address */
374#define         UNIV_REGOFF_LM_BS               0xf68
375
376/* VMEbus register access image control register */
377#define         UNIV_REGOFF_VRAI_CTL    0xf70
378# define        UNIV_VRAI_CTL_EN                        (1<<31) /* image enable */ 
379# define        UNIV_VRAI_CTL_PGM                       (1<<23) /* program AM */
380# define        UNIV_VRAI_CTL_DATA                      (1<<22) /* data AM */
381# define        UNIV_VRAI_CTL_SUPER                     (1<<21) /* supervisor AM */
382# define        UNIV_VRAI_CTL_USER                      (1<<20) /* user AM */
383# define        UNIV_VRAI_CTL_VAS_A16           (0<<16) /* A16 */
384# define        UNIV_VRAI_CTL_VAS_A24           (1<<16) /* A16 */
385# define        UNIV_VRAI_CTL_VAS_A32           (2<<16) /* A16 */
386
387/* VMEbus register acces image base address register */
388#define         UNIV_REGOFF_VRAI_BS             0xf74
389
390/* VMEbus CSR control register */
391#define         UNIV_REGOFF_VCSR_CTL    0xf80
392# define        UNIV_VCSR_CTL_EN                        (1<<31) /* image enable */
393# define        UNIV_VCSR_CTL_LAS_PCI_MEM       (0<<0)  /* pci mem space */
394# define        UNIV_VCSR_CTL_LAS_PCI_IO        (1<<0)  /* pci IO space */
395# define        UNIV_VCSR_CTL_LAS_PCI_CFG       (2<<0)  /* pci config space */
396
397/* VMEbus CSR translation offset */
398#define         UNIV_REGOFF_VCSR_TO             0xf84
399
400/* VMEbus AM code error log */
401#define         UNIV_REGOFF_V_AMERR             0xf88
402# define        UNIV_V_AMERR_AMERR(reg)         (((reg)>>26)&0x3f)      /* extract error log code */
403# define        UNIV_V_AMERR_IACK                       (1<<25) /* VMEbus IACK signal */
404# define        UNIV_V_AMERR_M_ERR                      (1<<24) /* multiple errors occurred */
405# define        UNIV_V_AMERR_V_STAT                     (1<<23) /* log status valid (write 1 to clear) */
406
407/* VMEbus address error log */
408#define         UNIV_REGOFF_VAERR               0xf8c           /* address of fault address (if MERR_V_STAT valid) */
409
410/* VMEbus CSR bit clear register */
411#define         UNIV_REGOFF_VCSR_CLR    0xff4
412# define        UNIV_VCSR_CLR_RESET                     (1<<31) /* read/negate LRST (can only be written from VME bus */
413# define        UNIV_VCSR_CLR_SYSFAIL           (1<<30) /* read/negate SYSFAIL */
414# define        UNIV_VCSR_CLR_FAIL                      (1<<29) /* read: board has failed */
415
416/* VMEbus CSR bit set register */
417#define         UNIV_REGOFF_VCSR_SET            (0xff8)
418# define        UNIV_VCSR_SET_RESET                     (1<<31) /* read/assert LRST (can only be written from VME bus */
419# define        UNIV_VCSR_SET_SYSFAIL           (1<<30) /* read/assert SYSFAIL */
420# define        UNIV_VCSR_SET_FAIL                      (1<<29) /* read: board has failed */
421
422/* VMEbus CSR base address register */
423#define         UNIV_REGOFF_VCSR_BS             0xffc
424#define         UNIV_VCSR_BS_MASK                       (0xfff80000)
425
426#ifdef __cplusplus
427extern "C" {
428#endif
429
430/* base address and IRQ line of 1st universe bridge
431 * NOTE: vmeUniverseInit() must be called before
432 *       these may be used.
433 */
434extern volatile LERegister *vmeUniverse0BaseAddr;
435extern int vmeUniverse0PciIrqLine;
436
437
438/* Initialize the driver */
439int
440vmeUniverseInit(void);
441
442/* setup the universe chip, i.e. disable most of its
443 * mappings, reset interrupts etc.
444 */
445void
446vmeUniverseReset(void);
447
448/* avoid pulling stdio.h into this header.
449 * Applications that want a declaration of the
450 * following routines should
451 *  #include <stdio.h>
452 *  #define _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
453 *  #include <vmeUniverse.h>
454 */
455#ifdef _VME_UNIVERSE_DECLARE_SHOW_ROUTINES
456/* print the current configuration of all master ports to
457 * f (stderr if NULL)
458 */
459void
460vmeUniverseMasterPortsShow(FILE *f);
461
462/* print the current configuration of all slave ports to
463 * f (stderr if NULL)
464 */
465void
466vmeUniverseSlavePortsShow(FILE *f);
467#else
468void
469vmeUniverseMasterPortsShow();
470void
471vmeUniverseSlavePortsShow();
472#endif
473
474/* disable all master or slave ports, respectively */
475void
476vmeUniverseDisableAllMasters(void);
477
478void
479vmeUniverseDisableAllSlaves(void);
480
481/* configure a master port
482 *
483 *   port:          port number 0..3  (0..7 for a UniverseII)
484 *
485 *   address_space: vxWorks compliant addressing mode identifier
486 *                  (see vme.h). The most important are:
487 *                    0x0d - A32, Sup, Data
488 *                    0x3d - A24, Sup, Data
489 *                    0x2d - A16, Sup, Data
490 *                  additionally, the value 0 is accepted; it will
491 *                  disable this port.
492 *   vme_address:   address on the vme_bus of this port.
493 *   local_address: address on the pci_bus of this port.
494 *   length:        size of this port.
495 *
496 *   NOTE: the addresses and length parameters must be aligned on a
497 *         2^16 byte (0x10000) boundary, except for port 4 (only available
498 *         on a UniverseII), where the alignment can be 4k (4096).
499 *
500 *   RETURNS: 0 on success, -1 on failure. Error messages printed to stderr.
501 */
502
503int
504vmeUniverseMasterPortCfg(
505        unsigned long   port,
506        unsigned long   address_space,
507        unsigned long   vme_address,
508        unsigned long   local_address,
509        unsigned long   length);
510
511/* translate an address through the bridge
512 *
513 * vmeUniverseXlateAddr(0,0,addr,as,&result)
514 * yields a VME a address that reflects
515 * a local memory location as seen from the VME bus through the universe
516 * VME slave.
517 *
518 * likewise does vmeUniverseXlateAddr(1,0,addr,as,&result)
519 * translate a VME bus addr (through the VME master) to the
520 * PCI side of the bridge.
521 *
522 * a valid address space modifier must be specified.
523 *
524 * The 'reverse' parameter may be used to find a reverse
525 * mapping, i.e. the pci address in a master window can be
526 * found if the respective vme address is known etc.
527 *
528 * RETURNS: translated address in *pbusAdrs / *plocalAdrs
529 *
530 *          0:  success
531 *          -1: address/modifier not found in any bridge port
532 *          -2: invalid modifier
533 */
534int
535vmeUniverseXlateAddr(
536        int master,             /* look in the master windows */
537        int reverse,            /* reverse mapping; for masters: map local to VME */
538        unsigned long as,       /* address space */
539        unsigned long addr,     /* address to look up */
540        unsigned long *paOut/* where to put result */
541        );
542
543/* configure a VME slave (PCI master) port */
544int
545vmeUniverseSlavePortCfg(
546        unsigned long   port,
547        unsigned long   address_space,
548        unsigned long   vme_address,
549        unsigned long   local_address,
550        unsigned long   length);
551
552/* start a (direct, not linked) DMA transfer
553 *
554 * NOTE:  DCTL and DGCS must be set up
555 *        prior to calling this routine
556 */
557int
558vmeUniverseStartDMA(
559        unsigned long local_addr,
560        unsigned long vme_addr,
561        unsigned long count);
562
563/* read a register in PCI memory space
564 * (offset being one of the declared constants)
565 */
566unsigned long
567vmeUniverseReadReg(unsigned long offset);
568
569/* write a register in PCI memory space */
570void
571vmeUniverseWriteReg(unsigned long value, unsigned long offset);
572
573/* convert an array of unsigned long values to LE (as needed
574 * when the universe reads e.g. DMA descriptors from PCI)
575 */
576void
577vmeUniverseCvtToLE(unsigned long *ptr, unsigned long num);
578
579/* reset the VME bus */
580static inline void
581vmeUniverseResetBus(void)
582{
583        vmeUniverseWriteReg(
584                vmeUniverseReadReg(UNIV_REGOFF_MISC_CTL) | UNIV_MISC_CTL_SW_SYSRST,
585                UNIV_REGOFF_MISC_CTL);
586}
587
588#ifdef __rtems__
589/* VME Interrupt Handler functionality */
590
591/* we dont use the current RTEMS/BSP interrupt API for the
592 * following reasons:
593 *
594 *    - RTEMS/BSP API does not pass an argument to the ISR :-( :-(
595 *    - no separate vector space for VME vectors. Some vectors would
596 *      have to overlap with existing PCI/ISA vectors.
597 *    - RTEMS/BSP API allocates a structure for every possible vector
598 *    - the irq_on(), irq_off() functions add more bloat than helping.
599 *      They are (currently) only used by the framework to disable
600 *      interrupts at the device level before removing a handler
601 *      and to enable interrupts after installing a handler.
602 *      These operations may as well be done by the driver itself.
603 *
604 * Hence, we maintain our own (VME) handler table and hook our PCI
605 * handler into the standard RTEMS/BSP environment. Our handler then
606 * dispatches VME interrupts.
607 */
608
609typedef void (*VmeUniverseISR) (void *usrArg, unsigned long vector);
610
611/* install a handler for a VME vector
612 * RETURNS 0 on success, nonzero on failure.
613 */
614int
615vmeUniverseInstallISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
616
617/* remove a handler for a VME vector. The vector and usrArg parameters
618 * must match the respective parameters used when installing the handler.
619 * RETURNS 0 on success, nonzero on failure.
620 */
621int
622vmeUniverseRemoveISR(unsigned long vector, VmeUniverseISR handler, void *usrArg);
623
624/* query for the currently installed ISR and usr parameter at a given vector
625 * RETURNS: ISR or 0 (vector too big or no ISR installed)
626 */
627VmeUniverseISR
628vmeUniverseISRGet(unsigned long vector, void **parg);
629
630/* utility routines to enable/disable a VME IRQ level
631 *
632 * RETURNS 0 on success, nonzero on failure
633 */
634int
635vmeUniverseIntEnable(unsigned int level);
636int
637vmeUniverseIntDisable(unsigned int level);
638
639
640/* use these special vectors to connect a handler to the
641 * universe specific interrupts (such as "DMA done",
642 * VOWN, error irqs etc.)
643 * NOTE: The wrapper clears all status LINT bits (except
644 * for regular VME irqs). Also note that it is the user's
645 * responsibility to enable the necessary interrupts in
646 * LINT_EN
647 *
648 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
649 * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER
650 * DEPENDS ON IT
651 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
652 *
653 */
654#define UNIV_VOWN_INT_VEC                       256
655#define UNIV_DMA_INT_VEC                        257
656#define UNIV_LERR_INT_VEC                       258
657#define UNIV_VERR_INT_VEC                       259
658#define UNIV_VME_SW_IACK_INT_VEC        260
659#define UNIV_PCI_SW_INT_VEC                     261
660#define UNIV_SYSFAIL_INT_VEC            262
661#define UNIV_ACFAIL_INT_VEC                     263
662#define UNIV_MBOX0_INT_VEC                      264
663#define UNIV_MBOX1_INT_VEC                      265
664#define UNIV_MBOX2_INT_VEC                      266
665#define UNIV_MBOX3_INT_VEC                      267
666#define UNIV_LM0_INT_VEC                        268
667#define UNIV_LM1_INT_VEC                        269
668#define UNIV_LM2_INT_VEC                        270
669#define UNIV_LM3_INT_VEC                        271
670
671#define UNIV_NUM_INT_VECS                       272
672
673/* the universe interrupt handler is capable of routing all sorts of
674 * (VME) interrupts to 8 different lines (some of) which may be hooked up
675 * in a (board specific) way to a PIC.
676 *
677 * This driver only supports at most two lines. It routes the 7 VME
678 * interrupts to the main line and optionally, it routes the 'special'
679 * interrupts generated by the universe itself (DMA done, VOWN etc.)
680 * to a second line. If no second line is available, all IRQs are routed
681 * to the main line.
682 *
683 * Because the driver has no way to figure out which lines are actually
684 * wired to the PIC, this information has to be provided when installing
685 * the manager.
686 *
687 * Hence the manager sets up routing VME interrupts to 1 or 2 universe
688 * OUTPUTS. However, it must also be told to which PIC INPUTS they
689 * are wired.
690 * Optionally, the first PIC input line can be read from PCI config space
691 * but the second must be passed to this routine. Note that the info read
692 * from PCI config space is wrong for many boards!
693 *
694 * PARAMETERS:
695 *       vmeIrqUnivOut: to which output pin (of the universe) should the 7
696 *                                      VME irq levels be routed.
697 *       vmeIrqPicLine: specifies to which PIC input the 'main' output is
698 *                      wired. If passed a value < 0, the driver reads this
699 *                      information from PCI config space ("IRQ line").
700 *   specialIrqUnivOut: to which output pin (of the universe) should the
701 *                      internally irqs be routed. Use 'vmeIRQunivOut'
702 *                      if < 0.
703 *   specialIrqPicLine: specifies to which PIC input the 'special' output
704 *                      pin is wired. The wiring of the 'vmeIRQunivOut' to
705 *                      the PIC is determined by reading PCI config space.
706 *
707 * RETURNS: 0 on success, -1 on failure.
708 *                                             
709 */
710int
711vmeUniverseInstallIrqMgr(int vmeIrqUnivOut,
712                                                 int vmeIrqPicLine,
713                                                 int specialIrqUnivOut,
714                                                 int specialIrqPicLine);
715
716#endif
717
718#ifdef __cplusplus
719}
720#endif
721
722#endif
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