source: rtems/c/src/lib/libbsp/shared/vmeUniverse/vmeTsi148.h @ afd4c7b

4.104.114.84.9
Last change on this file since afd4c7b was afd4c7b, checked in by Till Straumann <strauman@…>, on Dec 13, 2006 at 8:04:05 PM
  • vmeUniverse/vme_am_defs.h: Added address modifiers for 2eVME. Added flags for 2eSST and DBW16.
  • vmeUniverse/vmeUniverse.h: Removed AM definitions and include vme_am_defs.h instead. Declare new routine vmeUniverseMapCRG(). Export 'irq manager' API only if INSIDE_RTEMS_BSP defined. Renamed 'shared' argument to vmeUniverseInstallIrqMgrAlt() to 'flags' since now more options are available. Added new flag to install 'posted-write' workaround.
  • vmeUniverse/vmeUniverse.c: Allow BSP to override BSP_PCI2LOCAL_ADDR() macro. Data width of outbound port can now be restricted to 16-bit (if new DBW16 flag set in address modifier). Added vmeUniverseMapCRG() for mapping local registers onto VME. Interrupt manager now implements a workaround (enabled at installation time) which flushes the write-fifo after user ISR returns. This requires the universe's registers to be accessible from VME (either CSR space or CRG mapped to A16/A24/A32), though.
  • vmeUniverse/vmeTsi148.h: vmeTsi148ClearVMEBusErrors() now returns the fault address as a 32-bit address (not ulonglong anymore). The driver only supports 32-bit addresses. Declare new routine vmeTsi148MapCRG(). Export 'irq manager' API only if INSIDE_RTEMS_BSP defined. Renamed 'shared' argument to vmeTsi148InstallIrqMgrAlt() to 'flags' to allow more options to be supported. Added comments explaining the 'posted-write' workaround implemented by the interrupt manager.
  • vmeUniverse/vmeTsi148.c: Clear 'SYSFAIL' during initialization. Allow BSP to override BSP_PCI2LOCAL_ADDR() macro. Added support for 2eSST when configuring windows (untested - I have no 2eSST). Added vmeTsi148MapCRG() for mapping local registers onto VME. Implemented 'posted-write' workaround for interrupt manager (consult source for details).
  • Property mode set to 100644
File size: 20.0 KB
Line 
1/* $Id$ */
2#ifndef VME_TSI148_DRIVER_H
3#define VME_TSI148_DRIVER_H
4
5/* Routines to configure and use the Tundra Tsi148 VME bridge
6 * Author: Till Straumann <strauman@slac.stanford.edu>
7 *         Sept. 2005.
8 */
9
10#include <stdint.h>
11#include <bsp/vme_am_defs.h>
12
13
14/* NOTE: A64 currently not implemented */
15
16/* These can be ored with the AM */
17
18/* NOTE: unlike the universe, the tsi148 doesn't allow for disabling posted writes ! */
19
20#define VME_MODE_PREFETCH_ENABLE                        VME_AM_IS_MEMORY
21#define _LD_VME_MODE_PREFETCHSZ                         24
22#define VME_MODE_PREFETCH_SIZE(x)                       (((x)&3)<<_LD_VME_MODE_PREFETCHSZ)
23
24/* These bits can be or'ed with the address-modifier when calling
25 * the 'XlateAddr' routine below to further qualify the
26 * search criteria.
27 */
28#define VME_MODE_MATCH_MASK                                     (3<<30)
29#define VME_MODE_EXACT_MATCH                            (2<<30) /* all bits must match */
30#define VME_MODE_AS_MATCH                                       (1<<30) /* only A16/24/32 must match */
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36typedef volatile uint32_t BERegister; /* emphasize contents are big endian */
37
38/*
39 * Scan the PCI busses for the Nth (N=='instance') Tsi148 VME bridge.
40 *
41 * RETURNS:
42 *    contents of the IRQ_LINE PCI config register on Success,
43 *    the base address of the Tsi148 register block is stored in
44 *    *pbase.
45 *    -1 on error (no Tsi found, error accessing PCI config space).
46 *
47 * SIDE_EFFECTS: PCI busmaster and response to memory addresses is enabled.
48 */
49int
50vmeTsi148FindPciBase(int instance, BERegister **pbase);
51
52/* Initialize driver for Nth Tsi148 device found.
53 * This routine does not change any registers but
54 * just scans the PCI bus for Tsi bridges and initializes
55 * a driver slot.
56 *
57 * RETURNS: 0 on success, nonzero on error (or if no Tsi148
58 *          device is found).
59 */
60int
61vmeTsi148InitInstance(unsigned instance);
62
63/* Initialize driver with 1st Tsi148 bridge found
64 * RETURNS: (see vmeTsi148InitInstance()).
65 */
66int
67vmeTsi148Init(void);
68
69/* setup the tsi148 chip, i.e. disable most of its
70 * mappings, reset interrupts etc.
71 */
72void
73vmeTsi148ResetXX(BERegister *base);
74
75/* setup the tsi148 connected to the first driver slot */
76void
77vmeTsi148Reset();
78
79/* NOTE: all non-'XX' versions of driver entry points which
80 *       have an associated 'XX' entry point operate on the
81 *       device connected to the 1st driver slot.
82 */
83
84/* configure a outbound port
85 *
86 *   port:          port number 0..7
87 *
88 *   address_space: vxWorks compliant addressing mode identifier
89 *                  (see vme.h). The most important are:
90 *                    0x0d - A32, Sup, Data
91 *                    0x3d - A24, Sup, Data
92 *                    0x2d - A16, Sup, Data
93 *                  additionally, the value 0 is accepted; it will
94 *                  disable this port.
95 *   vme_address:   address on the vme_bus of this port.
96 *   local_address: address on the pci_bus of this port.
97 *   length:        size of this port.
98 *
99 *   NOTE: the addresses and length parameters must meet certain alignment
100 *         requirements (see Tsi148 documentation).
101 *
102 *   RETURNS: 0 on success, -1 on failure. Error messages printed to stderr.
103 */
104
105int
106vmeTsi148OutboundPortCfgXX(
107        BERegister              *base,
108        unsigned long   port,
109        unsigned long   address_space,
110        unsigned long   vme_address,
111        unsigned long   pci_address,
112        unsigned long   length);
113
114int
115vmeTsi148OutboundPortCfg(
116        unsigned long   port,
117        unsigned long   address_space,
118        unsigned long   vme_address,
119        unsigned long   pci_address,
120        unsigned long   length);
121
122
123/* configure a VME inbound (PCI master) port */
124int
125vmeTsi148InboundPortCfgXX(
126        BERegister              *base,
127        unsigned long   port,
128        unsigned long   address_space,
129        unsigned long   vme_address,
130        unsigned long   pci_address,
131        unsigned long   length);
132
133int
134vmeTsi148InboundPortCfg(
135        unsigned long   port,
136        unsigned long   address_space,
137        unsigned long   vme_address,
138        unsigned long   pci_address,
139        unsigned long   length);
140
141/* Translate an address through the bridge
142 *
143 * vmeTsi248XlateAddr(0,0,as,addr,&result)
144 * yields a VME a address that reflects
145 * a local memory location as seen from the VME bus through the
146 * tsi148 VME inbound port.
147 *
148 * Likewise does vmeTsi148XlateAddr(1,0,as,addr,&result)
149 * translate a VME bus addr (backwards, through the VME outbound
150 * port) to the PCI side of the bridge.
151 *
152 * A valid address space modifier must be specified.
153 * If VME_MODE_EXACT_MATCH is set, all the mode bits must
154 * match the requested mode. If VME_MODE_EXACT_MATCH is not
155 * set in the mode word, only the basic mode (address-space,
156 * sup/usr and pgm/data) is compared.
157 *
158 * The 'reverse' parameter may be used to find a reverse
159 * mapping, i.e. the pci address in a outbound window can be
160 * found if the respective vme address is known etc.
161 *
162 * RETURNS: translated address in *pbusAdrs / *plocalAdrs
163 *
164 *          0:  success
165 *          -1: address/modifier not found in any bridge port
166 *          -2: invalid modifier
167 */
168
169int
170vmeTsi148XlateAddrXX(
171        BERegister *base,       /* TSI 148 base address */
172        int outbound,           /* look in the outbound windows */
173        int reverse,            /* reverse mapping; for outbound ports: map local to VME */
174        unsigned long as,       /* address space */
175        unsigned long aIn,      /* address to look up */
176        unsigned long *paOut/* where to put result */
177        );
178
179int
180vmeTsi148XlateAddr(
181        int outbound,           /* look in the outbound windows */
182        int reverse,            /* reverse mapping; for outbound: map local to VME */
183        unsigned long as,       /* address space */
184        unsigned long aIn,      /* address to look up */
185        unsigned long *paOut/* where to put result */
186        );
187
188
189/* avoid pulling stdio.h into this header.
190 * Applications that want a declaration of the
191 * following routines should
192 *  #include <stdio.h>
193 *  #define _VME_TSI148_DECLARE_SHOW_ROUTINES
194 *  #include <vmeTsi148.h>
195 */
196#ifdef _VME_TSI148_DECLARE_SHOW_ROUTINES
197
198/* Print the current configuration of all outbound ports to
199 * f (stdout if NULL)
200 */
201
202void
203vmeTsi148OutboundPortsShowXX(BERegister *base, FILE *f);
204
205void
206vmeTsi148OutboundPortsShow(FILE *f);
207
208/* Print the current configuration of all inbound ports to
209 * f (stdout if NULL)
210 */
211
212void
213vmeTsi148InboundPortsShowXX(BERegister *base, FILE *f);
214
215void
216vmeTsi148InboundPortsShow(FILE *f);
217
218#endif
219
220
221/* Disable all in- or out-bound ports, respectively */
222void
223vmeTsi148DisableAllInboundPortsXX(BERegister *base);
224
225void
226vmeTsi148DisableAllInboundPorts(void);
227
228void
229vmeTsi148DisableAllOutboundPortsXX(BERegister *base);
230
231void
232vmeTsi148DisableAllOutboundPorts(void);
233
234#       define TSI_VEAT_VES                     (1<<31)
235#       define TSI_VEAT_VEOF            (1<<30)
236#       define TSI_VEAT_VESCL           (1<<29)
237#       define TSI_VEAT_2eOT            (1<<21)
238#       define TSI_VEAT_2eST            (1<<20)
239#       define TSI_VEAT_BERR            (1<<19)
240#       define TSI_VEAT_LWORD           (1<<18)
241#       define TSI_VEAT_WRITE           (1<<17)
242#       define TSI_VEAT_IACK            (1<<16)
243#       define TSI_VEAT_DS1                     (1<<15)
244#       define TSI_VEAT_DS0                     (1<<14)
245#       define TSI_VEAT_AM(v)           (((v)>>8)&63)
246#       define TSI_VEAT_XAM(v)          ((v)&255)
247
248/* Check and clear the error (AKA 'exception') register.
249 * Note that the Tsi148 does *not* propagate VME bus errors of any kind to
250 * the PCI status register and hence this routine (or registering an ISR
251 * to the TSI_VERR_INT_VEC) is the only means for detecting a bus error.
252 *
253 * RETURNS:
254 *   0 if no error has occurred since this routine was last called.
255 *     Contents of the 'VEAT' register (bit definitions as above)
256 *     otherwise.
257 *   If a non-NULL 'paddr'  argument is provided then the lower 32-bit
258 *   of the error address is stored in *paddr (only if return value is
259 *   non-zero).
260 *
261 * SIDE EFFECTS: this routine clears the error attribute register, allowing
262 *               for future errors to be latched.
263 */
264unsigned long
265vmeTsi148ClearVMEBusErrorsXX(BERegister *base, uint32_t *paddr);
266
267unsigned long
268vmeTsi148ClearVMEBusErrors(uint32_t *paddr);
269
270/* Map internal register block to VME.
271 *
272 * This routine is intended for BSP implementors. The registers must be
273 * accessible from VME so that the interrupt handler can flush the
274 * bridge FIFO (see below).
275 *
276 *            vme_base: VME address where the TSI registers (4k) can be mapped.
277 *                      This VME address must fall into a range covered by
278 *                      any pre-configured outbound window.
279 *       address_space: The desired VME address space.
280 *                      (all of SUP/USR/PGM/DATA are always accepted).
281 *
282 * See NOTES [vmeTsi148InstallIrqMgrAlt()] below for further information.
283 *
284 * RETURNS: 0 on success, nonzero on error. It is not possible (and results
285 *          in a non-zero return code) to change the CRG VME address after
286 *          initializing the interrupt manager as it uses the CRG.
287 */
288int
289vmeTsi148MapCRGXX(BERegister *base, uint32_t vme_base, uint32_t address_space);
290
291int
292vmeTsi148MapCRG(uint32_t vme_base, uint32_t address_space);
293
294
295/* VME Interrupt Handler functionality */
296
297/* we dont use the current RTEMS/BSP interrupt API for the
298 * following reasons:
299 *
300 *    - RTEMS/BSP API does not pass an argument to the ISR :-( :-(
301 *    - no separate vector space for VME vectors. Some vectors would
302 *      have to overlap with existing PCI/ISA vectors.
303 *    - RTEMS/BSP API allocates a structure for every possible vector
304 *    - the irq_on(), irq_off() functions add more bloat than helping.
305 *      They are (currently) only used by the framework to disable
306 *      interrupts at the device level before removing a handler
307 *      and to enable interrupts after installing a handler.
308 *      These operations may as well be done by the driver itself.
309 *
310 * Hence, we maintain our own (VME) handler table and hook our PCI
311 * handler into the standard RTEMS/BSP environment. Our handler then
312 * dispatches VME interrupts.
313 */
314
315typedef void (*VmeTsi148ISR) (void *usrArg, unsigned long vector);
316
317/* install a handler for a VME vector
318 * RETURNS 0 on success, nonzero on failure.
319 */
320int
321vmeTsi148InstallISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg);
322
323/* remove a handler for a VME vector. The vector and usrArg parameters
324 * must match the respective parameters used when installing the handler.
325 * RETURNS 0 on success, nonzero on failure.
326 */
327int
328vmeTsi148RemoveISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg);
329
330/* query for the currently installed ISR and usr parameter at a given vector
331 * RETURNS: ISR or 0 (vector too big or no ISR installed)
332 */
333VmeTsi148ISR
334vmeTsi148ISRGet(unsigned long vector, void **parg);
335
336/* utility routines to enable/disable a VME IRQ level
337 *
338 * To enable/disable the internal interrupt sources (special vectors above)
339 * pass a vector argument > 255.
340 *
341 * RETURNS 0 on success, nonzero on failure
342 */
343int
344vmeTsi148IntEnable(unsigned int level);
345
346int
347vmeTsi148IntDisable(unsigned int level);
348
349/* Check if an interrupt level or internal source is enabled:
350 *
351 * 'level': VME level 1..7 or internal special vector > 255
352 *
353 * RETURNS: value > 0 if interrupt is currently enabled,
354 *          zero      if interrupt is currently disabled,
355 *          -1        on error (invalid argument).
356 */
357
358int
359vmeTsi148IntIsEnabled(unsigned int level);
360
361/* Set IACK width (1,2, or 4 bytes) for a given interrupt level.
362 *
363 * 'width' arg may be 0,1,2 or 4. If zero, the currently active
364 * value is returned but not modified.
365 *
366 * RETURNS: old width or -1 if invalid argument.
367 */
368
369int
370vmeTsi148SetIackWidth(int level, int width);
371
372/* Change the routing of IRQ 'level' to 'pin'.
373 * If the BSP connects more than one of the four
374 * physical interrupt lines from the tsi148 to
375 * the board's PIC then you may change the physical
376 * line a given 'level' is using. By default,
377 * all 7 VME levels use the first wire (pin==0) and
378 * all internal sources use the (optional) second
379 * wire (pin==1) [The driver doesn't support more than
380 * four wires].
381 * This feature is useful if you want to make use of
382 * different hardware priorities of the PIC. Let's
383 * say you want to give IRQ level 7 the highest priority.
384 * You could then give 'pin 0' a higher priority (at the
385 * PIC) and 'pin 1' a lower priority and issue.
386 *
387 *   for ( i=1; i<7; i++ ) vmeTsi148IntRoute(i, 1);
388 *
389 * PARAMETERS:
390 *    'level' : VME interrupt level '1..7' or one of
391 *              the internal sources. Pass the internal
392 *              source's vector number (>=256).
393 *    'pin'   : a value of 0 routes the requested IRQ to
394 *              the first line registered with the manager,
395 *              a value of 1 routes it to the second wire
396 *              etc.
397 *
398 * RETURNS: 0 on success, nonzero on error (invalid arguments)
399 *
400 * NOTES:       - DONT change the tsi148 'map' registers
401 *            directly. The driver caches routing internally.
402 *          - support for the extra wires (beyond wire #0) is
403 *            board dependent. If the board only provides
404 *            a single physical wire from the tsi148 to
405 *            the PIC then the feature might not be available.
406 */
407int
408vmeTsi148IntRoute(unsigned int level, unsigned int pin);
409
410/* Raise a VME Interrupt at 'level' and respond with 'vector' to a
411 * handler on the VME bus. (The handler could be a different board
412 * or the tsi148 itself.
413 *
414 * Note that you could install a interrupt handler at TSI_VME_SW_IACK_INT_VEC
415 * to be notified of an IACK cycle having completed.
416 *
417 * This routine is mainly FOR TESTING.
418 *
419 * NOTES:
420 *   - the VICR register is modified.
421 *   - NO MUTUAL EXCLUSION PROTECTION (reads VICR, modifies then writes back).
422 *     If several users need access to VICR it is their responsibility to serialize access.
423 *
424 * Arguments:
425 *  'level':  interrupt level, 1..7
426 *  'vector': vector number (0..255) that the tsi148 puts on the bus in response to
427 *            an IACK cycle.
428 *
429 * RETURNS:
430 *        0:  Success
431 *       -1:  Invalid argument (level not 1..7, vector >= 256)
432 *       -2:  Interrupt 'level' already asserted (maybe nobody handles it).
433 *            You can manually clear it be setting the IRQC bit in
434 *            VICR. Make sure really nobody responds to avoid spurious
435 *            interrupts (consult tsi148 docs).
436 */
437
438int
439vmeTsi148IntRaiseXX(BERegister *base, int level, unsigned vector);
440
441int
442vmeTsi148IntRaise(int level, unsigned vector);
443
444/* Loopback test of the VME interrupt subsystem.
445 *  - installs ISRs on 'vector' and on TSI_VME_SW_IACK_INT_VEC
446 *  - asserts VME interrupt 'level'
447 *  - waits for both interrupts: 'ordinary' VME interrupt of 'level' and
448 *    IACK completion interrupt ('special' vector TSI_VME_SW_IACK_INT_VEC).
449 *
450 * NOTES:
451 *  - make sure no other handler responds to 'level'.
452 *  - make sure no ISR is installed on both vectors yet.
453 *  - ISRs installed by this routine are removed after completion.
454 *  - no concurrent access protection of all involved resources
455 *    (levels, vectors and registers  [see vmeTsi148IntRaise()])
456 *    is implemented.
457 *  - this routine is intended for TESTING (when implementing new BSPs etc.).
458 *  - one RTEMS message queue is temporarily used (created/deleted).
459 *
460 * RETURNS:
461 *                 0: Success.
462 *                -1: Invalid arguments.
463 *                 1: Test failed (outstanding interrupts).
464 * rtems_status_code: Failed RTEMS directive.
465 */
466
467int
468vmeTsi148IntLoopbackTst(int level, unsigned vector);
469
470/* use these special vectors to connect a handler to the
471 * tsi148 specific interrupts (such as "DMA done", SW or
472 * error irqs etc.)
473 * NOTE: The wrapper clears all status LINT bits (except
474 * for regular VME irqs). Also note that it is the user's
475 * responsibility to enable the necessary interrupts in
476 * LINT_EN
477 *
478 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
479 * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER
480 * DEPENDS ON IT
481 * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
482 *
483 * Deliberately, these vectors match the universe driver's
484 */
485/* 256 no VOWN interrupt */
486#define TSI_DMA_INT_VEC                 257
487#define TSI_LERR_INT_VEC                258
488#define TSI_VERR_INT_VEC                259
489/* 260 is reserved       */
490#define TSI_VME_SW_IACK_INT_VEC 261
491/* 262 no PCI SW IRQ     */
492#define TSI_SYSFAIL_INT_VEC             263
493#define TSI_ACFAIL_INT_VEC              264
494#define TSI_MBOX0_INT_VEC               265
495#define TSI_MBOX1_INT_VEC               266
496#define TSI_MBOX2_INT_VEC               267
497#define TSI_MBOX3_INT_VEC               268
498#define TSI_LM0_INT_VEC                 269
499#define TSI_LM1_INT_VEC                 270
500#define TSI_LM2_INT_VEC                 271
501#define TSI_LM3_INT_VEC                 272
502
503/* New vectors; only on TSI148 */
504#define TSI_VIES_INT_VEC                273
505#define TSI_DMA1_INT_VEC                274
506
507#define TSI_NUM_INT_VECS                275
508
509#ifdef __INSIDE_RTEMS_BSP__
510
511#include <stdarg.h>
512
513/* the tsi148 interrupt handler is capable of routing all sorts of
514 * (VME) interrupts to 4 different lines (some of) which may be hooked up
515 * in a (board specific) way to a PIC.
516 *
517 * This driver initially supports at most two lines (i.e., if the user
518 * doesn't re-route anything). By default, it routes the
519 * 7 VME interrupts to the main line and optionally, it routes the 'special'
520 * interrupts generated by the tsi148 itself (DMA done, SW irq etc.)
521 * to a second line. If no second line is available, all IRQs are routed
522 * to the main line.
523 *
524 * The routing of interrupts to the two lines can be modified (using
525 * the vmeTsi148IntRoute() call - see above - i.e., to make use of
526 * different hardware priorities and/or more physically available lines.
527 *
528 * Because the driver has no way to figure out which lines are actually
529 * wired to the PIC, this information has to be provided when installing
530 * the manager.
531 *
532 * Hence the manager sets up routing VME interrupts to 1 or 2 tsi148
533 * OUTPUTS. However, it must also be told to which PIC INPUTS they
534 * are wired.
535 * Optionally, the first PIC input line can be read from PCI config space
536 * but the second must be passed to this routine. Note that the info read
537 * from PCI config space is wrong for some boards!
538 *
539 * PARAMETERS:
540 *              flags:  VMETSI148_IRQ_MGR_FLAG_SHARED: 
541 *                      use the BSP_install_rtems_shared_irq_handler() instead
542 *                      of BSP_install_rtems_irq_handler(). Use this if the PIC
543 *                      line is used by other devices, too.
544 *                      CAVEAT: shared interrupts need RTEMS workspace, i.e., the
545 *                      VME interrupt manager can only be installed
546 *                      *after workspace is initialized* if 'shared' is nonzero
547 *                      (i.e., *not* from bspstart()).
548 *
549 *           tsi_pin_0: to which output pin (of the tsi148) should the 7
550 *                                      VME irq levels be routed.
551 *
552 *           pic_pin_0: specifies to which PIC input the 'main' output is
553 *                      wired on your board. If passed a value < 0, the driver
554 *                      reads this information from PCI config space ("IRQ line").
555 *           ...      : up to three additional tsi_pin/pic_pin pairs can be
556 *                      specified if your board provides more physical wires.
557 *                      In any case must the varargs list be terminated by '-1'.
558 *
559 * RETURNS: 0 on success, -1 on failure.
560 *
561 * NOTES: The Tsi148 always does 'posted' writes through a FIFO buffer.
562 *        This effectively makes VME write operations asynchronous
563 *        which can have undesired side-effects.
564 *        In particular, consider the case of an ISR clearing the
565 *        interrupt condition by writing to a CSR. The write operation
566 *        doesn't really do anything but goes into the FIFO and
567 *        the user ISR returns. At this point, the interrupt manager
568 *        may find the IRQ still pending, trying another IACK
569 *        cycle. Because it is probable that at this time the FIFO
570 *        has been flushed and the CSR-write operation been effective,
571 *        the IACK then times out.
572 *        Note that this phenomenon becomes more obvious as CPUs
573 *        become faster.
574 *
575 *        To avoid this race condition and many VME drivers having
576 *        to be re-written, a VME read (having the desired side-effect
577 *        of flushing the write FIFO) must be issued between the
578 *        user ISR returning and the interrupt manager checking for
579 *        more pending interrupts.
580 *
581 *        Therefore, the BSP needs to map the Tsi148 register
582 *        block to VME so that a read over VME can be effectuated.
583 *        (In addition to being mapped to VME, the mapped address
584 *        range must be accessible through an outbound window.)
585 */
586
587#define VMETSI148_IRQ_MGR_FLAG_SHARED   1
588int
589vmeTsi148InstallIrqMgrAlt(int shared, int tsi_pin0, int pic_pin0, ...);
590
591int
592vmeTsi148InstallIrqMgrVa(int shared, int tsi_pin0, int pic_pin0, va_list ap);
593#endif
594
595#ifdef __cplusplus
596}
597#endif
598
599#endif
Note: See TracBrowser for help on using the repository browser.