[784e792] | 1 | /* $Id$ */ |
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| 2 | #ifndef VME_TSI148_DRIVER_H |
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| 3 | #define VME_TSI148_DRIVER_H |
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| 4 | |
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| 5 | /* Routines to configure and use the Tundra Tsi148 VME bridge |
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| 6 | * Author: Till Straumann <strauman@slac.stanford.edu> |
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| 7 | * Sept. 2005. |
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| 8 | */ |
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| 9 | |
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[afd4c7b] | 10 | #include <stdint.h> |
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[784e792] | 11 | #include <bsp/vme_am_defs.h> |
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| 12 | |
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[afd4c7b] | 13 | |
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[784e792] | 14 | /* NOTE: A64 currently not implemented */ |
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| 15 | |
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| 16 | /* These can be ored with the AM */ |
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| 17 | |
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[afd4c7b] | 18 | /* NOTE: unlike the universe, the tsi148 doesn't allow for disabling posted writes ! */ |
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[784e792] | 19 | |
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[afd4c7b] | 20 | #define VME_MODE_PREFETCH_ENABLE VME_AM_IS_MEMORY |
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| 21 | #define _LD_VME_MODE_PREFETCHSZ 24 |
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| 22 | #define VME_MODE_PREFETCH_SIZE(x) (((x)&3)<<_LD_VME_MODE_PREFETCHSZ) |
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[784e792] | 23 | |
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[afd4c7b] | 24 | /* These bits can be or'ed with the address-modifier when calling |
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| 25 | * the 'XlateAddr' routine below to further qualify the |
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| 26 | * search criteria. |
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[784e792] | 27 | */ |
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[afd4c7b] | 28 | #define VME_MODE_MATCH_MASK (3<<30) |
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| 29 | #define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */ |
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| 30 | #define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */ |
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[784e792] | 31 | |
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| 32 | #ifdef __cplusplus |
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| 33 | extern "C" { |
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| 34 | #endif |
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| 35 | |
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[c2fc65b] | 36 | typedef volatile uint32_t BERegister; /* emphasize contents are big endian */ |
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[784e792] | 37 | |
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| 38 | /* |
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| 39 | * Scan the PCI busses for the Nth (N=='instance') Tsi148 VME bridge. |
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| 40 | * |
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| 41 | * RETURNS: |
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| 42 | * contents of the IRQ_LINE PCI config register on Success, |
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| 43 | * the base address of the Tsi148 register block is stored in |
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| 44 | * *pbase. |
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| 45 | * -1 on error (no Tsi found, error accessing PCI config space). |
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| 46 | * |
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| 47 | * SIDE_EFFECTS: PCI busmaster and response to memory addresses is enabled. |
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| 48 | */ |
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| 49 | int |
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| 50 | vmeTsi148FindPciBase(int instance, BERegister **pbase); |
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| 51 | |
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| 52 | /* Initialize driver for Nth Tsi148 device found. |
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| 53 | * This routine does not change any registers but |
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| 54 | * just scans the PCI bus for Tsi bridges and initializes |
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| 55 | * a driver slot. |
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| 56 | * |
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| 57 | * RETURNS: 0 on success, nonzero on error (or if no Tsi148 |
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| 58 | * device is found). |
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| 59 | */ |
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| 60 | int |
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| 61 | vmeTsi148InitInstance(unsigned instance); |
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| 62 | |
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| 63 | /* Initialize driver with 1st Tsi148 bridge found |
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| 64 | * RETURNS: (see vmeTsi148InitInstance()). |
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| 65 | */ |
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| 66 | int |
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| 67 | vmeTsi148Init(void); |
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| 68 | |
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| 69 | /* setup the tsi148 chip, i.e. disable most of its |
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| 70 | * mappings, reset interrupts etc. |
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| 71 | */ |
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| 72 | void |
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| 73 | vmeTsi148ResetXX(BERegister *base); |
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| 74 | |
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| 75 | /* setup the tsi148 connected to the first driver slot */ |
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| 76 | void |
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| 77 | vmeTsi148Reset(); |
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| 78 | |
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| 79 | /* NOTE: all non-'XX' versions of driver entry points which |
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| 80 | * have an associated 'XX' entry point operate on the |
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| 81 | * device connected to the 1st driver slot. |
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| 82 | */ |
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| 83 | |
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| 84 | /* configure a outbound port |
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| 85 | * |
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| 86 | * port: port number 0..7 |
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| 87 | * |
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| 88 | * address_space: vxWorks compliant addressing mode identifier |
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| 89 | * (see vme.h). The most important are: |
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| 90 | * 0x0d - A32, Sup, Data |
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| 91 | * 0x3d - A24, Sup, Data |
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| 92 | * 0x2d - A16, Sup, Data |
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| 93 | * additionally, the value 0 is accepted; it will |
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| 94 | * disable this port. |
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| 95 | * vme_address: address on the vme_bus of this port. |
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| 96 | * local_address: address on the pci_bus of this port. |
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| 97 | * length: size of this port. |
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| 98 | * |
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| 99 | * NOTE: the addresses and length parameters must meet certain alignment |
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| 100 | * requirements (see Tsi148 documentation). |
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| 101 | * |
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| 102 | * RETURNS: 0 on success, -1 on failure. Error messages printed to stderr. |
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| 103 | */ |
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| 104 | |
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| 105 | int |
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| 106 | vmeTsi148OutboundPortCfgXX( |
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| 107 | BERegister *base, |
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| 108 | unsigned long port, |
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| 109 | unsigned long address_space, |
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| 110 | unsigned long vme_address, |
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| 111 | unsigned long pci_address, |
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| 112 | unsigned long length); |
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| 113 | |
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| 114 | int |
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| 115 | vmeTsi148OutboundPortCfg( |
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| 116 | unsigned long port, |
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| 117 | unsigned long address_space, |
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| 118 | unsigned long vme_address, |
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| 119 | unsigned long pci_address, |
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| 120 | unsigned long length); |
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| 121 | |
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| 122 | |
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| 123 | /* configure a VME inbound (PCI master) port */ |
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| 124 | int |
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| 125 | vmeTsi148InboundPortCfgXX( |
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| 126 | BERegister *base, |
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| 127 | unsigned long port, |
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| 128 | unsigned long address_space, |
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| 129 | unsigned long vme_address, |
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| 130 | unsigned long pci_address, |
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| 131 | unsigned long length); |
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| 132 | |
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| 133 | int |
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| 134 | vmeTsi148InboundPortCfg( |
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| 135 | unsigned long port, |
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| 136 | unsigned long address_space, |
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| 137 | unsigned long vme_address, |
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| 138 | unsigned long pci_address, |
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| 139 | unsigned long length); |
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| 140 | |
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| 141 | /* Translate an address through the bridge |
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| 142 | * |
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| 143 | * vmeTsi248XlateAddr(0,0,as,addr,&result) |
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| 144 | * yields a VME a address that reflects |
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| 145 | * a local memory location as seen from the VME bus through the |
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| 146 | * tsi148 VME inbound port. |
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| 147 | * |
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| 148 | * Likewise does vmeTsi148XlateAddr(1,0,as,addr,&result) |
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| 149 | * translate a VME bus addr (backwards, through the VME outbound |
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| 150 | * port) to the PCI side of the bridge. |
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| 151 | * |
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| 152 | * A valid address space modifier must be specified. |
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| 153 | * If VME_MODE_EXACT_MATCH is set, all the mode bits must |
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| 154 | * match the requested mode. If VME_MODE_EXACT_MATCH is not |
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| 155 | * set in the mode word, only the basic mode (address-space, |
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| 156 | * sup/usr and pgm/data) is compared. |
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| 157 | * |
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| 158 | * The 'reverse' parameter may be used to find a reverse |
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| 159 | * mapping, i.e. the pci address in a outbound window can be |
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| 160 | * found if the respective vme address is known etc. |
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| 161 | * |
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| 162 | * RETURNS: translated address in *pbusAdrs / *plocalAdrs |
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| 163 | * |
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| 164 | * 0: success |
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| 165 | * -1: address/modifier not found in any bridge port |
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| 166 | * -2: invalid modifier |
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| 167 | */ |
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| 168 | |
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| 169 | int |
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| 170 | vmeTsi148XlateAddrXX( |
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| 171 | BERegister *base, /* TSI 148 base address */ |
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| 172 | int outbound, /* look in the outbound windows */ |
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| 173 | int reverse, /* reverse mapping; for outbound ports: map local to VME */ |
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| 174 | unsigned long as, /* address space */ |
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| 175 | unsigned long aIn, /* address to look up */ |
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| 176 | unsigned long *paOut/* where to put result */ |
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| 177 | ); |
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| 178 | |
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| 179 | int |
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| 180 | vmeTsi148XlateAddr( |
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| 181 | int outbound, /* look in the outbound windows */ |
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| 182 | int reverse, /* reverse mapping; for outbound: map local to VME */ |
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| 183 | unsigned long as, /* address space */ |
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| 184 | unsigned long aIn, /* address to look up */ |
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| 185 | unsigned long *paOut/* where to put result */ |
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| 186 | ); |
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| 187 | |
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[43ea369] | 188 | |
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| 189 | /* avoid pulling stdio.h into this header. |
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| 190 | * Applications that want a declaration of the |
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| 191 | * following routines should |
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| 192 | * #include <stdio.h> |
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| 193 | * #define _VME_TSI148_DECLARE_SHOW_ROUTINES |
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| 194 | * #include <vmeTsi148.h> |
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| 195 | */ |
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| 196 | #ifdef _VME_TSI148_DECLARE_SHOW_ROUTINES |
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| 197 | |
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[784e792] | 198 | /* Print the current configuration of all outbound ports to |
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| 199 | * f (stdout if NULL) |
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| 200 | */ |
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| 201 | |
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| 202 | void |
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| 203 | vmeTsi148OutboundPortsShowXX(BERegister *base, FILE *f); |
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| 204 | |
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| 205 | void |
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| 206 | vmeTsi148OutboundPortsShow(FILE *f); |
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| 207 | |
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| 208 | /* Print the current configuration of all inbound ports to |
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| 209 | * f (stdout if NULL) |
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| 210 | */ |
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| 211 | |
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| 212 | void |
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| 213 | vmeTsi148InboundPortsShowXX(BERegister *base, FILE *f); |
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| 214 | |
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| 215 | void |
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| 216 | vmeTsi148InboundPortsShow(FILE *f); |
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| 217 | |
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[43ea369] | 218 | #endif |
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| 219 | |
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[784e792] | 220 | |
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| 221 | /* Disable all in- or out-bound ports, respectively */ |
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| 222 | void |
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| 223 | vmeTsi148DisableAllInboundPortsXX(BERegister *base); |
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| 224 | |
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| 225 | void |
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| 226 | vmeTsi148DisableAllInboundPorts(void); |
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| 227 | |
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| 228 | void |
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| 229 | vmeTsi148DisableAllOutboundPortsXX(BERegister *base); |
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| 230 | |
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| 231 | void |
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| 232 | vmeTsi148DisableAllOutboundPorts(void); |
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| 233 | |
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| 234 | # define TSI_VEAT_VES (1<<31) |
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| 235 | # define TSI_VEAT_VEOF (1<<30) |
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| 236 | # define TSI_VEAT_VESCL (1<<29) |
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| 237 | # define TSI_VEAT_2eOT (1<<21) |
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| 238 | # define TSI_VEAT_2eST (1<<20) |
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| 239 | # define TSI_VEAT_BERR (1<<19) |
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| 240 | # define TSI_VEAT_LWORD (1<<18) |
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| 241 | # define TSI_VEAT_WRITE (1<<17) |
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| 242 | # define TSI_VEAT_IACK (1<<16) |
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| 243 | # define TSI_VEAT_DS1 (1<<15) |
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| 244 | # define TSI_VEAT_DS0 (1<<14) |
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| 245 | # define TSI_VEAT_AM(v) (((v)>>8)&63) |
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| 246 | # define TSI_VEAT_XAM(v) ((v)&255) |
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| 247 | |
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| 248 | /* Check and clear the error (AKA 'exception') register. |
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| 249 | * Note that the Tsi148 does *not* propagate VME bus errors of any kind to |
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| 250 | * the PCI status register and hence this routine (or registering an ISR |
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| 251 | * to the TSI_VERR_INT_VEC) is the only means for detecting a bus error. |
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| 252 | * |
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| 253 | * RETURNS: |
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| 254 | * 0 if no error has occurred since this routine was last called. |
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| 255 | * Contents of the 'VEAT' register (bit definitions as above) |
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| 256 | * otherwise. |
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[afd4c7b] | 257 | * If a non-NULL 'paddr' argument is provided then the lower 32-bit |
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| 258 | * of the error address is stored in *paddr (only if return value is |
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| 259 | * non-zero). |
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[784e792] | 260 | * |
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| 261 | * SIDE EFFECTS: this routine clears the error attribute register, allowing |
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| 262 | * for future errors to be latched. |
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| 263 | */ |
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| 264 | unsigned long |
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[afd4c7b] | 265 | vmeTsi148ClearVMEBusErrorsXX(BERegister *base, uint32_t *paddr); |
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[784e792] | 266 | |
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| 267 | unsigned long |
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[afd4c7b] | 268 | vmeTsi148ClearVMEBusErrors(uint32_t *paddr); |
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| 269 | |
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| 270 | /* Map internal register block to VME. |
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| 271 | * |
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| 272 | * This routine is intended for BSP implementors. The registers must be |
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| 273 | * accessible from VME so that the interrupt handler can flush the |
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| 274 | * bridge FIFO (see below). |
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| 275 | * |
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| 276 | * vme_base: VME address where the TSI registers (4k) can be mapped. |
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| 277 | * This VME address must fall into a range covered by |
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| 278 | * any pre-configured outbound window. |
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| 279 | * address_space: The desired VME address space. |
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| 280 | * (all of SUP/USR/PGM/DATA are always accepted). |
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| 281 | * |
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| 282 | * See NOTES [vmeTsi148InstallIrqMgrAlt()] below for further information. |
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| 283 | * |
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| 284 | * RETURNS: 0 on success, nonzero on error. It is not possible (and results |
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| 285 | * in a non-zero return code) to change the CRG VME address after |
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| 286 | * initializing the interrupt manager as it uses the CRG. |
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| 287 | */ |
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| 288 | int |
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| 289 | vmeTsi148MapCRGXX(BERegister *base, uint32_t vme_base, uint32_t address_space); |
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| 290 | |
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| 291 | int |
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| 292 | vmeTsi148MapCRG(uint32_t vme_base, uint32_t address_space); |
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| 293 | |
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[784e792] | 294 | |
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| 295 | /* VME Interrupt Handler functionality */ |
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| 296 | |
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| 297 | /* we dont use the current RTEMS/BSP interrupt API for the |
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| 298 | * following reasons: |
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| 299 | * |
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| 300 | * - RTEMS/BSP API does not pass an argument to the ISR :-( :-( |
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| 301 | * - no separate vector space for VME vectors. Some vectors would |
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| 302 | * have to overlap with existing PCI/ISA vectors. |
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| 303 | * - RTEMS/BSP API allocates a structure for every possible vector |
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| 304 | * - the irq_on(), irq_off() functions add more bloat than helping. |
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| 305 | * They are (currently) only used by the framework to disable |
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| 306 | * interrupts at the device level before removing a handler |
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| 307 | * and to enable interrupts after installing a handler. |
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| 308 | * These operations may as well be done by the driver itself. |
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| 309 | * |
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| 310 | * Hence, we maintain our own (VME) handler table and hook our PCI |
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| 311 | * handler into the standard RTEMS/BSP environment. Our handler then |
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| 312 | * dispatches VME interrupts. |
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| 313 | */ |
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| 314 | |
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| 315 | typedef void (*VmeTsi148ISR) (void *usrArg, unsigned long vector); |
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| 316 | |
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| 317 | /* install a handler for a VME vector |
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| 318 | * RETURNS 0 on success, nonzero on failure. |
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| 319 | */ |
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| 320 | int |
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| 321 | vmeTsi148InstallISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); |
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| 322 | |
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| 323 | /* remove a handler for a VME vector. The vector and usrArg parameters |
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| 324 | * must match the respective parameters used when installing the handler. |
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| 325 | * RETURNS 0 on success, nonzero on failure. |
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| 326 | */ |
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| 327 | int |
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| 328 | vmeTsi148RemoveISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); |
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| 329 | |
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| 330 | /* query for the currently installed ISR and usr parameter at a given vector |
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| 331 | * RETURNS: ISR or 0 (vector too big or no ISR installed) |
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| 332 | */ |
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| 333 | VmeTsi148ISR |
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| 334 | vmeTsi148ISRGet(unsigned long vector, void **parg); |
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| 335 | |
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| 336 | /* utility routines to enable/disable a VME IRQ level |
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| 337 | * |
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| 338 | * To enable/disable the internal interrupt sources (special vectors above) |
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| 339 | * pass a vector argument > 255. |
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| 340 | * |
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| 341 | * RETURNS 0 on success, nonzero on failure |
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| 342 | */ |
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| 343 | int |
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| 344 | vmeTsi148IntEnable(unsigned int level); |
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| 345 | |
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| 346 | int |
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| 347 | vmeTsi148IntDisable(unsigned int level); |
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| 348 | |
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| 349 | /* Check if an interrupt level or internal source is enabled: |
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| 350 | * |
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| 351 | * 'level': VME level 1..7 or internal special vector > 255 |
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| 352 | * |
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| 353 | * RETURNS: value > 0 if interrupt is currently enabled, |
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| 354 | * zero if interrupt is currently disabled, |
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| 355 | * -1 on error (invalid argument). |
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| 356 | */ |
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| 357 | |
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| 358 | int |
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| 359 | vmeTsi148IntIsEnabled(unsigned int level); |
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| 360 | |
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| 361 | /* Set IACK width (1,2, or 4 bytes) for a given interrupt level. |
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| 362 | * |
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| 363 | * 'width' arg may be 0,1,2 or 4. If zero, the currently active |
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| 364 | * value is returned but not modified. |
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| 365 | * |
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| 366 | * RETURNS: old width or -1 if invalid argument. |
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| 367 | */ |
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| 368 | |
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| 369 | int |
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| 370 | vmeTsi148SetIackWidth(int level, int width); |
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| 371 | |
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| 372 | /* Change the routing of IRQ 'level' to 'pin'. |
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| 373 | * If the BSP connects more than one of the four |
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| 374 | * physical interrupt lines from the tsi148 to |
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| 375 | * the board's PIC then you may change the physical |
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| 376 | * line a given 'level' is using. By default, |
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| 377 | * all 7 VME levels use the first wire (pin==0) and |
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| 378 | * all internal sources use the (optional) second |
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| 379 | * wire (pin==1) [The driver doesn't support more than |
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| 380 | * four wires]. |
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| 381 | * This feature is useful if you want to make use of |
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| 382 | * different hardware priorities of the PIC. Let's |
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| 383 | * say you want to give IRQ level 7 the highest priority. |
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| 384 | * You could then give 'pin 0' a higher priority (at the |
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| 385 | * PIC) and 'pin 1' a lower priority and issue. |
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| 386 | * |
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| 387 | * for ( i=1; i<7; i++ ) vmeTsi148IntRoute(i, 1); |
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| 388 | * |
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| 389 | * PARAMETERS: |
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| 390 | * 'level' : VME interrupt level '1..7' or one of |
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| 391 | * the internal sources. Pass the internal |
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| 392 | * source's vector number (>=256). |
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| 393 | * 'pin' : a value of 0 routes the requested IRQ to |
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| 394 | * the first line registered with the manager, |
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| 395 | * a value of 1 routes it to the second wire |
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| 396 | * etc. |
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| 397 | * |
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| 398 | * RETURNS: 0 on success, nonzero on error (invalid arguments) |
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| 399 | * |
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| 400 | * NOTES: - DONT change the tsi148 'map' registers |
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| 401 | * directly. The driver caches routing internally. |
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| 402 | * - support for the extra wires (beyond wire #0) is |
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| 403 | * board dependent. If the board only provides |
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| 404 | * a single physical wire from the tsi148 to |
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| 405 | * the PIC then the feature might not be available. |
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| 406 | */ |
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| 407 | int |
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| 408 | vmeTsi148IntRoute(unsigned int level, unsigned int pin); |
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| 409 | |
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| 410 | /* Raise a VME Interrupt at 'level' and respond with 'vector' to a |
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| 411 | * handler on the VME bus. (The handler could be a different board |
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| 412 | * or the tsi148 itself. |
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| 413 | * |
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| 414 | * Note that you could install a interrupt handler at TSI_VME_SW_IACK_INT_VEC |
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| 415 | * to be notified of an IACK cycle having completed. |
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| 416 | * |
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| 417 | * This routine is mainly FOR TESTING. |
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| 418 | * |
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| 419 | * NOTES: |
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| 420 | * - the VICR register is modified. |
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| 421 | * - NO MUTUAL EXCLUSION PROTECTION (reads VICR, modifies then writes back). |
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| 422 | * If several users need access to VICR it is their responsibility to serialize access. |
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| 423 | * |
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| 424 | * Arguments: |
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| 425 | * 'level': interrupt level, 1..7 |
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| 426 | * 'vector': vector number (0..255) that the tsi148 puts on the bus in response to |
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| 427 | * an IACK cycle. |
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| 428 | * |
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| 429 | * RETURNS: |
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| 430 | * 0: Success |
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| 431 | * -1: Invalid argument (level not 1..7, vector >= 256) |
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| 432 | * -2: Interrupt 'level' already asserted (maybe nobody handles it). |
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| 433 | * You can manually clear it be setting the IRQC bit in |
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| 434 | * VICR. Make sure really nobody responds to avoid spurious |
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| 435 | * interrupts (consult tsi148 docs). |
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| 436 | */ |
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| 437 | |
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| 438 | int |
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| 439 | vmeTsi148IntRaiseXX(BERegister *base, int level, unsigned vector); |
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| 440 | |
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| 441 | int |
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| 442 | vmeTsi148IntRaise(int level, unsigned vector); |
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| 443 | |
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| 444 | /* Loopback test of the VME interrupt subsystem. |
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| 445 | * - installs ISRs on 'vector' and on TSI_VME_SW_IACK_INT_VEC |
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| 446 | * - asserts VME interrupt 'level' |
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| 447 | * - waits for both interrupts: 'ordinary' VME interrupt of 'level' and |
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| 448 | * IACK completion interrupt ('special' vector TSI_VME_SW_IACK_INT_VEC). |
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| 449 | * |
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| 450 | * NOTES: |
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| 451 | * - make sure no other handler responds to 'level'. |
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| 452 | * - make sure no ISR is installed on both vectors yet. |
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| 453 | * - ISRs installed by this routine are removed after completion. |
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| 454 | * - no concurrent access protection of all involved resources |
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| 455 | * (levels, vectors and registers [see vmeTsi148IntRaise()]) |
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| 456 | * is implemented. |
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| 457 | * - this routine is intended for TESTING (when implementing new BSPs etc.). |
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| 458 | * - one RTEMS message queue is temporarily used (created/deleted). |
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| 459 | * |
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| 460 | * RETURNS: |
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| 461 | * 0: Success. |
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| 462 | * -1: Invalid arguments. |
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| 463 | * 1: Test failed (outstanding interrupts). |
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| 464 | * rtems_status_code: Failed RTEMS directive. |
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| 465 | */ |
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| 466 | |
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| 467 | int |
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| 468 | vmeTsi148IntLoopbackTst(int level, unsigned vector); |
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| 469 | |
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| 470 | /* use these special vectors to connect a handler to the |
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| 471 | * tsi148 specific interrupts (such as "DMA done", SW or |
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| 472 | * error irqs etc.) |
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| 473 | * NOTE: The wrapper clears all status LINT bits (except |
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| 474 | * for regular VME irqs). Also note that it is the user's |
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| 475 | * responsibility to enable the necessary interrupts in |
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| 476 | * LINT_EN |
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| 477 | * |
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| 478 | * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
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| 479 | * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER |
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| 480 | * DEPENDS ON IT |
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| 481 | * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
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| 482 | * |
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| 483 | * Deliberately, these vectors match the universe driver's |
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| 484 | */ |
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| 485 | /* 256 no VOWN interrupt */ |
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| 486 | #define TSI_DMA_INT_VEC 257 |
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| 487 | #define TSI_LERR_INT_VEC 258 |
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| 488 | #define TSI_VERR_INT_VEC 259 |
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| 489 | /* 260 is reserved */ |
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| 490 | #define TSI_VME_SW_IACK_INT_VEC 261 |
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| 491 | /* 262 no PCI SW IRQ */ |
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| 492 | #define TSI_SYSFAIL_INT_VEC 263 |
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| 493 | #define TSI_ACFAIL_INT_VEC 264 |
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| 494 | #define TSI_MBOX0_INT_VEC 265 |
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| 495 | #define TSI_MBOX1_INT_VEC 266 |
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| 496 | #define TSI_MBOX2_INT_VEC 267 |
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| 497 | #define TSI_MBOX3_INT_VEC 268 |
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| 498 | #define TSI_LM0_INT_VEC 269 |
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| 499 | #define TSI_LM1_INT_VEC 270 |
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| 500 | #define TSI_LM2_INT_VEC 271 |
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| 501 | #define TSI_LM3_INT_VEC 272 |
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| 502 | |
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| 503 | /* New vectors; only on TSI148 */ |
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| 504 | #define TSI_VIES_INT_VEC 273 |
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| 505 | #define TSI_DMA1_INT_VEC 274 |
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| 506 | |
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| 507 | #define TSI_NUM_INT_VECS 275 |
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| 508 | |
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[afd4c7b] | 509 | #ifdef __INSIDE_RTEMS_BSP__ |
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| 510 | |
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| 511 | #include <stdarg.h> |
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| 512 | |
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[784e792] | 513 | /* the tsi148 interrupt handler is capable of routing all sorts of |
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| 514 | * (VME) interrupts to 4 different lines (some of) which may be hooked up |
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| 515 | * in a (board specific) way to a PIC. |
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| 516 | * |
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| 517 | * This driver initially supports at most two lines (i.e., if the user |
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| 518 | * doesn't re-route anything). By default, it routes the |
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| 519 | * 7 VME interrupts to the main line and optionally, it routes the 'special' |
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| 520 | * interrupts generated by the tsi148 itself (DMA done, SW irq etc.) |
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| 521 | * to a second line. If no second line is available, all IRQs are routed |
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| 522 | * to the main line. |
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| 523 | * |
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| 524 | * The routing of interrupts to the two lines can be modified (using |
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| 525 | * the vmeTsi148IntRoute() call - see above - i.e., to make use of |
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| 526 | * different hardware priorities and/or more physically available lines. |
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| 527 | * |
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| 528 | * Because the driver has no way to figure out which lines are actually |
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| 529 | * wired to the PIC, this information has to be provided when installing |
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| 530 | * the manager. |
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| 531 | * |
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| 532 | * Hence the manager sets up routing VME interrupts to 1 or 2 tsi148 |
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| 533 | * OUTPUTS. However, it must also be told to which PIC INPUTS they |
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| 534 | * are wired. |
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| 535 | * Optionally, the first PIC input line can be read from PCI config space |
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| 536 | * but the second must be passed to this routine. Note that the info read |
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| 537 | * from PCI config space is wrong for some boards! |
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| 538 | * |
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| 539 | * PARAMETERS: |
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[afd4c7b] | 540 | * flags: VMETSI148_IRQ_MGR_FLAG_SHARED: |
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| 541 | * use the BSP_install_rtems_shared_irq_handler() instead |
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[784e792] | 542 | * of BSP_install_rtems_irq_handler(). Use this if the PIC |
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| 543 | * line is used by other devices, too. |
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| 544 | * CAVEAT: shared interrupts need RTEMS workspace, i.e., the |
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| 545 | * VME interrupt manager can only be installed |
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| 546 | * *after workspace is initialized* if 'shared' is nonzero |
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| 547 | * (i.e., *not* from bspstart()). |
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[afd4c7b] | 548 | * |
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[784e792] | 549 | * tsi_pin_0: to which output pin (of the tsi148) should the 7 |
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| 550 | * VME irq levels be routed. |
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[afd4c7b] | 551 | * |
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[784e792] | 552 | * pic_pin_0: specifies to which PIC input the 'main' output is |
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| 553 | * wired on your board. If passed a value < 0, the driver |
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| 554 | * reads this information from PCI config space ("IRQ line"). |
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| 555 | * ... : up to three additional tsi_pin/pic_pin pairs can be |
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| 556 | * specified if your board provides more physical wires. |
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| 557 | * In any case must the varargs list be terminated by '-1'. |
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| 558 | * |
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| 559 | * RETURNS: 0 on success, -1 on failure. |
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[afd4c7b] | 560 | * |
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| 561 | * NOTES: The Tsi148 always does 'posted' writes through a FIFO buffer. |
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| 562 | * This effectively makes VME write operations asynchronous |
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| 563 | * which can have undesired side-effects. |
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| 564 | * In particular, consider the case of an ISR clearing the |
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| 565 | * interrupt condition by writing to a CSR. The write operation |
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| 566 | * doesn't really do anything but goes into the FIFO and |
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| 567 | * the user ISR returns. At this point, the interrupt manager |
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| 568 | * may find the IRQ still pending, trying another IACK |
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| 569 | * cycle. Because it is probable that at this time the FIFO |
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| 570 | * has been flushed and the CSR-write operation been effective, |
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| 571 | * the IACK then times out. |
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| 572 | * Note that this phenomenon becomes more obvious as CPUs |
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| 573 | * become faster. |
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| 574 | * |
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| 575 | * To avoid this race condition and many VME drivers having |
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| 576 | * to be re-written, a VME read (having the desired side-effect |
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| 577 | * of flushing the write FIFO) must be issued between the |
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| 578 | * user ISR returning and the interrupt manager checking for |
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| 579 | * more pending interrupts. |
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| 580 | * |
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| 581 | * Therefore, the BSP needs to map the Tsi148 register |
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| 582 | * block to VME so that a read over VME can be effectuated. |
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| 583 | * (In addition to being mapped to VME, the mapped address |
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| 584 | * range must be accessible through an outbound window.) |
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[784e792] | 585 | */ |
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[afd4c7b] | 586 | |
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| 587 | #define VMETSI148_IRQ_MGR_FLAG_SHARED 1 |
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[784e792] | 588 | int |
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| 589 | vmeTsi148InstallIrqMgrAlt(int shared, int tsi_pin0, int pic_pin0, ...); |
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| 590 | |
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| 591 | int |
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| 592 | vmeTsi148InstallIrqMgrVa(int shared, int tsi_pin0, int pic_pin0, va_list ap); |
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[afd4c7b] | 593 | #endif |
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[784e792] | 594 | |
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| 595 | #ifdef __cplusplus |
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| 596 | } |
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| 597 | #endif |
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| 598 | |
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| 599 | #endif |
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