[784e792] | 1 | /* $Id$ */ |
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| 2 | #ifndef VME_TSI148_DRIVER_H |
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| 3 | #define VME_TSI148_DRIVER_H |
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| 4 | |
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[adac8ab] | 5 | /* Driver for the Tundra Tsi148 pci-vme bridge */ |
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| 6 | |
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| 7 | /* |
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| 8 | * Authorship |
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| 9 | * ---------- |
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| 10 | * This software was created by |
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| 11 | * Till Straumann <strauman@slac.stanford.edu>, 2005-2007, |
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| 12 | * Stanford Linear Accelerator Center, Stanford University. |
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| 13 | * |
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| 14 | * Acknowledgement of sponsorship |
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| 15 | * ------------------------------ |
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| 16 | * This software was produced by |
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| 17 | * the Stanford Linear Accelerator Center, Stanford University, |
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| 18 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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| 19 | * |
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| 20 | * Government disclaimer of liability |
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| 21 | * ---------------------------------- |
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| 22 | * Neither the United States nor the United States Department of Energy, |
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| 23 | * nor any of their employees, makes any warranty, express or implied, or |
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| 24 | * assumes any legal liability or responsibility for the accuracy, |
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| 25 | * completeness, or usefulness of any data, apparatus, product, or process |
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| 26 | * disclosed, or represents that its use would not infringe privately owned |
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| 27 | * rights. |
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| 28 | * |
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| 29 | * Stanford disclaimer of liability |
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| 30 | * -------------------------------- |
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| 31 | * Stanford University makes no representations or warranties, express or |
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| 32 | * implied, nor assumes any liability for the use of this software. |
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| 33 | * |
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| 34 | * Stanford disclaimer of copyright |
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| 35 | * -------------------------------- |
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| 36 | * Stanford University, owner of the copyright, hereby disclaims its |
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| 37 | * copyright and all other rights in this software. Hence, anyone may |
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| 38 | * freely use it for any purpose without restriction. |
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| 39 | * |
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| 40 | * Maintenance of notices |
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| 41 | * ---------------------- |
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| 42 | * In the interest of clarity regarding the origin and status of this |
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| 43 | * SLAC software, this and all the preceding Stanford University notices |
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| 44 | * are to remain affixed to any copy or derivative of this software made |
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| 45 | * or distributed by the recipient and are to be affixed to any copy of |
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| 46 | * software made or distributed by the recipient that contains a copy or |
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| 47 | * derivative of this software. |
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| 48 | * |
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| 49 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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| 50 | */ |
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[784e792] | 51 | |
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[afd4c7b] | 52 | #include <stdint.h> |
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[784e792] | 53 | #include <bsp/vme_am_defs.h> |
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| 54 | |
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[afd4c7b] | 55 | |
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[784e792] | 56 | /* NOTE: A64 currently not implemented */ |
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| 57 | |
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| 58 | /* These can be ored with the AM */ |
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| 59 | |
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[afd4c7b] | 60 | /* NOTE: unlike the universe, the tsi148 doesn't allow for disabling posted writes ! */ |
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[784e792] | 61 | |
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[afd4c7b] | 62 | #define VME_MODE_PREFETCH_ENABLE VME_AM_IS_MEMORY |
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| 63 | #define _LD_VME_MODE_PREFETCHSZ 24 |
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| 64 | #define VME_MODE_PREFETCH_SIZE(x) (((x)&3)<<_LD_VME_MODE_PREFETCHSZ) |
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[784e792] | 65 | |
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[afd4c7b] | 66 | /* These bits can be or'ed with the address-modifier when calling |
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| 67 | * the 'XlateAddr' routine below to further qualify the |
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| 68 | * search criteria. |
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[784e792] | 69 | */ |
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[afd4c7b] | 70 | #define VME_MODE_MATCH_MASK (3<<30) |
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| 71 | #define VME_MODE_EXACT_MATCH (2<<30) /* all bits must match */ |
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| 72 | #define VME_MODE_AS_MATCH (1<<30) /* only A16/24/32 must match */ |
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[784e792] | 73 | |
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| 74 | #ifdef __cplusplus |
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| 75 | extern "C" { |
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| 76 | #endif |
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| 77 | |
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[c2fc65b] | 78 | typedef volatile uint32_t BERegister; /* emphasize contents are big endian */ |
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[784e792] | 79 | |
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| 80 | /* |
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| 81 | * Scan the PCI busses for the Nth (N=='instance') Tsi148 VME bridge. |
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| 82 | * |
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| 83 | * RETURNS: |
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| 84 | * contents of the IRQ_LINE PCI config register on Success, |
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| 85 | * the base address of the Tsi148 register block is stored in |
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| 86 | * *pbase. |
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| 87 | * -1 on error (no Tsi found, error accessing PCI config space). |
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| 88 | * |
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| 89 | * SIDE_EFFECTS: PCI busmaster and response to memory addresses is enabled. |
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| 90 | */ |
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| 91 | int |
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| 92 | vmeTsi148FindPciBase(int instance, BERegister **pbase); |
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| 93 | |
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| 94 | /* Initialize driver for Nth Tsi148 device found. |
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| 95 | * This routine does not change any registers but |
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| 96 | * just scans the PCI bus for Tsi bridges and initializes |
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| 97 | * a driver slot. |
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| 98 | * |
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| 99 | * RETURNS: 0 on success, nonzero on error (or if no Tsi148 |
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| 100 | * device is found). |
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| 101 | */ |
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| 102 | int |
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| 103 | vmeTsi148InitInstance(unsigned instance); |
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| 104 | |
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| 105 | /* Initialize driver with 1st Tsi148 bridge found |
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| 106 | * RETURNS: (see vmeTsi148InitInstance()). |
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| 107 | */ |
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| 108 | int |
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| 109 | vmeTsi148Init(void); |
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| 110 | |
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| 111 | /* setup the tsi148 chip, i.e. disable most of its |
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| 112 | * mappings, reset interrupts etc. |
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| 113 | */ |
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| 114 | void |
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| 115 | vmeTsi148ResetXX(BERegister *base); |
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| 116 | |
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| 117 | /* setup the tsi148 connected to the first driver slot */ |
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| 118 | void |
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| 119 | vmeTsi148Reset(); |
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| 120 | |
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| 121 | /* NOTE: all non-'XX' versions of driver entry points which |
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| 122 | * have an associated 'XX' entry point operate on the |
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| 123 | * device connected to the 1st driver slot. |
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| 124 | */ |
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| 125 | |
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| 126 | /* configure a outbound port |
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| 127 | * |
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| 128 | * port: port number 0..7 |
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| 129 | * |
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| 130 | * address_space: vxWorks compliant addressing mode identifier |
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| 131 | * (see vme.h). The most important are: |
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| 132 | * 0x0d - A32, Sup, Data |
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| 133 | * 0x3d - A24, Sup, Data |
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| 134 | * 0x2d - A16, Sup, Data |
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| 135 | * additionally, the value 0 is accepted; it will |
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| 136 | * disable this port. |
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| 137 | * vme_address: address on the vme_bus of this port. |
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| 138 | * local_address: address on the pci_bus of this port. |
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| 139 | * length: size of this port. |
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| 140 | * |
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| 141 | * NOTE: the addresses and length parameters must meet certain alignment |
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| 142 | * requirements (see Tsi148 documentation). |
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| 143 | * |
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| 144 | * RETURNS: 0 on success, -1 on failure. Error messages printed to stderr. |
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| 145 | */ |
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| 146 | |
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| 147 | int |
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| 148 | vmeTsi148OutboundPortCfgXX( |
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| 149 | BERegister *base, |
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| 150 | unsigned long port, |
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| 151 | unsigned long address_space, |
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| 152 | unsigned long vme_address, |
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| 153 | unsigned long pci_address, |
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| 154 | unsigned long length); |
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| 155 | |
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| 156 | int |
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| 157 | vmeTsi148OutboundPortCfg( |
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| 158 | unsigned long port, |
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| 159 | unsigned long address_space, |
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| 160 | unsigned long vme_address, |
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| 161 | unsigned long pci_address, |
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| 162 | unsigned long length); |
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| 163 | |
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| 164 | |
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| 165 | /* configure a VME inbound (PCI master) port */ |
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| 166 | int |
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| 167 | vmeTsi148InboundPortCfgXX( |
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| 168 | BERegister *base, |
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| 169 | unsigned long port, |
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| 170 | unsigned long address_space, |
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| 171 | unsigned long vme_address, |
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| 172 | unsigned long pci_address, |
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| 173 | unsigned long length); |
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| 174 | |
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| 175 | int |
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| 176 | vmeTsi148InboundPortCfg( |
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| 177 | unsigned long port, |
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| 178 | unsigned long address_space, |
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| 179 | unsigned long vme_address, |
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| 180 | unsigned long pci_address, |
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| 181 | unsigned long length); |
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| 182 | |
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| 183 | /* Translate an address through the bridge |
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| 184 | * |
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| 185 | * vmeTsi248XlateAddr(0,0,as,addr,&result) |
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| 186 | * yields a VME a address that reflects |
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| 187 | * a local memory location as seen from the VME bus through the |
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| 188 | * tsi148 VME inbound port. |
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| 189 | * |
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| 190 | * Likewise does vmeTsi148XlateAddr(1,0,as,addr,&result) |
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| 191 | * translate a VME bus addr (backwards, through the VME outbound |
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| 192 | * port) to the PCI side of the bridge. |
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| 193 | * |
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| 194 | * A valid address space modifier must be specified. |
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| 195 | * If VME_MODE_EXACT_MATCH is set, all the mode bits must |
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| 196 | * match the requested mode. If VME_MODE_EXACT_MATCH is not |
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| 197 | * set in the mode word, only the basic mode (address-space, |
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| 198 | * sup/usr and pgm/data) is compared. |
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| 199 | * |
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| 200 | * The 'reverse' parameter may be used to find a reverse |
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| 201 | * mapping, i.e. the pci address in a outbound window can be |
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| 202 | * found if the respective vme address is known etc. |
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| 203 | * |
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| 204 | * RETURNS: translated address in *pbusAdrs / *plocalAdrs |
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| 205 | * |
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| 206 | * 0: success |
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| 207 | * -1: address/modifier not found in any bridge port |
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| 208 | * -2: invalid modifier |
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| 209 | */ |
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| 210 | |
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| 211 | int |
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| 212 | vmeTsi148XlateAddrXX( |
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| 213 | BERegister *base, /* TSI 148 base address */ |
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| 214 | int outbound, /* look in the outbound windows */ |
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| 215 | int reverse, /* reverse mapping; for outbound ports: map local to VME */ |
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| 216 | unsigned long as, /* address space */ |
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| 217 | unsigned long aIn, /* address to look up */ |
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| 218 | unsigned long *paOut/* where to put result */ |
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| 219 | ); |
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| 220 | |
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| 221 | int |
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| 222 | vmeTsi148XlateAddr( |
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| 223 | int outbound, /* look in the outbound windows */ |
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| 224 | int reverse, /* reverse mapping; for outbound: map local to VME */ |
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| 225 | unsigned long as, /* address space */ |
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| 226 | unsigned long aIn, /* address to look up */ |
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| 227 | unsigned long *paOut/* where to put result */ |
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| 228 | ); |
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| 229 | |
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[43ea369] | 230 | |
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| 231 | /* avoid pulling stdio.h into this header. |
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| 232 | * Applications that want a declaration of the |
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| 233 | * following routines should |
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| 234 | * #include <stdio.h> |
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| 235 | * #define _VME_TSI148_DECLARE_SHOW_ROUTINES |
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| 236 | * #include <vmeTsi148.h> |
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| 237 | */ |
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| 238 | #ifdef _VME_TSI148_DECLARE_SHOW_ROUTINES |
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| 239 | |
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[784e792] | 240 | /* Print the current configuration of all outbound ports to |
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| 241 | * f (stdout if NULL) |
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| 242 | */ |
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| 243 | |
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| 244 | void |
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| 245 | vmeTsi148OutboundPortsShowXX(BERegister *base, FILE *f); |
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| 246 | |
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| 247 | void |
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| 248 | vmeTsi148OutboundPortsShow(FILE *f); |
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| 249 | |
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| 250 | /* Print the current configuration of all inbound ports to |
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| 251 | * f (stdout if NULL) |
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| 252 | */ |
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| 253 | |
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| 254 | void |
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| 255 | vmeTsi148InboundPortsShowXX(BERegister *base, FILE *f); |
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| 256 | |
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| 257 | void |
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| 258 | vmeTsi148InboundPortsShow(FILE *f); |
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| 259 | |
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[43ea369] | 260 | #endif |
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| 261 | |
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[784e792] | 262 | |
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| 263 | /* Disable all in- or out-bound ports, respectively */ |
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| 264 | void |
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| 265 | vmeTsi148DisableAllInboundPortsXX(BERegister *base); |
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| 266 | |
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| 267 | void |
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| 268 | vmeTsi148DisableAllInboundPorts(void); |
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| 269 | |
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| 270 | void |
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| 271 | vmeTsi148DisableAllOutboundPortsXX(BERegister *base); |
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| 272 | |
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| 273 | void |
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| 274 | vmeTsi148DisableAllOutboundPorts(void); |
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| 275 | |
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| 276 | # define TSI_VEAT_VES (1<<31) |
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| 277 | # define TSI_VEAT_VEOF (1<<30) |
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| 278 | # define TSI_VEAT_VESCL (1<<29) |
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| 279 | # define TSI_VEAT_2eOT (1<<21) |
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| 280 | # define TSI_VEAT_2eST (1<<20) |
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| 281 | # define TSI_VEAT_BERR (1<<19) |
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| 282 | # define TSI_VEAT_LWORD (1<<18) |
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| 283 | # define TSI_VEAT_WRITE (1<<17) |
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| 284 | # define TSI_VEAT_IACK (1<<16) |
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| 285 | # define TSI_VEAT_DS1 (1<<15) |
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| 286 | # define TSI_VEAT_DS0 (1<<14) |
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| 287 | # define TSI_VEAT_AM(v) (((v)>>8)&63) |
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| 288 | # define TSI_VEAT_XAM(v) ((v)&255) |
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| 289 | |
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| 290 | /* Check and clear the error (AKA 'exception') register. |
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| 291 | * Note that the Tsi148 does *not* propagate VME bus errors of any kind to |
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| 292 | * the PCI status register and hence this routine (or registering an ISR |
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| 293 | * to the TSI_VERR_INT_VEC) is the only means for detecting a bus error. |
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| 294 | * |
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| 295 | * RETURNS: |
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| 296 | * 0 if no error has occurred since this routine was last called. |
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| 297 | * Contents of the 'VEAT' register (bit definitions as above) |
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| 298 | * otherwise. |
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[afd4c7b] | 299 | * If a non-NULL 'paddr' argument is provided then the lower 32-bit |
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| 300 | * of the error address is stored in *paddr (only if return value is |
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| 301 | * non-zero). |
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[784e792] | 302 | * |
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| 303 | * SIDE EFFECTS: this routine clears the error attribute register, allowing |
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| 304 | * for future errors to be latched. |
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| 305 | */ |
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| 306 | unsigned long |
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[afd4c7b] | 307 | vmeTsi148ClearVMEBusErrorsXX(BERegister *base, uint32_t *paddr); |
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[784e792] | 308 | |
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| 309 | unsigned long |
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[afd4c7b] | 310 | vmeTsi148ClearVMEBusErrors(uint32_t *paddr); |
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| 311 | |
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| 312 | /* Map internal register block to VME. |
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| 313 | * |
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| 314 | * This routine is intended for BSP implementors. The registers must be |
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| 315 | * accessible from VME so that the interrupt handler can flush the |
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| 316 | * bridge FIFO (see below). |
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| 317 | * |
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| 318 | * vme_base: VME address where the TSI registers (4k) can be mapped. |
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| 319 | * This VME address must fall into a range covered by |
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| 320 | * any pre-configured outbound window. |
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| 321 | * address_space: The desired VME address space. |
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| 322 | * (all of SUP/USR/PGM/DATA are always accepted). |
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| 323 | * |
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| 324 | * See NOTES [vmeTsi148InstallIrqMgrAlt()] below for further information. |
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| 325 | * |
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| 326 | * RETURNS: 0 on success, nonzero on error. It is not possible (and results |
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| 327 | * in a non-zero return code) to change the CRG VME address after |
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| 328 | * initializing the interrupt manager as it uses the CRG. |
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| 329 | */ |
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| 330 | int |
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| 331 | vmeTsi148MapCRGXX(BERegister *base, uint32_t vme_base, uint32_t address_space); |
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| 332 | |
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| 333 | int |
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| 334 | vmeTsi148MapCRG(uint32_t vme_base, uint32_t address_space); |
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| 335 | |
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[784e792] | 336 | |
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| 337 | /* VME Interrupt Handler functionality */ |
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| 338 | |
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| 339 | /* we dont use the current RTEMS/BSP interrupt API for the |
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| 340 | * following reasons: |
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| 341 | * |
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| 342 | * - RTEMS/BSP API does not pass an argument to the ISR :-( :-( |
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| 343 | * - no separate vector space for VME vectors. Some vectors would |
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| 344 | * have to overlap with existing PCI/ISA vectors. |
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| 345 | * - RTEMS/BSP API allocates a structure for every possible vector |
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| 346 | * - the irq_on(), irq_off() functions add more bloat than helping. |
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| 347 | * They are (currently) only used by the framework to disable |
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| 348 | * interrupts at the device level before removing a handler |
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| 349 | * and to enable interrupts after installing a handler. |
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| 350 | * These operations may as well be done by the driver itself. |
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| 351 | * |
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| 352 | * Hence, we maintain our own (VME) handler table and hook our PCI |
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| 353 | * handler into the standard RTEMS/BSP environment. Our handler then |
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| 354 | * dispatches VME interrupts. |
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| 355 | */ |
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| 356 | |
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| 357 | typedef void (*VmeTsi148ISR) (void *usrArg, unsigned long vector); |
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| 358 | |
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| 359 | /* install a handler for a VME vector |
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| 360 | * RETURNS 0 on success, nonzero on failure. |
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| 361 | */ |
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| 362 | int |
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| 363 | vmeTsi148InstallISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); |
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| 364 | |
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| 365 | /* remove a handler for a VME vector. The vector and usrArg parameters |
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| 366 | * must match the respective parameters used when installing the handler. |
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| 367 | * RETURNS 0 on success, nonzero on failure. |
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| 368 | */ |
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| 369 | int |
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| 370 | vmeTsi148RemoveISR(unsigned long vector, VmeTsi148ISR handler, void *usrArg); |
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| 371 | |
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| 372 | /* query for the currently installed ISR and usr parameter at a given vector |
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| 373 | * RETURNS: ISR or 0 (vector too big or no ISR installed) |
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| 374 | */ |
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| 375 | VmeTsi148ISR |
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| 376 | vmeTsi148ISRGet(unsigned long vector, void **parg); |
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| 377 | |
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| 378 | /* utility routines to enable/disable a VME IRQ level |
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| 379 | * |
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| 380 | * To enable/disable the internal interrupt sources (special vectors above) |
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| 381 | * pass a vector argument > 255. |
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| 382 | * |
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| 383 | * RETURNS 0 on success, nonzero on failure |
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| 384 | */ |
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| 385 | int |
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| 386 | vmeTsi148IntEnable(unsigned int level); |
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| 387 | |
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| 388 | int |
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| 389 | vmeTsi148IntDisable(unsigned int level); |
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| 390 | |
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| 391 | /* Check if an interrupt level or internal source is enabled: |
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| 392 | * |
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| 393 | * 'level': VME level 1..7 or internal special vector > 255 |
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| 394 | * |
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| 395 | * RETURNS: value > 0 if interrupt is currently enabled, |
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| 396 | * zero if interrupt is currently disabled, |
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| 397 | * -1 on error (invalid argument). |
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| 398 | */ |
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| 399 | |
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| 400 | int |
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| 401 | vmeTsi148IntIsEnabled(unsigned int level); |
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| 402 | |
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| 403 | /* Set IACK width (1,2, or 4 bytes) for a given interrupt level. |
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| 404 | * |
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| 405 | * 'width' arg may be 0,1,2 or 4. If zero, the currently active |
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| 406 | * value is returned but not modified. |
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| 407 | * |
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| 408 | * RETURNS: old width or -1 if invalid argument. |
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| 409 | */ |
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| 410 | |
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| 411 | int |
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| 412 | vmeTsi148SetIackWidth(int level, int width); |
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| 413 | |
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| 414 | /* Change the routing of IRQ 'level' to 'pin'. |
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| 415 | * If the BSP connects more than one of the four |
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| 416 | * physical interrupt lines from the tsi148 to |
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| 417 | * the board's PIC then you may change the physical |
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| 418 | * line a given 'level' is using. By default, |
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| 419 | * all 7 VME levels use the first wire (pin==0) and |
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| 420 | * all internal sources use the (optional) second |
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| 421 | * wire (pin==1) [The driver doesn't support more than |
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| 422 | * four wires]. |
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| 423 | * This feature is useful if you want to make use of |
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| 424 | * different hardware priorities of the PIC. Let's |
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| 425 | * say you want to give IRQ level 7 the highest priority. |
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| 426 | * You could then give 'pin 0' a higher priority (at the |
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| 427 | * PIC) and 'pin 1' a lower priority and issue. |
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| 428 | * |
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| 429 | * for ( i=1; i<7; i++ ) vmeTsi148IntRoute(i, 1); |
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| 430 | * |
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| 431 | * PARAMETERS: |
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| 432 | * 'level' : VME interrupt level '1..7' or one of |
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| 433 | * the internal sources. Pass the internal |
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| 434 | * source's vector number (>=256). |
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| 435 | * 'pin' : a value of 0 routes the requested IRQ to |
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| 436 | * the first line registered with the manager, |
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| 437 | * a value of 1 routes it to the second wire |
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| 438 | * etc. |
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| 439 | * |
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| 440 | * RETURNS: 0 on success, nonzero on error (invalid arguments) |
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| 441 | * |
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| 442 | * NOTES: - DONT change the tsi148 'map' registers |
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| 443 | * directly. The driver caches routing internally. |
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| 444 | * - support for the extra wires (beyond wire #0) is |
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| 445 | * board dependent. If the board only provides |
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| 446 | * a single physical wire from the tsi148 to |
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| 447 | * the PIC then the feature might not be available. |
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| 448 | */ |
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| 449 | int |
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| 450 | vmeTsi148IntRoute(unsigned int level, unsigned int pin); |
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| 451 | |
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| 452 | /* Raise a VME Interrupt at 'level' and respond with 'vector' to a |
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| 453 | * handler on the VME bus. (The handler could be a different board |
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| 454 | * or the tsi148 itself. |
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| 455 | * |
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| 456 | * Note that you could install a interrupt handler at TSI_VME_SW_IACK_INT_VEC |
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| 457 | * to be notified of an IACK cycle having completed. |
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| 458 | * |
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| 459 | * This routine is mainly FOR TESTING. |
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| 460 | * |
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| 461 | * NOTES: |
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| 462 | * - the VICR register is modified. |
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| 463 | * - NO MUTUAL EXCLUSION PROTECTION (reads VICR, modifies then writes back). |
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| 464 | * If several users need access to VICR it is their responsibility to serialize access. |
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| 465 | * |
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| 466 | * Arguments: |
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| 467 | * 'level': interrupt level, 1..7 |
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| 468 | * 'vector': vector number (0..255) that the tsi148 puts on the bus in response to |
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| 469 | * an IACK cycle. |
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| 470 | * |
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| 471 | * RETURNS: |
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| 472 | * 0: Success |
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| 473 | * -1: Invalid argument (level not 1..7, vector >= 256) |
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| 474 | * -2: Interrupt 'level' already asserted (maybe nobody handles it). |
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| 475 | * You can manually clear it be setting the IRQC bit in |
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| 476 | * VICR. Make sure really nobody responds to avoid spurious |
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| 477 | * interrupts (consult tsi148 docs). |
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| 478 | */ |
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| 479 | |
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| 480 | int |
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| 481 | vmeTsi148IntRaiseXX(BERegister *base, int level, unsigned vector); |
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| 482 | |
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| 483 | int |
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| 484 | vmeTsi148IntRaise(int level, unsigned vector); |
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| 485 | |
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| 486 | /* Loopback test of the VME interrupt subsystem. |
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| 487 | * - installs ISRs on 'vector' and on TSI_VME_SW_IACK_INT_VEC |
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| 488 | * - asserts VME interrupt 'level' |
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| 489 | * - waits for both interrupts: 'ordinary' VME interrupt of 'level' and |
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| 490 | * IACK completion interrupt ('special' vector TSI_VME_SW_IACK_INT_VEC). |
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| 491 | * |
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| 492 | * NOTES: |
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| 493 | * - make sure no other handler responds to 'level'. |
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| 494 | * - make sure no ISR is installed on both vectors yet. |
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| 495 | * - ISRs installed by this routine are removed after completion. |
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| 496 | * - no concurrent access protection of all involved resources |
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| 497 | * (levels, vectors and registers [see vmeTsi148IntRaise()]) |
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| 498 | * is implemented. |
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| 499 | * - this routine is intended for TESTING (when implementing new BSPs etc.). |
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| 500 | * - one RTEMS message queue is temporarily used (created/deleted). |
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| 501 | * |
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| 502 | * RETURNS: |
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| 503 | * 0: Success. |
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| 504 | * -1: Invalid arguments. |
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| 505 | * 1: Test failed (outstanding interrupts). |
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| 506 | * rtems_status_code: Failed RTEMS directive. |
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| 507 | */ |
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| 508 | |
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| 509 | int |
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| 510 | vmeTsi148IntLoopbackTst(int level, unsigned vector); |
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| 511 | |
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| 512 | /* use these special vectors to connect a handler to the |
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| 513 | * tsi148 specific interrupts (such as "DMA done", SW or |
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| 514 | * error irqs etc.) |
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| 515 | * NOTE: The wrapper clears all status LINT bits (except |
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| 516 | * for regular VME irqs). Also note that it is the user's |
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| 517 | * responsibility to enable the necessary interrupts in |
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| 518 | * LINT_EN |
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| 519 | * |
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| 520 | * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
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| 521 | * DO NOT CHANGE THE ORDER OF THESE VECTORS - THE DRIVER |
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| 522 | * DEPENDS ON IT |
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| 523 | * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
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| 524 | * |
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| 525 | * Deliberately, these vectors match the universe driver's |
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| 526 | */ |
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| 527 | /* 256 no VOWN interrupt */ |
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| 528 | #define TSI_DMA_INT_VEC 257 |
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| 529 | #define TSI_LERR_INT_VEC 258 |
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| 530 | #define TSI_VERR_INT_VEC 259 |
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| 531 | /* 260 is reserved */ |
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| 532 | #define TSI_VME_SW_IACK_INT_VEC 261 |
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| 533 | /* 262 no PCI SW IRQ */ |
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| 534 | #define TSI_SYSFAIL_INT_VEC 263 |
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| 535 | #define TSI_ACFAIL_INT_VEC 264 |
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| 536 | #define TSI_MBOX0_INT_VEC 265 |
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| 537 | #define TSI_MBOX1_INT_VEC 266 |
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| 538 | #define TSI_MBOX2_INT_VEC 267 |
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| 539 | #define TSI_MBOX3_INT_VEC 268 |
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| 540 | #define TSI_LM0_INT_VEC 269 |
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| 541 | #define TSI_LM1_INT_VEC 270 |
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| 542 | #define TSI_LM2_INT_VEC 271 |
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| 543 | #define TSI_LM3_INT_VEC 272 |
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| 544 | |
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| 545 | /* New vectors; only on TSI148 */ |
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| 546 | #define TSI_VIES_INT_VEC 273 |
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| 547 | #define TSI_DMA1_INT_VEC 274 |
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| 548 | |
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| 549 | #define TSI_NUM_INT_VECS 275 |
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| 550 | |
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[afd4c7b] | 551 | #ifdef __INSIDE_RTEMS_BSP__ |
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| 552 | |
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| 553 | #include <stdarg.h> |
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| 554 | |
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[784e792] | 555 | /* the tsi148 interrupt handler is capable of routing all sorts of |
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| 556 | * (VME) interrupts to 4 different lines (some of) which may be hooked up |
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| 557 | * in a (board specific) way to a PIC. |
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| 558 | * |
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| 559 | * This driver initially supports at most two lines (i.e., if the user |
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| 560 | * doesn't re-route anything). By default, it routes the |
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| 561 | * 7 VME interrupts to the main line and optionally, it routes the 'special' |
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| 562 | * interrupts generated by the tsi148 itself (DMA done, SW irq etc.) |
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| 563 | * to a second line. If no second line is available, all IRQs are routed |
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| 564 | * to the main line. |
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| 565 | * |
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| 566 | * The routing of interrupts to the two lines can be modified (using |
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| 567 | * the vmeTsi148IntRoute() call - see above - i.e., to make use of |
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| 568 | * different hardware priorities and/or more physically available lines. |
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| 569 | * |
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| 570 | * Because the driver has no way to figure out which lines are actually |
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| 571 | * wired to the PIC, this information has to be provided when installing |
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| 572 | * the manager. |
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| 573 | * |
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| 574 | * Hence the manager sets up routing VME interrupts to 1 or 2 tsi148 |
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| 575 | * OUTPUTS. However, it must also be told to which PIC INPUTS they |
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| 576 | * are wired. |
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| 577 | * Optionally, the first PIC input line can be read from PCI config space |
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| 578 | * but the second must be passed to this routine. Note that the info read |
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| 579 | * from PCI config space is wrong for some boards! |
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| 580 | * |
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| 581 | * PARAMETERS: |
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[afd4c7b] | 582 | * flags: VMETSI148_IRQ_MGR_FLAG_SHARED: |
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| 583 | * use the BSP_install_rtems_shared_irq_handler() instead |
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[784e792] | 584 | * of BSP_install_rtems_irq_handler(). Use this if the PIC |
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| 585 | * line is used by other devices, too. |
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| 586 | * CAVEAT: shared interrupts need RTEMS workspace, i.e., the |
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| 587 | * VME interrupt manager can only be installed |
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| 588 | * *after workspace is initialized* if 'shared' is nonzero |
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| 589 | * (i.e., *not* from bspstart()). |
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[afd4c7b] | 590 | * |
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[784e792] | 591 | * tsi_pin_0: to which output pin (of the tsi148) should the 7 |
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| 592 | * VME irq levels be routed. |
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[afd4c7b] | 593 | * |
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[784e792] | 594 | * pic_pin_0: specifies to which PIC input the 'main' output is |
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| 595 | * wired on your board. If passed a value < 0, the driver |
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| 596 | * reads this information from PCI config space ("IRQ line"). |
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| 597 | * ... : up to three additional tsi_pin/pic_pin pairs can be |
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| 598 | * specified if your board provides more physical wires. |
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| 599 | * In any case must the varargs list be terminated by '-1'. |
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| 600 | * |
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| 601 | * RETURNS: 0 on success, -1 on failure. |
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[afd4c7b] | 602 | * |
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| 603 | * NOTES: The Tsi148 always does 'posted' writes through a FIFO buffer. |
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| 604 | * This effectively makes VME write operations asynchronous |
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| 605 | * which can have undesired side-effects. |
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| 606 | * In particular, consider the case of an ISR clearing the |
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| 607 | * interrupt condition by writing to a CSR. The write operation |
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| 608 | * doesn't really do anything but goes into the FIFO and |
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| 609 | * the user ISR returns. At this point, the interrupt manager |
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| 610 | * may find the IRQ still pending, trying another IACK |
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| 611 | * cycle. Because it is probable that at this time the FIFO |
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| 612 | * has been flushed and the CSR-write operation been effective, |
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| 613 | * the IACK then times out. |
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| 614 | * Note that this phenomenon becomes more obvious as CPUs |
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| 615 | * become faster. |
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| 616 | * |
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| 617 | * To avoid this race condition and many VME drivers having |
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| 618 | * to be re-written, a VME read (having the desired side-effect |
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| 619 | * of flushing the write FIFO) must be issued between the |
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| 620 | * user ISR returning and the interrupt manager checking for |
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| 621 | * more pending interrupts. |
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| 622 | * |
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| 623 | * Therefore, the BSP needs to map the Tsi148 register |
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| 624 | * block to VME so that a read over VME can be effectuated. |
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| 625 | * (In addition to being mapped to VME, the mapped address |
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| 626 | * range must be accessible through an outbound window.) |
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[784e792] | 627 | */ |
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[afd4c7b] | 628 | |
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| 629 | #define VMETSI148_IRQ_MGR_FLAG_SHARED 1 |
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[784e792] | 630 | int |
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| 631 | vmeTsi148InstallIrqMgrAlt(int shared, int tsi_pin0, int pic_pin0, ...); |
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| 632 | |
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| 633 | int |
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| 634 | vmeTsi148InstallIrqMgrVa(int shared, int tsi_pin0, int pic_pin0, va_list ap); |
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[afd4c7b] | 635 | #endif |
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[784e792] | 636 | |
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| 637 | #ifdef __cplusplus |
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| 638 | } |
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| 639 | #endif |
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| 640 | |
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| 641 | #endif |
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