[e0ddaa7e] | 1 | /* |
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| 2 | * /dev/gdbsci[0|1] for gdb's simulator's SH sci emulation |
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| 3 | * |
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| 4 | * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany |
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| 7 | * |
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| 8 | * This program is distributed in the hope that it will be useful, |
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| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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| 15 | #include <rtems.h> |
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| 16 | |
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| 17 | #include <stdlib.h> |
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| 18 | |
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| 19 | #include <rtems/libio.h> |
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| 20 | #include <iosupp.h> |
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| 21 | #include <rtems/score/sh_io.h> |
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| 22 | /* HACK: There must be something better than this :) */ |
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| 23 | #if defined(__sh1__) |
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| 24 | #include <rtems/score/ispsh7032.h> |
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| 25 | #include <rtems/score/iosh7032.h> |
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| 26 | #elif defined(__sh2__) |
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| 27 | #include <rtems/score/ispsh7045.h> |
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| 28 | #include <rtems/score/iosh7045.h> |
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| 29 | #else |
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| 30 | #error unsupported sh model |
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| 31 | #endif |
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| 32 | #include <sh/sh7_sci.h> |
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| 33 | #include <sh/sh7_pfc.h> |
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| 34 | #include <sh/sci.h> |
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| 35 | |
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| 36 | /* |
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| 37 | * gdb assumes area 5/char access (base address & 0x0500000), |
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| 38 | * the RTEMS's sh7045 code however defaults to area 5/int/short/char access |
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| 39 | * [Very likely a bug in the sh7045 code, RC.] |
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| 40 | */ |
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| 41 | |
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| 42 | #define GDBSCI_BASE 0x05ffffff |
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| 43 | |
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| 44 | #define GDBSCI0_SMR (SCI0_SMR & GDBSCI_BASE) |
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| 45 | #define GDBSCI0_BRR (SCI0_BRR & GDBSCI_BASE) |
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| 46 | #define GDBSCI0_SCR (SCI0_SCR & GDBSCI_BASE) |
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| 47 | #define GDBSCI0_TDR (SCI0_TDR & GDBSCI_BASE) |
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| 48 | #define GDBSCI0_SSR (SCI0_SSR & GDBSCI_BASE) |
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| 49 | #define GDBSCI0_RDR (SCI0_RDR & GDBSCI_BASE) |
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| 50 | |
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| 51 | #define GDBSCI1_SMR (SCI1_SMR & GDBSCI_BASE) |
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| 52 | #define GDBSCI1_BRR (SCI1_BRR & GDBSCI_BASE) |
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| 53 | #define GDBSCI1_SCR (SCI1_SCR & GDBSCI_BASE) |
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| 54 | #define GDBSCI1_TDR (SCI1_TDR & GDBSCI_BASE) |
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| 55 | #define GDBSCI1_SSR (SCI1_SSR & GDBSCI_BASE) |
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| 56 | #define GDBSCI1_RDG (SCI1_RDR & GDBSCI_BASE) |
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| 57 | |
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| 58 | /* |
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| 59 | * NOTE: Only device 1 is valid for the simulator |
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| 60 | */ |
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| 61 | |
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| 62 | #define SH_GDBSCI_MINOR_DEVICES 2 |
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| 63 | |
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| 64 | /* Force SIGBUS by using an unsupported address for /dev/gdbsci0 */ |
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| 65 | #define SH_GDBSCI_BASE_0 SCI0_SMR |
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| 66 | #define SH_GDBSCI_BASE_1 GDBSCI1_SMR |
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| 67 | |
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| 68 | struct scidev_t { |
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| 69 | char * name ; |
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[a8a961f] | 70 | uint32_t addr ; |
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[e0ddaa7e] | 71 | rtems_device_minor_number minor ; |
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| 72 | unsigned short opened ; |
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| 73 | tcflag_t cflags ; |
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| 74 | } sci_device[SH_GDBSCI_MINOR_DEVICES] = |
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| 75 | { |
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| 76 | { "/dev/gdbsci0", SH_GDBSCI_BASE_0, 0, 0, B9600 | CS8 }, |
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| 77 | { "/dev/gdbsci1", SH_GDBSCI_BASE_1, 1, 0, B9600 | CS8 } |
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| 78 | } ; |
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| 79 | |
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| 80 | /* imported from scitab.rel */ |
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| 81 | extern int _sci_get_brparms( |
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| 82 | tcflag_t cflag, |
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| 83 | unsigned char *smr, |
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| 84 | unsigned char *brr ); |
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| 85 | |
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[09e19e6] | 86 | #if 0 |
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[e0ddaa7e] | 87 | /* Translate termios' tcflag_t into sci settings */ |
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| 88 | static int _sci_set_cflags( |
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| 89 | struct scidev_t *sci_dev, |
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| 90 | tcflag_t c_cflag ) |
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| 91 | { |
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[a8a961f] | 92 | uint8_t smr; |
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| 93 | uint8_t brr; |
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[e0ddaa7e] | 94 | |
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| 95 | if ( c_cflag & CBAUD ) |
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| 96 | { |
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| 97 | if ( _sci_get_brparms( c_cflag, &smr, &brr ) != 0 ) |
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| 98 | return -1 ; |
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| 99 | } |
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| 100 | |
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| 101 | if ( c_cflag & CSIZE ) |
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| 102 | { |
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| 103 | if ( c_cflag & CS8 ) |
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| 104 | smr &= ~SCI_SEVEN_BIT_DATA; |
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| 105 | else if ( c_cflag & CS7 ) |
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| 106 | smr |= SCI_SEVEN_BIT_DATA; |
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| 107 | else |
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| 108 | return -1 ; |
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| 109 | } |
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| 110 | |
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| 111 | if ( c_cflag & CSTOPB ) |
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| 112 | smr |= SCI_STOP_BITS_2; |
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| 113 | else |
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| 114 | smr &= ~SCI_STOP_BITS_2; |
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| 115 | |
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| 116 | if ( c_cflag & PARENB ) |
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| 117 | smr |= SCI_PARITY_ON ; |
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| 118 | else |
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| 119 | smr &= ~SCI_PARITY_ON ; |
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| 120 | |
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| 121 | if ( c_cflag & PARODD ) |
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| 122 | smr |= SCI_ODD_PARITY ; |
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| 123 | else |
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| 124 | smr &= ~SCI_ODD_PARITY; |
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| 125 | |
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| 126 | write8( smr, sci_dev->addr + SCI_SMR ); |
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| 127 | write8( brr, sci_dev->addr + SCI_BRR ); |
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| 128 | |
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| 129 | return 0 ; |
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| 130 | } |
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[09e19e6] | 131 | #endif |
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[e0ddaa7e] | 132 | |
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| 133 | static void _sci_init( |
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| 134 | rtems_device_minor_number minor ) |
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| 135 | { |
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| 136 | #if NOT_SUPPORTED_BY_GDB |
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[a8a961f] | 137 | uint16_t temp16 ; |
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[e0ddaa7e] | 138 | |
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| 139 | /* Pin function controller initialisation for asynchronous mode */ |
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| 140 | if( minor == 0) |
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| 141 | { |
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| 142 | temp16 = read16( PFC_PBCR1); |
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| 143 | temp16 &= ~( PB8MD | PB9MD ); |
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| 144 | temp16 |= (PB_TXD0 | PB_RXD0); |
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| 145 | write16( temp16, PFC_PBCR1); |
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| 146 | } |
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| 147 | else |
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| 148 | { |
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| 149 | temp16 = read16( PFC_PBCR1); |
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| 150 | temp16 &= ~( PB10MD | PB11MD); |
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| 151 | temp16 |= (PB_TXD1 | PB_RXD1); |
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| 152 | write16( temp16, PFC_PBCR1); |
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| 153 | } |
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| 154 | |
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| 155 | /* disable sck-pin */ |
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| 156 | if( minor == 0) |
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| 157 | { |
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| 158 | temp16 = read16( PFC_PBCR1); |
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| 159 | temp16 &= ~(PB12MD); |
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| 160 | write16( temp16, PFC_PBCR1); |
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| 161 | } |
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| 162 | else |
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| 163 | { |
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| 164 | temp16 = read16( PFC_PBCR1); |
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| 165 | temp16 &= ~(PB13MD); |
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| 166 | write16( temp16, PFC_PBCR1); |
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| 167 | } |
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| 168 | #endif |
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| 169 | } |
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| 170 | |
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| 171 | static void _sci_tx_polled( |
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| 172 | int minor, |
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| 173 | const char buf ) |
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| 174 | { |
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| 175 | struct scidev_t *scidev = &sci_device[minor] ; |
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| 176 | #if NOT_SUPPORTED_BY_GDB |
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[a8a961f] | 177 | int8_t ssr ; |
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[e0ddaa7e] | 178 | |
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| 179 | while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE )) |
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| 180 | ; |
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| 181 | #endif |
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| 182 | write8(buf,scidev->addr+SCI_TDR); |
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| 183 | |
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| 184 | #if NOT_SUPPORTED_BY_GDB |
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| 185 | ssr = inb(scidev->addr+SCI_SSR); |
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| 186 | ssr &= ~SCI_TDRE ; |
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| 187 | write8(ssr,scidev->addr+SCI_SSR); |
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| 188 | #endif |
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| 189 | } |
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| 190 | |
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| 191 | static int _sci_rx_polled ( |
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| 192 | int minor) |
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| 193 | { |
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| 194 | struct scidev_t *scidev = &sci_device[minor] ; |
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| 195 | |
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| 196 | unsigned char c; |
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| 197 | #if NOT_SUPPORTED_BY_GDB |
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| 198 | char ssr ; |
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| 199 | ssr = read8(scidev->addr + SCI_SSR) ; |
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| 200 | |
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| 201 | if (ssr & (SCI_PER | SCI_FER | SCI_ORER)) |
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| 202 | write8(ssr & ~(SCI_PER | SCI_FER | SCI_ORER), scidev->addr+SCI_SSR); |
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| 203 | |
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| 204 | if ( !(ssr & SCI_RDRF) ) |
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| 205 | return -1; |
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| 206 | #endif |
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| 207 | c = read8(scidev->addr + SCI_RDR) ; |
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| 208 | #if NOT_SUPPORTED_BY_GDB |
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| 209 | write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR); |
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| 210 | #endif |
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| 211 | return c; |
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| 212 | } |
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| 213 | |
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| 214 | /* |
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| 215 | * sci_initialize |
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| 216 | */ |
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| 217 | |
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| 218 | rtems_device_driver sh_gdbsci_initialize( |
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| 219 | rtems_device_major_number major, |
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| 220 | rtems_device_minor_number minor, |
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| 221 | void *arg ) |
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| 222 | { |
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| 223 | rtems_device_driver status ; |
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| 224 | rtems_device_minor_number i; |
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| 225 | |
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| 226 | /* |
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| 227 | * register all possible devices. |
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| 228 | * the initialization of the hardware is done by sci_open |
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| 229 | */ |
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| 230 | |
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| 231 | for ( i = 0 ; i < SH_GDBSCI_MINOR_DEVICES ; i++ ) |
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| 232 | { |
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| 233 | status = rtems_io_register_name( |
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| 234 | sci_device[i].name, |
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| 235 | major, |
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| 236 | sci_device[i].minor ); |
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| 237 | if (status != RTEMS_SUCCESSFUL) |
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| 238 | rtems_fatal_error_occurred(status); |
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| 239 | } |
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| 240 | |
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| 241 | /* default hardware setup */ |
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| 242 | |
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| 243 | return RTEMS_SUCCESSFUL; |
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| 244 | } |
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| 245 | |
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| 246 | |
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| 247 | /* |
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| 248 | * Open entry point |
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| 249 | */ |
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| 250 | |
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| 251 | rtems_device_driver sh_gdbsci_open( |
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| 252 | rtems_device_major_number major, |
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| 253 | rtems_device_minor_number minor, |
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| 254 | void * arg ) |
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| 255 | { |
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| 256 | #if NOT_SUPPORTED_BY_GDB |
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[a8a961f] | 257 | uint8_t temp8; |
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[e0ddaa7e] | 258 | #endif |
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| 259 | /* check for valid minor number */ |
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| 260 | if(( minor > ( SH_GDBSCI_MINOR_DEVICES -1 )) || ( minor < 0 )) |
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| 261 | { |
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| 262 | return RTEMS_INVALID_NUMBER; |
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| 263 | } |
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| 264 | |
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| 265 | /* device already opened */ |
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| 266 | if ( sci_device[minor].opened > 0 ) |
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| 267 | { |
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| 268 | sci_device[minor].opened++ ; |
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| 269 | return RTEMS_SUCCESSFUL ; |
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| 270 | } |
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| 271 | |
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| 272 | _sci_init( minor ); |
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| 273 | |
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| 274 | #if NOT_SUPPORTED_BY_GDB |
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| 275 | if (minor == 0) { |
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| 276 | temp8 = read8(sci_device[minor].addr + SCI_SCR); |
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| 277 | temp8 &= ~(SCI_TE | SCI_RE) ; |
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| 278 | write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */ |
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| 279 | _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags ); |
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| 280 | |
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| 281 | /* FIXME: Should be one bit delay */ |
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| 282 | CPU_delay(50000); /* microseconds */ |
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| 283 | |
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| 284 | temp8 |= SCI_RE | SCI_TE; |
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| 285 | write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */ |
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| 286 | } else { |
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| 287 | temp8 = read8(sci_device[minor].addr + SCI_SCR); |
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| 288 | temp8 &= ~(SCI_TE | SCI_RE) ; |
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| 289 | write8(temp8, sci_device[minor].addr + SCI_SCR); /* Clear SCR */ |
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| 290 | _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags ); |
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| 291 | |
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| 292 | /* FIXME: Should be one bit delay */ |
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| 293 | CPU_delay(50000); /* microseconds */ |
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| 294 | |
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| 295 | temp8 |= SCI_RE | SCI_TE; |
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| 296 | write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */ |
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| 297 | } |
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| 298 | #endif |
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| 299 | |
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| 300 | sci_device[minor].opened++ ; |
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| 301 | |
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| 302 | return RTEMS_SUCCESSFUL ; |
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| 303 | } |
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| 304 | |
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| 305 | /* |
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| 306 | * Close entry point |
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| 307 | */ |
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| 308 | |
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| 309 | rtems_device_driver sh_gdbsci_close( |
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| 310 | rtems_device_major_number major, |
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| 311 | rtems_device_minor_number minor, |
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| 312 | void * arg |
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| 313 | ) |
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| 314 | { |
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| 315 | if( sci_device[minor].opened == 0 ) |
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| 316 | { |
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| 317 | return RTEMS_INVALID_NUMBER; |
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| 318 | } |
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| 319 | |
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| 320 | sci_device[minor].opened-- ; |
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| 321 | |
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| 322 | return RTEMS_SUCCESSFUL ; |
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| 323 | } |
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| 324 | |
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| 325 | /* |
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| 326 | * read bytes from the serial port. |
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| 327 | */ |
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| 328 | |
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| 329 | rtems_device_driver sh_gdbsci_read( |
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| 330 | rtems_device_major_number major, |
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| 331 | rtems_device_minor_number minor, |
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| 332 | void * arg |
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| 333 | ) |
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| 334 | { |
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| 335 | int count = 0; |
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| 336 | |
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| 337 | rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg; |
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| 338 | char * buffer = rw_args->buffer; |
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| 339 | int maximum = rw_args->count; |
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| 340 | |
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| 341 | for (count = 0; count < maximum; count++) { |
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| 342 | buffer[ count ] = _sci_rx_polled(minor); |
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| 343 | if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { |
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| 344 | buffer[ count++ ] = '\n'; |
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| 345 | break; |
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| 346 | } |
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| 347 | } |
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| 348 | |
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| 349 | rw_args->bytes_moved = count; |
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| 350 | return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; |
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| 351 | } |
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| 352 | |
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| 353 | /* |
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| 354 | * write bytes to the serial port. |
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| 355 | */ |
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| 356 | |
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| 357 | rtems_device_driver sh_gdbsci_write( |
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| 358 | rtems_device_major_number major, |
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| 359 | rtems_device_minor_number minor, |
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| 360 | void * arg |
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| 361 | ) |
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| 362 | { |
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| 363 | int count; |
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| 364 | |
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| 365 | rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg; |
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| 366 | char *buffer = rw_args->buffer; |
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| 367 | int maximum = rw_args->count; |
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| 368 | |
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| 369 | for (count = 0; count < maximum; count++) { |
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| 370 | _sci_tx_polled( minor, buffer[ count ] ); |
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| 371 | } |
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| 372 | |
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| 373 | rw_args->bytes_moved = maximum; |
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| 374 | return 0; |
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| 375 | } |
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| 376 | |
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| 377 | /* |
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| 378 | * IO Control entry point |
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| 379 | */ |
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| 380 | |
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| 381 | rtems_device_driver sh_gdbsci_control( |
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| 382 | rtems_device_major_number major, |
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| 383 | rtems_device_minor_number minor, |
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| 384 | void * arg |
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| 385 | ) |
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| 386 | { |
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| 387 | /* Not yet supported */ |
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| 388 | return RTEMS_SUCCESSFUL ; |
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| 389 | } |
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